CN117832093B - Preparation method and device of shielded gate trench type power metal oxide semiconductor - Google Patents
Preparation method and device of shielded gate trench type power metal oxide semiconductor Download PDFInfo
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- CN117832093B CN117832093B CN202410239174.7A CN202410239174A CN117832093B CN 117832093 B CN117832093 B CN 117832093B CN 202410239174 A CN202410239174 A CN 202410239174A CN 117832093 B CN117832093 B CN 117832093B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 16
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 16
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- 229920005591 polysilicon Polymers 0.000 claims abstract description 56
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 230000001590 oxidative effect Effects 0.000 claims abstract description 7
- 238000000034 method Methods 0.000 claims description 31
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- -1 boron ions Chemical class 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 10
- 238000000206 photolithography Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention discloses a preparation method and a device of a shielded gate trench type power metal oxide semiconductor, which comprises the following specific steps: s1: etching a groove on the epitaxial layer, growing a bottom oxide layer on the surface of the epitaxial layer and the inner surface of the groove, and then depositing source polycrystalline silicon in the groove and etching; s2: etching the bottom oxide layer until the surface of the bottom oxide layer is flush with the surface of the source polycrystalline silicon; s3: depositing polysilicon on the surface of the epitaxial layer, the surface of the bottom oxide layer and the surface of the source polysilicon; s4: etching the polysilicon to form a polysilicon side wall residual layer, and etching the polysilicon at the side wall position to form a residual polysilicon layer; s5: oxidizing the surface of the epitaxial layer and the inner surface of the groove to form a gate oxide layer; s6: and refilling the polysilicon into the trench to form gate polysilicon. The invention reduces the capacitance Cgd2 by increasing the distance thickness between the gate and the drain, so as to achieve the technical purpose of reducing the switching loss of the input end.
Description
Technical Field
The invention belongs to the fields of electronic components, semiconductors and integrated circuits, and particularly relates to a preparation method and a device of a shield gate trench type power metal oxide semiconductor.
Background
The shield gate trench power metal oxide semiconductor (SHIELDING GATE) realizes the limit value of silicon base on medium and low voltage physics, the structure is as shown in figure 1, the Charge Balance (Charge Balance) principle is fully utilized, and the higher voltage withstand effect can be achieved by only using thinner epitaxy with lower resistance, thereby greatly reducing the on-resistance and reducing the conduction loss in a plurality of circuit applications. The source polysilicon in the trench in the structure acts as a shielding layer, and the increase in the thickness of the shielding layer causes the capacitance Cgd1 of one of the components to decrease, and Cgd1 is used as a part of the input capacitance Ciss thereof, so that the input capacitance is reduced, the switching speed of the input terminal is greatly improved, and the switching loss of the input terminal is reduced. However, the thickness of the shield layer has an influence on the pressure resistance of the module, and generally, although a thicker shield layer can be obtained by a deeper trench depth, there is a risk of lowering the pressure resistance, and therefore, there is a limit in setting the trench depth and the thickness of the shield layer.
Disclosure of Invention
In order to overcome the above-mentioned shortcomings, the present invention provides a method for preparing a trench-type power metal oxide semiconductor device with a shield gate, and the device can reduce the capacitance Cgd2 by increasing the gate-drain distance thickness, so as to achieve the technical purpose of reducing the switching loss of the input terminal.
The technical scheme adopted in the invention is as follows:
A preparation method of a shield gate trench type power metal oxide semiconductor comprises the following specific preparation steps of a trench internal structure:
S1: etching a groove on the epitaxial layer by adopting a photoetching process, growing a bottom oxide layer on the surface of the epitaxial layer and the inner surface of the groove under a certain temperature condition, and then depositing source polycrystalline silicon in the groove and carrying out etching treatment;
s2: etching the bottom oxide layer until the surface of the bottom oxide layer is flush with the surface of the source polycrystalline silicon;
s3: depositing polysilicon on the surface of the epitaxial layer, the surface of the bottom oxide layer and the surface of the source polysilicon;
s4: etching the polysilicon by adopting a dry etching process to form a polysilicon side wall residual layer in the groove, etching the polysilicon at the side wall position by utilizing a wet etching process, and forming residual polysilicon layers on two side walls of the groove on the upper surface of the bottom oxide layer;
S5: oxidizing the surface of the epitaxial layer and the inner surface of the groove to form a gate oxide layer under a certain temperature condition, and oxidizing part or all of the surface of the residual polysilicon layer to form an oxide layer;
s6: and refilling the polysilicon into the trench to form gate polysilicon.
Preferably, the method further comprises step S7: and after the gate oxide layer on the surface of the epitaxial layer is removed by adopting a wet etching process, a P-well region and an N+ well region are defined on two sides of the epitaxial layer by utilizing a two-layer photoetching process, and the N+ well region is positioned on the upper surface of the P-well region.
Preferably, the method further comprises step S8: after depositing an ILD dielectric layer on the surface of the N+ well region, defining the position of a metal contact hole by adopting a photoetching process, and depositing a metal layer so that the metal layer is contacted with the P-well region, the N+ well region and the ILD dielectric layer.
Preferably, in S1, the bottom oxide layer is grown at 900-1100 ℃.
Preferably, in S4, the height of the residual polysilicon layer is lower than the bottom surface of the P-well region.
Preferably, in the step S5, the thickness of the gate oxide layer is 0.04um to 0.1um.
Preferably, in S7, the height of the gate polysilicon is higher than the bottom surface of the n+ well region.
Preferably, in the S7, the concentration of boron ions doped in the P-well region is 6e12-3e13 cm -2, and the concentration of arsenic ions doped in the n+ well region is 5e15-2e16 cm -2.
A shield gate trench power metal oxide semiconductor device is prepared by a preparation method of a shield gate trench power metal oxide semiconductor.
The beneficial effects are that: the invention provides a preparation method and a device of a shielded gate trench type power metal oxide semiconductor, which have the following advantages:
(1) According to the invention, the capacitance Cgd2 is reduced by increasing the distance thickness between the gate electrode and the source electrode, so that the technical scheme of adding a shielding layer (shown in figure 1) is replaced, the technical purpose of reducing the switching loss of the input end is achieved, the risk of reducing the voltage resistance is avoided, the limitation is small, and the safety and the reliability of a product are improved.
(2) Compared with the production process for increasing the shielding layer and reducing Cgd1, the invention has the advantages that the number of the adopted optical layers is the same, no extra cost is generated, and the product quality is ensured on the premise of not increasing the production cost.
Drawings
Fig. 1 is a schematic diagram of a semiconductor device in the prior art;
Fig. 2 is a schematic structural diagram of step S1 in embodiment 1;
fig. 3 is a schematic structural diagram of step S2 in embodiment 1;
Fig. 4 is a schematic structural diagram of step S3 in embodiment 1;
FIG. 5 is a schematic diagram I of the structure of step S4 in example 1;
FIG. 6 is a schematic diagram II of the structure of step S4 in embodiment 1;
Fig. 7 is a schematic structural diagram of step S5 in embodiment 1;
Fig. 8 is a schematic structural diagram of step S6 in embodiment 1;
fig. 9 is a schematic structural diagram of step S7 in embodiment 1;
fig. 10 is a schematic structural diagram of step S8 in embodiment 1;
Fig. 11 is a schematic view of the structure of a semiconductor device of embodiment 1;
In the figure: epitaxial layer 100, bottom oxide layer 101, source polysilicon 102a, polysilicon 102b, polysilicon sidewall residue layer 102c, residue polysilicon layer 102d, gate polysilicon 102e, gate oxide layer 103, P-well 104, n+ well 105, ILD dielectric layer 106, metal layer 107.
Detailed Description
In order to better understand the technical solutions of the present application for those skilled in the art, the following description of the technical solutions of the embodiments of the present application will be clearly and completely described, and it is obvious that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
Embodiment 1, a method for preparing a shielded gate trench-type power metal oxide semiconductor, comprises the following steps:
S1: as shown in fig. 2, a trench is etched in the epitaxial layer 100 by using a photolithography process, and a bottom oxide layer 101 is grown on the surface of the epitaxial layer 100 and the inner surface of the trench at a temperature of 900-1100 ℃, and then source polysilicon 102a is deposited in the trench and subjected to an etching process, wherein the surface of the source polysilicon 102a is 0.8-1.5 μm below the surface of the epitaxial layer 100;
S2: as shown in fig. 3, the bottom oxide layer 101 is subjected to etching treatment until the surface of the bottom oxide layer 101 is flush with the surface of the source polysilicon 102 a;
S3: as shown in fig. 4, a layer of polysilicon 102b is deposited on the surface of the epitaxial layer 100, the surface of the bottom oxide layer 101, and the surface of the source polysilicon 102 a;
S4: as shown in fig. 5, the polysilicon 102b is etched by a dry etching process, a polysilicon sidewall residual layer 102c is formed in the trench, polysilicon at the sidewall position is etched by a wet etching process, and a residual polysilicon layer 102d is formed on both sidewalls of the trench on the upper surface of the bottom oxide layer 101, as shown in fig. 6.
S5: as shown in fig. 7, under the temperature condition of 900-1100 ℃, oxidizing the surface of the epitaxial layer 100 and the inner surface of the trench to form a gate oxide layer 103, and oxidizing the surface of the residual polysilicon layer (102 d) partially or completely at the same time to form an oxide layer; in embodiment 1, the thickness of the gate oxide layer 103 is 0.04 to 0.1um.
S6: as shown in fig. 8, the polysilicon is refilled into the trench to form gate polysilicon 102e. In a practical manufacturing process, polysilicon is typically filled into the trench to about 1 μm above the surface and then etched to the structure shown in fig. 8.
S7: as shown in fig. 9, after the gate oxide layer 103 on the surface of the epitaxial layer 100 is removed by a wet etching process, a P-well region 104 and an n+ well region 105 are defined on both sides of the epitaxial layer 100 by a two-layer photolithography process, and the n+ well region 105 is located on the upper surface of the P-well region 104. In embodiment 1, the height of the gate polysilicon 102e is higher than the bottom surface of the n+ well region 105, the boron ion concentration of the P-well region 104 is 6e12-3e13 cm -2, and the arsenic ion concentration of the n+ well region 105 is 5e15-2e16 cm -2.
S8: after depositing the ILD dielectric layer 106 on the surface of the n+ well region 105, defining a metal contact hole by using a photolithography process, as shown in fig. 10, then depositing a metal layer 107 in the metal contact hole, so that the metal layer 107 contacts the P-well region 104, the n+ well region 105 and the ILD dielectric layer 106, thereby obtaining the target product shield gate trench type power mos device, as shown in fig. 11.
In embodiment 1, the residual polysilicon layer 102d is approximately triangular, and the height of the residual polysilicon layer 102d is lower than the bottom surface of the P-well 104. In the present invention, the shape of the residual polysilicon layer 102d may be, but not limited to, a triangular shape, or may be a shape conforming to the existing requirements such as an arc shape.
In the present invention, an oxide layer corresponding to the surface of the residual polysilicon layer 102d is formed, and the capacitance Cgd2 is reduced by increasing the distance between the surface of the oxide layer and the surface of the residual polysilicon layer 102d (i.e., the gate-to-source distance d 2).
The embodiment of the invention also provides a shield gate trench type power metal oxide semiconductor device which is manufactured by adopting the manufacturing method.
The design principle of the invention is as follows:
According to the calculation formula of the capacitance C of the plate capacitor: c= (epsilon×a)/d, where epsilon is the dielectric constant, a is the area of the plates, and d is the distance between the plates, and it can be known that the capacitance Cgd2 can be reduced by increasing the thickness d2 between the gate and the source, so as to achieve the purpose of reducing the switching loss of the input terminal.
The foregoing is merely a preferred embodiment of the present invention and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present invention, which are intended to be comprehended within the scope of the present invention.
Claims (9)
1. A preparation method of a shield gate trench type power metal oxide semiconductor is characterized in that the specific preparation steps of the trench structure are as follows:
S1: etching a groove on the epitaxial layer (100) by adopting a photoetching process, growing a bottom oxide layer (101) on the surface of the epitaxial layer (100) and the inner surface of the groove under a certain temperature condition, and then depositing source polycrystalline silicon (102 a) in the groove and carrying out etching treatment;
s2: etching the bottom oxide layer (101) until the surface of the bottom oxide layer (101) is flush with the surface of the source polysilicon (102 a);
S3: depositing polysilicon (102 b) on the surface of the epitaxial layer (100), the surface of the bottom oxide layer (101) and the surface of the source polysilicon (102 a);
S4: etching the polysilicon (102 b) by adopting a dry etching process to form a polysilicon side wall residual layer (102 c) in the groove, etching the polysilicon at the side wall position by adopting a wet etching process, and forming residual polysilicon layers (102 d) on two side walls of the groove on the upper surface of the bottom oxide layer (101);
s5: oxidizing the surface of the epitaxial layer (100) and the inner surface of the groove to form a gate oxide layer (103) under a certain temperature condition, and oxidizing part or all of the surface of the residual polysilicon layer (102 d) to form an oxide layer at the same time;
s6: the polysilicon is refilled into the trench to form gate polysilicon (102 e).
2. The method for manufacturing a shield gate trench power metal oxide semiconductor as claimed in claim 1, further comprising step S7: after the gate oxide layer (103) on the surface of the epitaxial layer (100) is removed by adopting a wet etching process, a P-well region (104) and an N+ well region (105) are defined on two sides of the epitaxial layer (100) by utilizing a two-layer photoetching process, and the N+ well region (105) is positioned on the upper surface of the P-well region (104).
3. The method for manufacturing a shield gate trench power metal oxide semiconductor as claimed in claim 2, further comprising step S8: after depositing an ILD dielectric layer (106) on the surface of the N+ well region (105), defining the position of a metal contact hole by adopting a photoetching process, and then depositing a metal layer (107), so that the metal layer (107) is in contact with the P-well region (104), the N+ well region (105) and the ILD dielectric layer (106).
4. The method of claim 1, wherein in S1, the bottom oxide layer is grown at 900-1100 ℃.
5. The method of claim 1, wherein in S4, the residual polysilicon layer (102 d) is lower than the bottom surface of the P-well region (104).
6. The method of claim 1, wherein in S5, the thickness of the gate oxide layer (103) is 0.04um to 0.1um.
7. The method of claim 2, wherein in S7, the gate polysilicon (102 e) is higher than the bottom surface of the n+ well region (105).
8. The method for manufacturing a shielded gate trench power mos according to claim 2, wherein in S7, the concentration of the boron ions doped in the P-well region (104) is 6e 12-3 e13 cm -2, and the concentration of the arsenic ions doped in the n+ well region (105) is 5e 15-2 e16 cm -2.
9. A shielded gate trench power metal oxide semiconductor device prepared by the method of any one of claims 1-8.
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| CN107017167A (en) * | 2017-03-01 | 2017-08-04 | 上海华虹宏力半导体制造有限公司 | The manufacture method of trench-gate device with shield grid |
| CN108172517A (en) * | 2017-12-29 | 2018-06-15 | 中航（重庆）微电子有限公司 | A kind of shield grid groove MOSFET manufacturing method |
| CN109216172A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the division grid structure of semiconductor devices |
| CN115036358A (en) * | 2022-07-14 | 2022-09-09 | 扬杰科技(无锡)有限公司 | Novel shielded gate trench MOSFET and method of making same |
| CN115206807A (en) * | 2022-09-16 | 2022-10-18 | 华羿微电子股份有限公司 | Preparation method of medium-voltage shielded gate trench MOSFET device |
| CN115985780A (en) * | 2023-02-28 | 2023-04-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing shielding grid MOSTET |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017167A (en) * | 2017-03-01 | 2017-08-04 | 上海华虹宏力半导体制造有限公司 | The manufacture method of trench-gate device with shield grid |
| CN109216172A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The manufacturing method of the division grid structure of semiconductor devices |
| CN108172517A (en) * | 2017-12-29 | 2018-06-15 | 中航（重庆）微电子有限公司 | A kind of shield grid groove MOSFET manufacturing method |
| CN115036358A (en) * | 2022-07-14 | 2022-09-09 | 扬杰科技(无锡)有限公司 | Novel shielded gate trench MOSFET and method of making same |
| CN115206807A (en) * | 2022-09-16 | 2022-10-18 | 华羿微电子股份有限公司 | Preparation method of medium-voltage shielded gate trench MOSFET device |
| CN115985780A (en) * | 2023-02-28 | 2023-04-18 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing shielding grid MOSTET |
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