CN117457499A - Technological method for improving HDP filling of shielded gate power semiconductor device - Google Patents

Technological method for improving HDP filling of shielded gate power semiconductor device Download PDF

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CN117457499A
CN117457499A CN202311442621.0A CN202311442621A CN117457499A CN 117457499 A CN117457499 A CN 117457499A CN 202311442621 A CN202311442621 A CN 202311442621A CN 117457499 A CN117457499 A CN 117457499A
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oxide layer
polysilicon
layer
filling
etching
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刘科科
钟义栋
董云
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Zhongjing Xinyuan Shanghai Semiconductor Co ltd
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Zhongjing Xinyuan Shanghai Semiconductor Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

The invention discloses a process method for improving HDP filling of a shielded gate power semiconductor device, which comprises the following steps: preparing a substrate, forming an epitaxial layer and an ONO hard mask layer on the substrate, and then etching to form a deep trench; generating a field oxide layer; filling the first polysilicon, and etching back to remove redundant first polysilicon; etching the field oxide layer to form a side wall protection layer; etching the first polysilicon; forming an HDP oxide layer and etching to form an isolation oxide layer; removing the ONO hard mask layer; and forming a gate oxide layer and gate polysilicon. According to the invention, the shielded gate polysilicon is etched back for one time, so that the depth of HDP filling can be reduced under the condition of the same design parameters of a finished product, the filling morphology of the HDP is improved, and the problem of pressure resistance reduction between the grid electrode and the source electrode caused by poor morphology of the isolation oxide layer can be avoided especially under the condition that the filling depth-to-width ratio is close to the limit of filling equipment.

Description

Technological method for improving HDP filling of shielded gate power semiconductor device
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a process method for improving HDP filling of a shielded gate power semiconductor device.
Background
At present, in the semiconductor device technology, compared with the traditional Trench type MOSFET, a Shielded-Gate Trench type MOSFET (SGT-MOSFET) introduces horizontal depletion on the basis of vertical depletion of a PN junction, changes the electric field of the device from triangular distribution to approximately rectangular distribution, and can obtain higher breakdown voltage under the condition of adopting epitaxial material specifications with the same doping concentration. Meanwhile, due to the introduction of the shielding grid structure, the Miller capacitance of the MOSFET can be greatly reduced, and the switching loss of the device can be reduced.
One conventional fabrication process for SGT-MOSFETs is to form an isolation oxide (IPO) between the gate and source polysilicon using a High Density Plasma (HDP) fill and then a back etch. However, as the cell size is continuously reduced, the aspect ratio of the HDP filling is continuously increased, and the performance limit of the current HDP filling machine is more and more approaching, so that the voltage withstand between the gate and the source is often reduced due to the abnormal HDP filling morphology.
Disclosure of Invention
In view of the above, the present invention aims to provide a process for improving HDP filling of a shielded gate power semiconductor device, which is capable of reducing the depth of HDP filling under the same design parameters (gate polysilicon depth and isolation oxide thickness) of a finished product by performing additional etching back on the shielded gate polysilicon, improving the HDP filling morphology, and avoiding the problem of reduced withstand voltage between the gate and the source due to poor isolation oxide morphology, especially under the condition that the filling aspect ratio is close to the limit of filling equipment.
In order to achieve the above object, the present invention provides a process for improving HDP filling of a shielded gate power semiconductor device, comprising the steps of:
preparing a substrate, forming an epitaxial layer on the substrate, forming an ONO hard mask layer on the epitaxial layer, and then etching to form a deep trench;
generating a field oxide layer at the bottom and the side wall of the deep trench;
filling the deep trench with first polysilicon, and back-etching to remove redundant first polysilicon, so that the depth of the upper end of the residual first polysilicon from the upper surface of the epitaxial layer is f, wherein f is f < a+b, a is the depth of the gate polysilicon in the finished product of the shielded gate power semiconductor device, and b is the thickness of the isolation oxide layer in the finished product of the shielded gate power semiconductor device;
a side wall protection layer is reserved on the side wall of the groove above the first polysilicon by etching and thinning the exposed field oxide layer, the depth of the upper end of the field oxide layer which is not thinned from the upper surface of the epitaxial layer is g, and g meets f < g < a+b;
further etching the first polysilicon back to enable the depth of the upper end of the remaining first polysilicon from the upper surface of the epitaxial layer to be a+b;
filling the deep trench and the epitaxial layer with HDP to form an HDP oxide layer, and etching the HDP oxide layer to form an isolation oxide layer;
removing the ONO hard mask layer;
and forming a gate oxide layer and gate polysilicon in the deep trench above the isolation oxide layer.
Preferably, a gate oxide layer and gate polysilicon are formed in the deep trench above the isolation oxide layer, specifically comprising the following steps:
forming a gate oxide layer on the side wall of the deep trench above the isolation oxide layer through thermal oxidation;
and filling second polysilicon in the deep trench above the isolation oxide layer and etching back to form gate polysilicon.
Preferably, the etching back removes the redundant first polysilicon, specifically: and firstly etching back to remove the first polysilicon on the upper surface of the ONO hard mask layer, and then etching back to remove the redundant first polysilicon in the deep trench.
Preferably, the thickness of the side wall protection layer is 20-25 nm.
Preferably, the ONO hard mask layer includes a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence.
Preferably, the sidewall protection layer is removed prior to HDP filling.
Preferably, the depth g of the upper end of the field oxide layer which is not thinned from the upper surface of the epitaxial layer is not more than 200nm different from the maximum depth allowed by the HDP filling process.
The beneficial effects of the invention are as follows:
(1) According to the invention, the shielded gate polysilicon is etched back for one time, so that the depth of HDP filling can be reduced under the condition of the same design parameters of a finished product (the depth of the gate polysilicon and the thickness of the isolation oxide layer), the filling morphology of the HDP is improved, and the problem of pressure resistance reduction between the gate and the source caused by poor morphology of the isolation oxide layer can be avoided especially under the condition that the filling aspect ratio is close to the limit of filling equipment.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1A to 1M are schematic flow diagrams of a first embodiment of the present invention;
FIGS. 2A to 2D are schematic flow diagrams of comparative examples;
wherein:
a 10 substrate; 20 epitaxial layers; 30ONO hard mask layer; 31 a first oxide layer; a 32 nitride layer; 33 a second oxide layer; 40 deep trenches; a 50 field oxide layer; 51 a sidewall protection layer; 61 a first polysilicon; 71 shield gate polysilicon; 72 gate polysilicon; an 80HDP oxide layer; 81 isolating an oxide layer; 90 gate oxide.
Detailed Description
The core of the invention is to provide a process method for improving the HDP filling of a shielded gate power semiconductor device, which is characterized in that the shielded gate polysilicon is etched back for one time, so that the depth of HDP filling can be reduced under the condition of the same design parameters (the depth of the gate polysilicon and the thickness of an isolation oxide layer) of a finished product, the filling morphology of the HDP is improved, and the problem of pressure resistance reduction between a gate and a source caused by poor morphology of the isolation oxide layer can be avoided especially under the condition that the filling depth-to-width ratio is close to the limit of filling equipment.
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Fig. 1A to 1M illustrate a process method for improving HDP filling of a shielded gate power semiconductor device according to the present embodiment, including the following steps:
s1: as shown in fig. 1A, a substrate 10 is prepared, an epitaxial layer 20 is formed on the substrate 10, and an ONO hard mask layer 30 is formed on the epitaxial layer 20, in this embodiment, the ONO hard mask layer 30 includes a first oxide layer 31, a nitride layer 32, and a second oxide layer 33 stacked in this order, wherein the nitride layer 32 is used to act as a barrier when etching oxides such as a field oxide layer in a subsequent step.
S2: as shown in fig. 1B, the deep trench 40 is etched.
S3: as shown in fig. 1C, a field oxide layer 50 is formed at the bottom and sidewalls of the deep trench 40.
S4: as shown in fig. 1D, the first polysilicon 61 is filled in the deep trench 40.
S5: as shown in fig. 1E, the first polysilicon 61 is etched back for the first time, and the portion of the first polysilicon 61 located above the hard mask layer 30 is removed.
S6: as shown in fig. 1F, the first polysilicon 61 is etched back for the second time, and then needs to be etched back to the upper end of the final product of the gate polysilicon 71, leaving a margin for further etching in the subsequent step, specifically, the depth of the upper end of the remaining first polysilicon from the upper surface of the epitaxial layer is F, where F is F < a+b, where a is the gate polysilicon depth in the final product of the gate power semiconductor device and b is the isolation oxide thickness in the final product of the gate power semiconductor device.
S7: as shown in fig. 1G, the exposed field oxide layer 50 is thinned by etching, so that a sidewall protection layer 51 is remained on the sidewall of the trench above the first polysilicon 61, preferably, the thickness of the sidewall protection layer 51 is 20-25 nm, and the upper end of the field oxide layer 50 which is not thinned will be slightly deeper than the upper end of the first polysilicon 61 due to the characteristics of the etching process, i.e. the depth of the upper end of the field oxide layer 50 which is not thinned from the upper surface of the epitaxial layer 20 is G, where G satisfies f < G < a+b:
s8: as shown in fig. 1H, the first polysilicon 61 is etched back again to form a shield gate polysilicon 71, where the upper end of the shield gate polysilicon 71 is a+b from the upper surface of the epitaxial layer, and further, the remaining sidewall protection layer 51 may be etched away to reduce the aspect ratio of the HDP filling in step S9 (fig. 1H to 1I describe the case where the sidewall protection layer 51 is not removed).
S9: as shown in fig. 1I, an HDP oxide layer 80 is formed over deep trench 40 and epitaxial layer 20 by HDP filling.
S10: as shown in fig. 1J, the HDP oxide layer 80 is etched to form an isolation oxide layer 81, which may be etched away in this step if the remaining sidewall protection layer 51 is not removed in step S8; in the above steps, the thickness of the surface layer of the ONO hard mask layer 30, i.e., the second oxide layer 33, is changed according to the oxide deposition/etching steps, and is removed in this step, but the ONO hard mask layer 30 is not completely removed due to the nitride layer 32.
S11: as shown in fig. 1K, the remaining ONO hard mask layer 30 is removed.
S12: as shown in fig. 1L, a gate oxide layer 90 is formed on the deep trench sidewalls above the isolation oxide layer 81 by thermal oxidation (while also creating a thinner oxide layer on the surface of the epitaxial layer 20).
S13: as shown in fig. 1M, the deep trench 40 above the isolation oxide 81 is filled with a second polysilicon and etched back to form a gate polysilicon 72.
The subsequent manufacturing process of the shielded gate power semiconductor device disclosed in this embodiment, such as the manufacturing of the source and the drain, can be known by those skilled in the art from other related technical documents, and will not be described herein again. Compared with the prior art, the step S8 is added, so that the depth of HDP filling can be reduced and the morphology of the HDP filling can be improved under the condition of the same gate polysilicon depth a and isolation oxide layer thickness b. The following is a detailed description of comparative examples.
Comparative examples
The difference between the present embodiment and the first embodiment is that, as shown in fig. 2A to 2D, steps S6 to S13 in the first embodiment are corresponding, and step S8 is not included in the steps in the comparative embodiment, so that the relevant depth parameters are also adjusted accordingly, specifically as follows:
s6-1: as shown in fig. 2A, the first polysilicon 61 is etched back for the second time, and then the shielding gate polysilicon 71 is formed at the position to be etched back to the final product, specifically, the depth of the upper end of the remaining first polysilicon from the upper surface of the epitaxial layer is a+b, where a is the depth of the gate polysilicon in the final product of the shielding gate power semiconductor device, and b is the thickness of the isolation oxide layer in the final product of the shielding gate power semiconductor device.
S7-1: as shown in fig. 2B, the exposed field oxide layer 50 is removed by etching (i.e. without retaining the sidewall protection layer), and the upper end of the field oxide layer 50 is deeper than the upper end of the shielded gate polysilicon 71 due to the characteristics of the etching process itself, and the depth difference is e, i.e. the depth of the upper end of the field oxide layer 50 is a+b+e from the upper surface of the epitaxial layer 20:
s9-1: as shown in fig. 2C, an HDP oxide layer 80 is formed over the deep trench 40 and the epitaxial layer 20 by HDP filling.
S10-1: the HDP oxide layer 80 is etched to form an isolation oxide layer 81.
S11-1: the remaining ONO hard mask layer 30 is removed.
S12-1: a gate oxide layer 90 is formed by thermally oxidizing the deep trench sidewalls above the isolation oxide layer 81.
S13-1: as shown in fig. 2D, the deep trench 40 in the upper isolation oxide 81 fills the second polysilicon and is etched back to form gate polysilicon 72.
Comparing the comparison of the embodiment with the first embodiment, it can be seen that, with the upper surface of the epitaxial layer 20 as a reference, the HDP filling depths of step S9-1 and step S9 are a+b+e and a+b, respectively (and since the upper end positions of the middle shield gate polysilicon 71 are the same, if only the depth to be filled above the field oxide layer 50 is considered, the HDP filling depths are a+b+e and a+b-c, respectively), it can be seen that in the case where the HDP filling widths are substantially identical (corresponding to the case where the sidewall protection layer 51 is removed in step S8 in the first embodiment), the HDP filling depth-to-width ratio of the first embodiment is smaller, and in a preferred embodiment, the final product is 40v sgt, the filling depth of the HDP filling process can be reduced by 200nm or more; in particular, the improved process of the present invention has a significant advantage over conventional processes when the process parameters of the HDP filling approach the limits of the apparatus, such as the parameter g mentioned in example one, and the maximum depth allowed by the HDP filling process (with a better guaranteed topography) are not more than 200nm apart.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (7)

1. The process method for improving the HDP filling of the shielded gate power semiconductor device is characterized by comprising the following steps of:
preparing a substrate, forming an epitaxial layer on the substrate, forming an ONO hard mask layer on the epitaxial layer, and then etching to form a deep trench;
generating a field oxide layer at the bottom and the side wall of the deep trench;
filling the deep trench with first polysilicon, and back-etching to remove redundant first polysilicon, so that the depth of the upper end of the residual first polysilicon from the upper surface of the epitaxial layer is f, wherein f is f < a+b, a is the depth of the gate polysilicon in the finished product of the shielded gate power semiconductor device, and b is the thickness of the isolation oxide layer in the finished product of the shielded gate power semiconductor device;
a side wall protection layer is reserved on the side wall of the groove above the first polysilicon by etching and thinning the exposed field oxide layer, the depth of the upper end of the field oxide layer which is not thinned from the upper surface of the epitaxial layer is g, and g meets f < g < a+b;
further etching the first polysilicon back to enable the depth of the upper end of the remaining first polysilicon from the upper surface of the epitaxial layer to be a+b;
filling the deep trench and the epitaxial layer with HDP to form an HDP oxide layer, and etching the HDP oxide layer to form an isolation oxide layer;
removing the ONO hard mask layer;
and forming a gate oxide layer and gate polysilicon in the deep trench above the isolation oxide layer.
2. The process of claim 1, wherein forming a gate oxide layer and a gate polysilicon in the deep trench above the isolation oxide layer, comprises:
forming a gate oxide layer on the side wall of the deep trench above the isolation oxide layer through thermal oxidation;
and filling second polysilicon in the deep trench above the isolation oxide layer and etching back to form gate polysilicon.
3. The process according to claim 1, wherein the back etching removes the excess first polysilicon, specifically: and firstly etching back to remove the first polysilicon on the upper surface of the ONO hard mask layer, and then etching back to remove the redundant first polysilicon in the deep trench.
4. The process of claim 1 wherein the sidewall protection layer has a thickness of 20-25 nm.
5. The process of claim 1, wherein the ONO hard mask layer comprises a first oxide layer, a nitride layer, and a second oxide layer stacked in sequence.
6. The process of claim 1 wherein the sidewall protection layer is removed prior to HDP filling.
7. The process of claim 1, wherein the depth g of the upper end of the non-thinned field oxide layer from the upper surface of the epitaxial layer differs from the maximum depth allowed by the HDP fill process by no more than 200nm.
CN202311442621.0A 2023-11-01 2023-11-01 Technological method for improving HDP filling of shielded gate power semiconductor device Pending CN117457499A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107017167A (en) * 2017-03-01 2017-08-04 上海华虹宏力半导体制造有限公司 The manufacture method of trench-gate device with shield grid
CN108364870A (en) * 2018-01-23 2018-08-03 西安龙腾新能源科技发展有限公司 Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107017167A (en) * 2017-03-01 2017-08-04 上海华虹宏力半导体制造有限公司 The manufacture method of trench-gate device with shield grid
CN108364870A (en) * 2018-01-23 2018-08-03 西安龙腾新能源科技发展有限公司 Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality

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