CN106876284B - 半导体封装件及其制造方法 - Google Patents
半导体封装件及其制造方法 Download PDFInfo
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- CN106876284B CN106876284B CN201611043189.8A CN201611043189A CN106876284B CN 106876284 B CN106876284 B CN 106876284B CN 201611043189 A CN201611043189 A CN 201611043189A CN 106876284 B CN106876284 B CN 106876284B
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Abstract
提供了半导体封装件及其制造方法。该半导体封装件包括上半导体芯片封装件、下半导体芯片封装件和置于封装件之间的重分配布线层图案。下封装件包括模制层,至少一个芯片嵌入模制层中,下封装件具有顶表面和倾斜的侧壁表面,重分配布线层图案沿顶表面和侧壁表面形成。上封装件和下封装件通过重分配布线层图案彼此电连接。第一封装件可由晶片级封装技术形成并可包括作为基底的重分配布线层、设置在重分配布线层上的半导体芯片以及其上设置有下封装件、重分配布线层图案和上封装件的模制层。
Description
本申请要求于2015年12月10日在韩国知识产权局提交的第10-2015-0176044号韩国专利申请的优先权,该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
发明构思涉及一种半导体封装件,更具体地,涉及一种包括多个半导体芯片的半导体封装件和一种制造该半导体封装件的方法。
背景技术
为了在电子产品中使用集成电路芯片(或半导体芯片),可通过封装技术包封集成电路芯片,从而形成包括集成电路芯片的半导体封装件。在普通的半导体封装件中,半导体芯片可安装在印刷电路板(PCB)上并可通过键合引线或凸块电连接到PCB。在电子工业中,对高性能、高速且小型的电子组件的需求已经越来越多。为满足这些需求,可将多个半导体芯片堆叠在一个基底上和/或可将封装件堆叠在另一个封装件上。
发明内容
根据发明构思的一方面,一种制造半导体封装件的方法包括:设置第一封装件,所述第一封装件包括基底、第一半导体芯片和第一模制层;设置第二封装件,所述第二封装件包括第二半导体芯片和位于第二半导体芯片上的第二模制层,其中,第二半导体芯片具有设置在第二半导体芯片的顶表面处并被第二模制层暴露的芯片焊盘,其中,第二封装件具有底表面、顶表面和侧壁表面,所述顶表面在与基底的顶表面平行的给定方向上比底表面窄并基本上平行于底表面,所述侧壁表面在相对于底表面非垂直的倾斜的方向上延伸;在第一封装件上以第二封装件的底表面面对第一封装件的取向来安装第二封装件;沿第二封装件的顶表面和侧壁表面形成重分配布线层图案,重分配布线层图案电连接至第二半导体芯片的芯片焊盘;在重分配布线层图案上安装第三半导体芯片并使第三半导体芯片电连接至重分配布线层图案。
根据发明构思的另一方面,一种制造半导体封装件的方法包括:设置下封装件,所述下封装件包括:基底;第一半导体芯片,安装在基底上;第一模制层,覆盖位于基底上的第一半导体芯片;电互连件,在基底上的第一模制层中延伸;第二模制层,位于第一模制层上,第二模制层具有比第一模制层窄的底表面、比底表面窄的顶表面和在相对于基底的顶表面非垂直的倾斜的方向上延伸的侧壁表面;以及第二半导体芯片,嵌入第二模制层中,第二半导体芯片包括设置在其顶表面处的芯片焊盘;在下封装件上形成重分配布线层图案,使重分配布线图案电连接至互连件和下封装件的第二半导体芯片的芯片焊盘两者;将第三半导体芯片安装到下封装件,使第三半导体芯片设置于重分配布线层图案上并电连接至重分配布线层图案。
根据发明构思的又一方面,一种制造半导体封装件的方法包括:形成半导体封装件,所述半导体封装件具有基本梯形的截面形状并包括第一半导体芯片和第一模制层,第一半导体芯片嵌入第一模制层中,所述半导体封装件具有底表面、基本平行于底表面的顶表面和在相对于顶表面和底表面非垂直的倾斜的方向上延伸至顶表面的边缘和底表面的边缘并位于顶表面的边缘和底表面的边缘之间的侧壁表面,第一半导体芯片具有构成半导体封装件的顶表面的有效表面;形成重分配布线层图案,所述重分配布线层图案位于第一模制层上并且在第一半导体芯片的有效表面处电连接至第一半导体芯片,其中,重分配布线层图案的各个部分设置在第一模制层的顶表面和侧壁表面上并分别与顶表面和所述倾斜的方向基本平行地延伸;将另一个半导体芯片安装到半导体封装件,使所述另一个半导体芯片设置于重分配布线层图案上并电连接至重分配布线层图案,该步骤包括将所述另一个半导体芯片设置在重分配布线层图案的设置于第一模制层的顶表面上并基本平行于第一模制层的顶表面延伸的部分上,并在所述另一个半导体芯片和重分配布线层图案上形成另一个模制层。
根据发明构思的再一方面,一种半导体封装件包括:第一封装件,所述第一封装件包括基底、安装在基底上的第一半导体芯片、覆盖位于基底上的第一半导体芯片的第一模制层和在第一模制层内的至少一个电互连件;第二封装件,所述第二封装件包括第二半导体芯片和第二模制层,所述第二半导体芯片设置在第一模制层上并具有芯片焊盘、与第一模制层分隔开的底表面和芯片焊盘所在的顶表面,所述第二模制层覆盖第二半导体芯片的底表面和侧面,所述第二模制层具有在与基底的顶表面平行的给定方向上比第一封装件窄的底表面、在所述给定方向上比第二模制层的底表面窄的顶表面以及在相对于基底的顶表面非垂直的倾斜的方向上延伸的侧壁表面;重分配布线层图案,沿第一模制层的顶表面、第二模制层的侧壁表面和第二模制层的顶表面延伸,所述重分配布线层图案电连接至互连件和芯片焊盘;以及第三半导体芯片,设置于重分配布线层图案上。
附图说明
基于附图和所附的详细描述,发明构思将变得更加清楚。
图1是示出根据发明构思的一些示例的半导体封装件的剖视图。
图2是图1的区域“I”的放大图以示出根据发明构思的一些示例的半导体封装件的第二模制层和重分配图案。
图3是示出根据发明构思的一些示例的半导体封装件的剖视图。
图4A至图4H是示出根据发明构思的一些示例的制造半导体封装件的方法的剖视图。
图5是示出根据发明构思的一些示例的半导体封装件的剖视图。
图6A至图6C是示出根据发明构思的一些示例的制造半导体封装件的方法的剖视图。
具体实施方式
将在下文中描述根据发明构思的一些示例的半导体封装件。
图1是示出根据发明构思的一些示例的半导体封装件的剖视图。
参照图1,半导体封装件1可包括第一封装件PKG1、第二封装件PKG2和第三封装件PKG3以及重分配布线层图案500,其中,所述重分配布线层图案500在下文中可被简称为“重分配图案500”。第一封装件PKG1可包括基底100、第一半导体芯片110、第一模制层120和电互连件130。重分配层可被用作基底100。例如,基底100可包括金属图案103、第一绝缘层101和第二绝缘层105。例如,金属图案103可包括铜。第一绝缘层101可覆盖第一半导体芯片110的底表面110b和第一模制层120的底表面。第一绝缘层101可由硅基绝缘材料或聚合物形成。金属图案103可设置于第一绝缘层101的底表面上。金属图案103可延伸至第一绝缘层101内。第二绝缘层105可设置在第一绝缘层101的底表面上以覆盖金属图案103。第二绝缘层105还可由硅基绝缘材料或聚合物形成。在一些示例中,绝缘层101和105的数量以及金属图案103的数量与在图1中示出的数量不同。连接通孔107可设置在第二绝缘层105中以与金属图案103接触。基底100可具有大约0.1mm至大约0.5mm的平均厚度D1,因此可使半导体封装件1的尺寸最小化。在某些示例中,基底100可为具有电路图案的印刷电路板(PCB)。
外部端子150可设置在第二绝缘层105的底表面上以连接至连接通孔107。外部端子150可包括外部焊盘151和/或焊球153。外部端子150可包括诸如锡(Sn)、银(Ag)或他们的合金的导电材料。可设置多个外部端子150和多个连接通孔107。金属图案103可从第一半导体芯片110的底表面110b的下方延伸至第一模制层120的底表面下方,因此外部端子150可设置在第一半导体芯片110的底表面110b和第一模制层120的底表面两者的下面。因此,外部端子150的布局具有高自由度。
第一半导体芯片110可设置在基底100的顶表面100a上。第一半导体芯片110可包括第一集成电路(未示出),诸如,存储电路、逻辑电路或他们的组合。第一集成电路可邻近于第一半导体芯片110的底表面110b。第一半导体芯片110可包括设置于其底表面110b上的第一芯片焊盘111,因此第一半导体芯片110的底表面110b可用作有效表面。第一芯片焊盘111可连接至第一半导体芯片110的第一集成电路。在下文中,术语“芯片焊盘”将指半导体芯片的焊盘导电材料,该焊盘导电材料电连接至半导体芯片的集成电路的有源/无源元件并用作使外部装置电连接至集成电路的端子。金属图案103可延伸到第一绝缘层101内从而连接至第一芯片焊盘111。因此,半导体封装件1不需要键合引线来将第一半导体芯片110电连接至基底100。结果,半导体封装件1的尺寸可保持为最小。在一些示例中,可在基底100和第一芯片焊盘111之间设置内插器(未示出)。内插器可包括导电(焊)球、柱、或(焊料)凸块。
第一模制层120可以设置在基底100上,以覆盖第一半导体芯片110的侧面和顶面。第一模制层120可以由诸如环氧树脂模塑料(EMC)的绝缘聚合物形成。
互连件130可设置在基底100上的第一模制层120中。互连件130可具有柱状或凸块的形状。互连件130可与半导体芯片110横向分隔开。第一模制层120可暴露互连件130的顶表面130a。连接焊盘131可设置在互连件130和基底100之间。金属图案103的延伸部可穿透第一绝缘层101以连接至连接焊盘131。可设置多个互连件130。在一些示例中,每个互连件130和连接焊盘131可包括铜(Cu)、锡(Sn)、银(Ag)或其任意合金。
第二封装件PKG2可设置在第一封装件PKG1上。第二封装件PKG2可包括第二半导体芯片210和第二模制层220。第二封装件PKG2可覆在第一封装件PKG1的中心部分上(即,竖直对齐或并列),但可不覆在第一封装件PKG1的外部***部分上。具体地,第二封装件PKG2可不覆盖第一模制层120的顶表面120a的一部分和互连件130。第二半导体芯片210可设置在第一模制层120上。第二半导体芯片210的有效表面可以面朝上,以成为第二半导体芯片210沿图中所示的半导体封装件1取向的顶表面210a。因此,例如,第二半导体芯片210可以包括设置在其顶表面210a上的第二芯片焊盘211。第二半导体芯片210可包括设置在其芯片主体中的第二集成电路(未示出),第二集成电路可与第二半导体芯片210的顶表面210a相邻。
第二模制层220可设置在第一模制层120和重分配图案500之间。第二模制层220可覆盖第二半导体芯片210的侧面和底面并可暴露第二芯片焊盘211。粘附膜160可设置在第一模制层120和第二模制层220之间。粘附膜160可包括绝缘聚合物,例如,热固性聚合物。第二模制层220可具有顶表面220a、底表面220b和侧壁表面220c。第二模制层220的顶表面220a和底表面220b可基本平行于基底100的顶表面100a。在本说明书中,术语“基本平行”可包括与平行的精确程度的偏差,该偏差在用于将第一封装件PKG1和第二封装件PKG2制造并封装在一起的工艺所带来的公差之内。第二模制层220的底表面220b的宽度W2(即,第二封装件PKG2的底表面的宽度)可小于第一模制层120的顶表面120a的宽度W1(即,第一封装件PKG1的顶表面的宽度)。第二模制层220可不覆盖第一模制层120的顶表面120a的一部分。第二模制层220的顶表面220a的宽度W3(即,第二封装件PKG2的顶表面的宽度)可小于第二模制层220的底表面220b的宽度W2(即,第二封装件PKG2的底表面的宽度)。第二模制层220的侧壁表面220c可以在相对于基底100的顶表面100a倾斜的同时延伸至顶表面220a的边缘和底表面220b的边缘并位于两者之间。由第二模制层220的侧壁表面220c和底表面220b所构成的角θ1可以是锐角。因此,如图1中所示,第二封装件PKG2的(模制层的)截面形状可为梯形。
在本说明书中,所描述的元件相对于一些表面或平面倾斜的描述可意味着连接该元件的两端(即,顶端和底端)的假想直线相对于所述表面或平面倾斜。换言之,元件的“倾斜(inclination)”可指元件的两端之间的平均梯度的度量。在一些示例中,第二模制层220的侧壁表面220c可以是相对于基底100的顶表面100a以倾斜延伸的平坦表面。然而,第二模制层220的侧壁表面220c的形状不限于此。即,第二模制层220的侧壁表面220c可具有除平坦之外的形状,并仍相对于基底100的顶表面100a倾斜。在此情况下,第二封装件PKG2的截面形状可被认为“基本上”是梯形。第二模制层220可包括诸如环氧树脂模塑料(EMC)的绝缘聚合物。
重分配图案500可沿第一模制层120的顶表面120a、第二模制层220的侧壁表面220c和第二模制层220的顶表面220a延伸。重分配图案500可包括第一绝缘图案510、导电图案520和第二绝缘图案530。第一绝缘图案510可覆盖第一模制层120的顶表面120a、第二模制层220的侧壁表面220c和第二模制层220的顶表面220a。第一绝缘图案510可具有暴露第二芯片焊盘211的第一开口511和暴露互连件130的第二开口512。第一绝缘图案510可由诸如氧化硅、氮化硅和/或氮氧化硅的硅基绝缘材料形成。导电图案520可设置在第一绝缘图案510上。导电图案520可延伸至第一开口511内以连接至第二芯片焊盘211。导电图案520可延伸至第二开口512内以连接至互连件130。第二半导体芯片210可通过导电图案520和互连件130电连接至基底100。导电图案520可包括金属例如铜。第二绝缘图案530可设置在导电图案520上。第二绝缘图案530可覆盖导电图案520以保护导电图案520。第二绝缘图案530可由氧化硅、氮化硅和/或氮氧化硅形成。通孔535可设置在第二绝缘图案530中以连接至导电图案520。在一些示例中,绝缘图案510和530的数量以及导电图案520的数量与图1中示出的数量不同。重分配图案500比能够执行相同功能的对应或对比的印刷电路板(PCB)薄。例如,重分配图案500的平均厚度D2可在大约0.1mm至大约0.5mm的范围。因此,半导体封装件1的尺寸可保持为最小。
设置在第二模制层220的侧壁表面220c上的重分配图案500可相对于基底100的顶表面100a倾斜。例如,设置在侧壁表面220c上的重分配图案500可与第二模制层220的底表面220b构成锐角。第二半导体芯片210可设置在重分配图案500的倾斜部分之间(如剖视图中所示)或可被重分配图案500的倾斜部分围绕全部四个侧面(如平面图中将看到)。如果省略重分配图案500的倾斜部分,那么必须在重分配图案500和互连件130之间形成另外的焊球、焊料凸块或通孔。根据发明构思的一些示例,重分配图案500可与互连件130接触,因此需要相对少的工艺来制造半导体封装件1。第一模制层120和第二模制层220可填充基底100和重分配图案500之间的空间。
再次参照图1,第三封装件PKG3可设置在重分配图案500上。第三封装件PKG3可包括第三半导体芯片310和第三模制层320。第三半导体芯片310可包括设置在其芯片主体内的第三集成电路(未示出)。第三半导体芯片310可包括设置在其底表面上的第三芯片焊盘311,即,第三半导体芯片310的有效表面可为在图中示出的取向上的底表面310b。
连接端子537可设置在重分配图案500上并可与通孔535对齐。连接端子537可连接至第三半导体芯片310的第三芯片焊盘311。第三半导体芯片310可通过连接端子537和导电图案520电连接至第一封装件PKG1。每个连接端子537可为柱状或导电材料或焊球。连接端子537可包括导电材料,诸如锡(Sn)、银(Ag)、铜(Cu)或其任意合金。在一些示例中,可在连接端子537和通孔535之间设置焊盘(未示出)。在一些示例中,可以省略连接端子537,并且第三芯片焊盘311可以与通孔535或设置在通孔535上的导电焊盘(未示出)直接接触。根据发明构思的一些示例,第二半导体芯片210和第三半导体芯片310可通过重分配图案500电连接至基底100,因此无需另外的上基底。因此,半导体封装件1的尺寸可保持为最小。
根据发明构思的一些示例,第二半导体芯片210可以设置在重分配图案500的底表面之下,第三半导体芯片310可以设置在重分配图案500的顶表面上。如果第二半导体芯片210相反地被设置在第三半导体芯片310的顶表面上,则半导体封装件应需要将第二半导体芯片210连接至重分配图案500的键合引线。然而,根据发明构思的一些示例,不需要键合引线,因此可以使半导体封装件1的高度最小化。如果第二半导体芯片210设置在第三半导体芯片310上并通过焊球连接到第三半导体芯片310,则应需要穿透第三半导体芯片310延伸的贯穿孔。然而,根据发明构思的一些示例,半导体封装件1不具有这样的贯穿孔,因此制造半导体封装件1相对简单。重分配图案500的平均厚度D2可小于印刷电路板(PCB)的厚度。例如,重分配图案500的平均厚度D2可在大约0.1mm至大约0.5mm的范围。因此,可以使半导体封装件1的尺寸最小化。
第三模制层320可以被设置在重分配图案500上,以覆盖第三半导体芯片310。第三模制层320可以由诸如环氧树脂模塑料(EMC)的绝缘聚合物形成。
图2是为示出根据发明构思的一些示例的半导体封装件的第二模制层和重分配图案的图1的区域“I”的放大图。
参照图1和图2,第二模制层220的侧壁表面220c可以为倾斜的。如上所述,侧壁表面220c的“倾斜(inclination)”可以是该表面的两端(顶端和底端)之间的平均梯度。第二模制层220的侧壁表面220c可具有楼梯形状,其中,所述楼梯形状具有交替重复的第一部分和第二部分。第一部分可平行于基底100的顶表面100a(即,在图中示出的取向上可为水平表面),第二部分可垂直于基底100的顶表面100a(即,可为竖直表面)。在此情况下,连接第二模制层220的侧壁表面220c的两端的假想线在相对于基底100的顶表面100a非垂直(oblique)的方向上延伸。即,连接侧壁表面220c的两端的假想线可与第二模制层220的底表面220b构成锐角。然而,第二模制层220的侧壁表面220c的形状不限于平坦形状或楼梯形状,而是可以具有任意的其他各种形状,只要该表面的“倾斜”相对于基底100的顶表面100a非垂直(或者成非直角,oblique)即可。因此,在任意的这些其他示例中,第二封装件PKG2的(模制层220的)截面形状可基本为梯形。
第一绝缘图案510可设置在第二模制层220的侧壁表面220c上以具有楼梯形状的底表面510b。第一绝缘图案510的顶表面510a可为在相对于基底100的顶表面100a非垂直的方向上倾斜的平坦表面。导电图案520可沿所述倾斜的方向在第二模制层220的侧壁表面220c上延伸并且可以是平坦的。然而,发明构思的示例不限于第一绝缘图案510的顶表面510a、导电图案520和第二绝缘图案530的前述形状。
图3是示出根据发明构思的一些示例的半导体封装件的剖视图。
参照图3,半导体封装件2可包括第一封装件PKG1、第二封装件PKG2、第三封装件PKG3和重分配图案500。第一封装件PKG1、第三封装件PKG3和重分配图案500可与参照图1描述的那些相同。例如,第一封装件PKG1可包括基底100、第一半导体芯片110、第一模制层120和互连件130。重分配层可用作基底100。第三封装件PKG3可包括第三半导体芯片310和第三模制层320。
第二封装件PKG2可包括第二半导体芯片210和第二模制层220。在这些示例中,第二封装件PKG2具有多个第二半导体芯片210。第二半导体芯片210可横向布置。第二半导体芯片210的第二芯片焊盘211可连接至重分配图案500。
在一些示例中,可设置多个第一半导体芯片110。第一半导体芯片110可横向布置。
将在下文中描述根据发明构思的示例的半导体封装件的制造方法。
图4A至图4H是示出根据发明构思的一些示例的半导体封装件的制造方法的剖视图。在下文中,术语“顶表面”和“底表面”是参照图1的描述来使用的,而与示出和描述方法的具体阶段期间的表面的取向无关。在下文中,为了简洁和便于解释,在上面已经提及并详细描述的技术特征将不再详细描述或将仅简要提及。
参照图4A,可在载体基底400上设置第一半导体芯片110。可在载体基底400上设置多个第一半导体芯片110。第一半导体芯片110的第一芯片焊盘111可面向载体基底400。可在载体基底400上与第一半导体芯片110横向分隔开的位置处(例如,在扇出区中)形成连接焊盘131和互连件130。可在载体基底400上形成第一模制层120以覆盖第一半导体芯片110。第一模制层120可覆盖互连件130的侧面,但可不覆盖互连件130的顶表面130a。随后,可去除载体基底400以暴露第一半导体芯片110的第一芯片焊盘111。在一些示例中,可在这些工艺中省略形成互连件130的步骤。
参照图4B,可在第一半导体芯片110的底表面110b和第一模制层120的底表面上形成绝缘层101和105以及金属图案103,从而制造基底100。可在第一半导体芯片110的底表面110b和第一模制层120的底表面上形成第一绝缘层101。第一绝缘层101可暴露第一半导体芯片110的第一芯片焊盘111和连接焊盘131。可通过电镀工艺在第一绝缘层101的底表面上形成金属图案103。金属图案103可延伸至第一绝缘层101内以连接至第一芯片焊盘111和连接焊盘131。可形成第二绝缘层105以覆盖金属图案103。可形成连接通孔107以穿透第二绝缘层105。连接通孔107可连接至金属图案103。可在第二绝缘层105的底表面上形成外部焊盘151以连接至连接通孔107。可在外部焊盘151上形成焊球153,从而形成外部端子150。每个外部端子150可包括相应的一个外部焊盘151和相应的一个焊球153。因此,可制造晶片级的第一封装件PKG1。在一些示例中,可不在参照图4A描述的工艺中形成而是可在制造基底100之后形成互连件130。
参照图4C,可在支撑基底410上形成第二半导体芯片210和第二模制层220。可在支撑基底410上设置多个第二半导体芯片210。第二半导体芯片210的第二芯片焊盘211可面向支撑基底410。第二模制层220可覆盖第二半导体芯片210,但可不覆盖第二芯片焊盘211。随后,可去除支撑基底410以暴露第二半导体芯片210的第二芯片焊盘211。
参照图4D,可锯开第二模制层220以使第二封装件PKG2彼此分离。可使用刀片或激光锯开第二模制层220。可以沿着相对于第二模制层220的底表面220b非垂直地倾斜的方向锯开第二模制层220。例如,第二模制层220的侧壁表面220c和第二模制层220的底表面220b可以构成锐角。在一些示例中,可通过台阶式切割(step-cut)技术锯开第二模制层220以使第二模制层220的侧壁表面220c具有在图2中示出的楼梯形状。然而,发明构思的示例不限于制造上述形状的第二模制层220的侧壁表面220c。可通过基于期望形式的各种锯开工艺来形成第二模制层220的其他形式的倾斜的侧壁表面220c,只要总体形式如上面已经描述的是倾斜的即可。
参照图4E,可在第一封装件PKG1上堆叠第二封装件PKG2。此时,第二封装件PKG2的第二模制层220的底表面220b可面向第一模制层120并可基本平行于基底100的顶表面100a来设置。第二封装件PKG2的第二模制层220的侧壁表面220c可平行于前述的倾斜的方向。在将第二封装件PKG2堆叠在第一封装件PKG1上之前可在第一封装件PKG1上或第二封装件PKG2下面形成粘附膜160,使得粘附膜160置于第一模制层120与每个第二模制层220之间,以将每个第二模制层220粘附到第一模制层120。第二封装件PKG2可不覆盖第一模制层120的顶表面120a的一部分和互连件130的顶表面130a。在一些示例中,可不在参照图4A描述的工艺中形成而是可在将第二封装件PKG2堆叠在第一封装件PKG1上之后形成互连件130。
参照图4F,可在第一封装件PKG1和第二封装件PKG2上形成第一绝缘图案510。第一绝缘图案510可沿第一模制层120的未被第二封装件PKG2覆盖的顶表面120a、第二模制层220的侧壁表面220c、第二模制层220的顶表面220a和第二半导体芯片210的顶表面210a延伸。可使用光刻工艺将第一绝缘图案510图案化,以在第一绝缘图案510中形成第一开口511和第二开口512。第一开口511可暴露第二芯片焊盘211,第二开口512可暴露互连件130。可由参照图1描述的材料形成第一绝缘图案510。
参照图4G,可在第一绝缘图案510上形成导电图案520。导电图案520可延伸至第一开口511和第二开口512内以连接至第二芯片焊盘211和互连件130。可使用电镀工艺形成导电图案520。
可形成第二绝缘图案530以覆盖导电图案520。可将第二绝缘图案530图案化,以形成暴露导电图案520的第三开口531。因此,可制造重分配图案500。
参照图4H,可在重分配图案500上形成第三封装件PKG3。例如,可在重分配图案500上设置第三半导体芯片310。第三半导体芯片310的第三芯片焊盘311可面向重分配图案500。例如,可在重分配图案500的设置在第二半导体芯片PKG2的部分上分别设置第三半导体芯片310。可通过用导电材料填充第三开口531来在第三开口531中形成通孔535。可在重分配图案500上形成连接端子537以使连接端子537被连接至通孔535和第三芯片焊盘311。在一些示例中,可将连接焊盘(未示出)形成为分别置于通孔535和连接端子537之间。可形成第三模制层320以覆盖重分配图案500和第三半导体芯片310。
可沿图4H中虚线表示的位置锯开第一模制层130、第三模制层320和基底100,从而使半导体封装件1彼此分离。每个半导体封装件1可与参照图1描述的相同。
图5是示出根据发明构思的一些其他示例的半导体封装件的剖视图。
参照图5,半导体封装件3可包括下封装件P1、重分配基底1500和上封装件P2。下封装件P1可包括下半导体芯片1210和下模制层1220。下封装件P1可与参照图1描述的第二封装件PKG2类似。例如,下半导体芯片1210可包括设置在其顶表面1210a处的下芯片焊盘1211。下模制层1220可覆盖下半导体芯片1210的侧壁表面和底表面,而可不覆盖下半导体芯片1210的顶表面1210a。下模制层1220可具有顶表面1220a、底表面1220b和侧壁表面1220c。下模制层1220的顶表面1220a处的宽度W5(即,下封装件P1的顶表面的宽度W5)可小于下模制层1220的底表面1220b的宽度W4(即,下封装件P1的底表面的宽度W4)。下模制层1220的侧壁表面1220c可以延伸至顶表面1220a的边缘和底表面1220b的边缘并位于这两个边缘之间。下模制层1220的侧壁表面1220c可以相对于下模制层1220的底表面1220b非垂直地倾斜。例如,下模制层1220的侧壁表面1220c与底表面1220b之间的角θ2可为锐角。
重分配基底1500可设置在下封装件P1上。重分配基底1500可与参照图1描述的重分配图案500类似。重分配基底1500可沿下模制层1220的顶表面1220a和侧壁表面1220c来设置。重分配基底1500可还沿上模制层1320的底表面1320b延伸以具有与下模制层1220的底表面1220b基本共面的底表面。设置在下模制层1220的侧壁表面1220c上的重分配基底1500可相对于下模制层1220的底表面1220b倾斜。
重分配基底1500可包括顺序堆叠的第一绝缘图案1510、导电图案1520和第二绝缘图案1530。第一绝缘图案1510可沿下模制层1220的顶表面1220a和侧壁表面1220c设置,并可从下模制层1220的底端部分横向延伸。第一绝缘图案1510的横向延伸的底表面可不被下模制层1220覆盖。导电图案1520可设置在第一绝缘图案1510上。导电图案1520可延伸至绝缘图案1510内以连接至下芯片焊盘1211。第二绝缘图案1530可覆盖导电图案1520。通孔1535可设置在第二绝缘图案1530中以连接至导电图案1520。重分配基底1500可比对应或对比的印刷电路板(PCB)薄。例如,重分配基底1500可具有大约0.1mm至大约0.5mm的厚度D3。
外部端子150可设置在重分配基底1500的底表面上。在此,重分配基底1500的底表面可被下模制层1220暴露。导电图案1520可延伸至第一绝缘图案1510内以连接至外部端子150。每个外部端子150可包括相应的一个外部焊盘151和相应的一个焊球153。
上封装件P2可设置在重分配基底1500上。上封装件P2可包括上半导体芯片1310和上模制层1320。上封装件P2可与参照图1描述的第三封装件PKG3类似。上半导体芯片1310可包括设置在其底表面1310b处的上芯片焊盘1311,因此上半导体芯片1310的底表面1310b可为上半导体芯片1310的有效表面。连接端子1537可设置在通孔1535上以连接至上半导体芯片1310的上芯片焊盘1311。
根据发明构思的一些示例,上半导体芯片1310和下半导体芯片1210可通过重分配基底1500电连接至外部端子150。因此,无需另外的上基底,从而可使半导体封装件3的尺寸最小化。
图6A至图6C是示出根据发明构思的一些示例的制造半导体封装件的方法的剖视图。在下文中,为了简洁和便于解释,与在前面已经详细描述的元件相同的元件将不再详细描述或将仅简要提及。
参照图6A,可在临时基底420上放置下封装件P1。下封装件P1可包括下半导体芯片1210和下模制层1220。下封装件P1可与参照图5描述的相同并可通过与参照图4C和图4D描述的制造第二封装件PKG2的技术相同的技术制造。可在临时基底420上设置多个下封装件P1。可在临时基底420上横向彼此分隔开地设置下封装件P1。下模制层1220的底表面1220b可面向临时基底420。下模制层1220的侧壁表面1220c可平行于前述倾斜的方向。
参照图6B,可以在临时基底420上形成重分配基底1500以及上封装件P2。重分配基底1500可与参照图5描述的重分配基底相同,并可通过与参照图4F和图4G描述的技术相同的技术制造。例如,重分配基底1500可包括顺序堆叠的第一绝缘图案1510、导电图案1520和第二绝缘图案1530。导电图案1520可延伸至形成在第一绝缘图案1510中的第一开口1511和第二开口1512内。重分配图案1500可沿下模制层1220的顶表面1220a、下模制层1220的侧壁表面1220c和临时基底420的顶表面420a延伸。
上封装件P2可与参照图5描述的上封装件相同,并可通过与参照图4H描述的制造第三封装件PKG3的技术相同的技术来制造。例如,上半导体芯片1310可设置在重分配基底1500上,并可连接至重分配基底1500。可在重分配基底1500上设置多个上半导体芯片1310。上半导体芯片1310可分别覆在下封装件P1上。可在重分配基底1500上形成上模制层1320以覆盖上半导体芯片1310。可去除临时基底420以暴露设置在第二开口1512中的导电图案1520。
参照图5和图6C,可在重分配基底1500的暴露的底表面上形成外部端子150。每个外部端子150可连接至设置在第二开口1512之一中的相应的导电图案1520。每个外部端子150可包括外部焊盘151和焊球153,并可与参照图5描述的相同。可沿由图6C中的虚点线指示的区域锯开上模制层1320和重分配基底1500,从而使半导体封装件3彼此分离。每个半导体封装件3可与参照图5描述的半导体封装件相同。
根据发明构思的一些示例,第二封装件可具有倾斜的侧壁表面,因此重分配图案可形成在第一封装件和第二封装件上。第二半导体芯片和第三半导体芯片可通过重分配图案电连接至基底。因此,在根据发明构思的一些示例的半导体封装件中可省略另外的上基底。重分配图案可相对薄。由于设置了重分配图案可使半导体封装件的尺寸最小化。
虽然已经参照发明构思的一些示例描述了发明构思,但本领域技术人员将清楚,可在不脱离发明构思的精神和范围的情况下对这些示例做出各种改变和修改。因此,应理解上述示例不是限制性的而是说明性的。因此,发明构思的范围由权利要求的最宽许可解释来确定,而不应该受前面的描述限制或局限。
Claims (23)
1.一种制造半导体封装件的方法,所述方法包括:
设置第一封装件,所述第一封装件包括基底、第一半导体芯片和第一模制层;
设置第二封装件,所述第二封装件包括第二半导体芯片和位于第二半导体芯片上的第二模制层,其中,第二半导体芯片在第二半导体芯片的顶表面处具有被第二模制层暴露的芯片焊盘,第二封装件具有底表面、顶表面和侧壁表面,其中,所述顶表面在与基底的顶表面平行的给定方向上比底表面窄并与底表面基本平行地延伸,所述侧壁表面在相对于底表面非垂直的倾斜的方向上延伸;
以第二封装件的底表面面对第一封装件的取向来在第一封装件上安装第二封装件;
沿第二封装件的顶表面和侧壁表面形成重分配布线层图案,重分配布线层图案电连接至第二半导体芯片的芯片焊盘;以及
在重分配布线层图案上安装第三半导体芯片并使第三半导体芯片电连接至重分配布线层图案,
其中,设置第一封装件的步骤包括:
在载体基底上设置第一半导体芯片,所述第一半导体芯片包括设置在第一半导体芯片的底表面处的焊盘;
在载体基底上形成覆盖第一半导体芯片的第一模制层;
去除载体基底以暴露第一半导体芯片的焊盘;以及
在第一半导体芯片的底表面和第一模制层的底表面上形成基底。
2.根据权利要求1所述的方法,所述方法还包括:形成穿透第一模制层的电互连件,
其中,互连件电连接到基底,重分配布线层图案电连接到互连件。
3.根据权利要求2所述的方法,其中,在第一封装件上设置第二封装件以暴露互连件的顶表面。
4.根据权利要求1所述的方法,其中,设置在第一封装件上的第二封装件暴露第一模制层的顶表面的至少一部分;以及
重分配布线层图案沿第一模制层的暴露的顶表面延伸。
5.根据权利要求1所述的方法,其中,重分配布线层图案在与第二封装件的侧壁表面的所述倾斜的方向平行的方向上延伸。
6.根据权利要求1所述的方法,所述方法还包括:
形成粘附膜,所述粘附膜在第二封装件被安装于第一封装件上时变得被置于第一模制层和第二模制层之间。
7.根据权利要求1所述的方法,其中,基底包括彼此堆叠的第一绝缘层、金属图案和第二绝缘层。
8.根据权利要求1所述的方法,所述方法还包括:
在重分配布线层图案上形成覆盖第三半导体芯片的第三模制层。
9.根据权利要求1所述的方法,其中,第二模制层覆盖第二半导体芯片的底表面和侧表面,但暴露第二半导体芯片的顶表面。
10.根据权利要求1所述的方法,其中,将第二封装件设置在第一封装件上的步骤包括:
以第二封装件的底表面基本平行于基底的顶表面的取向来在第一封装件上设置第二封装件。
11.一种制造半导体封装件的方法,所述方法包括:
设置下封装件,所述下封装件包括:基底;第一半导体芯片,安装在基底上;第一模制层,覆盖基底上的第一半导体芯片;电互连件,在基底上的第一模制层中延伸;第二模制层,位于第一模制层上,第二模制层具有比第一模制层窄的底表面、比底表面窄的顶表面和在相对于基底的顶表面非垂直的倾斜的方向上延伸的侧壁表面;以及第二半导体芯片,嵌入第二模制层中,第二半导体芯片包括设置在其顶表面处的芯片焊盘;
在下封装件上形成重分配布线层图案,并且使重分配布线层图案电连接至互连件和下封装件的第二半导体芯片的芯片焊盘两者;以及
将第三半导体芯片安装到下封装件,使第三半导体芯片设置于重分配布线层图案上并电连接至重分配布线层图案,
其中,所述第一半导体芯片在其底表面上具有芯片焊盘,
其中,所述基底设置在第一半导体芯片的底表面和第一模制层的底表面上,并且
其中,所述第一半导体芯片的芯片焊盘电连接到基底。
12.根据权利要求11所述的方法,其中,第二模制层暴露芯片焊盘。
13.根据权利要求11所述的方法,其中,第一模制层和第二模制层暴露互连件的顶表面。
14.根据权利要求11所述的方法,其中,第二模制层暴露第一模制层的顶表面的至少一部分,以及
重分配布线层图案沿第二模制层的顶表面、第二模制层的侧壁表面以及第一模制层的被第二模制层暴露的顶表面延伸。
15.根据权利要求11所述的方法,所述方法还包括:
形成粘附膜,使粘附膜置于第一模制层和第二模制层之间。
16.根据权利要求11所述的方法,其中,形成重分配布线层图案的步骤包括:
在第一模制层和第二模制层上形成第一绝缘图案,第一绝缘图案具有暴露芯片焊盘的第一开口和暴露互连件的第二开口;
在第一绝缘图案上形成导电图案,导电图案延伸至第一开口和第二开口内;以及
在导电图案上形成第二绝缘图案。
17.根据权利要求11所述的方法,其中,重分配布线层图案被形成为在平行于侧壁表面的所述倾斜的方向的同时沿着第二模制层的侧壁表面分层地延伸。
18.根据权利要求11所述的方法,其中,第三半导体芯片包括设置于第三半导体芯片的底表面处的焊盘,
重分配布线层图案电连接至第三半导体芯片的焊盘。
19.一种半导体封装件,所述半导体封装件包括:
第一封装件,所述第一封装件包括:基底;第一半导体芯片,安装在基底上并包括设置在第一半导体芯片的底表面处的焊盘;第一模制层,覆盖基底上的第一半导体芯片;至少一个电互连件,在第一模制层内,其中,基底形成在第一半导体芯片的底表面和第一模制层的底表面上;
第二封装件,所述第二封装件包括:第二半导体芯片,设置在第一模制层上并具有芯片焊盘、与第一模制层分隔开的底表面和芯片焊盘所位于的顶表面;以及第二模制层,覆盖第二半导体芯片的底表面和侧面,第二模制层具有在与基底的顶表面平行的给定方向上比第一封装件窄的底表面、在所述给定方向上比第二模制层的底表面窄的顶表面以及在相对于基底的顶表面非垂直的倾斜的方向上延伸的侧壁表面;
重分配布线层图案,沿第一模制层的顶表面、第二模制层的侧壁表面和第二模制层的顶表面延伸,重分配布线层图案电连接至互连件和芯片焊盘;
第三半导体芯片,设置于重分配布线层图案上。
20.根据权利要求19所述的半导体封装件,其中,粘附膜置于第一模制层和第二模制层之间。
21.根据权利要求19所述的半导体封装件,其中,设置于第二模制层的侧壁表面上的重分配布线层图案与所述倾斜的方向平行地延伸。
22.根据权利要求19所述的半导体封装件,其中,第二封装件暴露第一模制层的顶表面的至少一部分和互连件的顶表面。
23.根据权利要求19所述的半导体封装件,所述半导体封装件还包括覆盖第三半导体芯片的第三模制层。
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US20170170154A1 (en) | 2017-06-15 |
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