CN109194333B - Composite structure successive approximation analog-to-digital converter and quantization method thereof - Google Patents

Composite structure successive approximation analog-to-digital converter and quantization method thereof Download PDF

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CN109194333B
CN109194333B CN201810900483.9A CN201810900483A CN109194333B CN 109194333 B CN109194333 B CN 109194333B CN 201810900483 A CN201810900483 A CN 201810900483A CN 109194333 B CN109194333 B CN 109194333B
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张启辉
张中
钱莹莹
宁宁
于奇
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University of Electronic Science and Technology of China
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    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
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    • H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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Abstract

A successive approximation analog-to-digital converter with a composite structure and a quantization method thereof belong to the technical field of analog-to-digital conversion. The digital-to-analog conversion module comprises a capacitance weight type digital-to-analog conversion unit and a serial capacitance type digital-to-analog conversion unit, and the successive approximation logic module comprises a capacitance weight type successive approximation logic unit and a serial successive approximation logic unit which are respectively used for controlling the capacitance weight type digital-to-analog conversion unit and the serial capacitance type digital-to-analog conversion unit. The invention uses the capacitance weighted digital-analog conversion unit to sample and realizes the quantification of analog input through two-step conversion, the comparison module compares the voltage signal output by the digital-analog conversion module with the reference signal, and the obtained comparison result is converted into the output code of the composite structure successive approximation analog-digital converter through the successive approximation logic module. The invention has the advantages of high area efficiency, low power consumption, high conversion speed and the like.

Description

Composite structure successive approximation analog-to-digital converter and quantization method thereof
Technical Field
The invention belongs to the technical field of analog-digital conversion, and particularly relates to a successive approximation analog-digital converter with a composite structure and a quantization method thereof.
Background
Analog-to-digital converters are widely used in the fields of image processing, digital video, biomedical, and the like. For handheld mobile terminal devices (such as image sensors) which are increasingly widely used, low power consumption plays a crucial role in the service life of product batteries. Meanwhile, with the higher requirements of people on the sensory experience of image quality and the like and the pursuit of more detailed data information, the analog-digital converter system is required to have higher conversion speed and higher resolution precision.
The conventional N-bit binary capacitance weighted successive approximation analog-to-digital converter is shown in fig. 1, and includes a binary capacitance weighted digital-to-analog converter C-DAC101, a sample-and-hold circuit S/H102, a comparator CMP103, and a successive approximation logic sarlog 104. Wherein, the output end of the binary capacitance weighted digital-analog converter C-DAC101 is connected to the input negative end of the comparator CMP103, the output end of the sample hold circuit S/H102 is connected to the input positive end of the comparator CMP103, the output end of the comparator CMP103 is connected to the input end of the successive approximation Logic SAR Logic104, the output end of the successive approximation Logic SAR Logic104 outputs the switch control signal of the binary capacitance weighted digital-analog converter C-DAC101
In the binary capacitance weighted successive approximation analog-digital converter, the timing control comprises a sampling phase and a quantization phase. In the sampling phase, the input signal is sampled by the sample and hold circuit S/H102. During the quantization stage, starting from the highest bit quantization capacitor under the drive of the clock CLK, the successive approximation logic104 provides control logic to switch the voltage at the output end of the binary capacitor weighted digital-analog converter C-DAC101, and then the comparator CMP103 compares the voltage at the output end of the binary capacitor weighted digital-analog converter C-DAC101 with the sampling voltage V output by the sample-and-hold circuit S/H102HComparing and giving a comparator result, judging whether the bit quantization capacitor needs to be switched back or not by the successive approximation Logic SAR Logic104 according to the comparison result, and giving a control Logic of the next bit quantization capacitor, and repeating the steps until the lowest bit quantization capacitor is switched.
It can be seen that, for the binary capacitance weighted digital-to-analog converter C-DAC101, the number and area of unit capacitors and the resolution N increase exponentially, and the huge number of capacitors may cause too high power consumption and area, and generally, the resolution achieved by the conventional N-bit binary capacitance weighted successive approximation type analog-to-digital converter structure does not exceed 10 bits.
FIG. 2 shows an N-bit capacitive Serial successive approximation type analog-to-digital converter, which includes a Serial-to-DAC 201 (C)1＝C2) Sample and hold circuit S/H202, comparator CMP203, serial successive approximation logic 204. The output end of the Serial capacitance digital-to-analog converter Serial-to-DAC 201 is connected to the negative input end of the comparator CMP203, the output end of the sample-and-hold circuit S/H202 is connected to the positive input end of the comparator CMP203, the output end of the comparator CMP203 is connected to the input end of the Serial successive approximation logic 204, and the output end of the Serial successive approximation logic 204 outputs the switch control signal of the Serial capacitance digital-to-analog converter Serial-to-DAC 201.
In the capacitance serial successive approximation analog-digital converter, the timing control also includes a sampling phase and a quantization phase. In the sampling phase, the input signal is sampled by the sample and hold circuit S/H202. During the quantization phase, driven by the clock CLK, the specific operation flow of the Serial successive approximation logic 204 for the Serial capacitive digital-to-analog converter Serial-DAC201 is as follows:
1) a reset phase. To the first series capacitor C1Charging, second series capacitance C2Reset, the switching action is as follows: the first switch S is switched off1And a third switch S3And a fourth switch S4Closing the second switch S2And a fifth switch S5。
2) A charge distribution phase. If this is the first quantization, then this step is skipped. Otherwise, the first serial capacitor C is controlled in a first-in first-out serial output mode according to the quantization results of the previous times1A charge or discharge operation. Switching action: the first switch S is switched off1And a fourth switch S4Closing the fifth switch S5When the last quantized output code is 0, the second switch S is turned off2Closing the third switch S3(ii) a When the last quantized output code is 1, the third switch S is turned off3Closing the second switch S2。
3) And a charge sharing stage. Storing the last stage in the first series capacitor C1And a second series capacitor C2Is re-leveled to the total chargeAre both distributed over the two capacitors. The switching action is as follows: the second switch S is turned off2And a third switch S3And a fourth switch S4And a fifth switch S5Closing the first switch S1。
4) And a voltage comparison stage. A second serial capacitor C2Is connected to the negative input terminal of the comparator CMP203 and is connected to the sampled voltage V of the positive input terminal of the comparator CMP203HCompare and give a comparator result. The switching action is as follows: the first switch S is switched off1A second switch S2And a third switch S3And a fifth switch S5Closing the fourth switch S4。
Starting with the most significant code value, the above control logic cycles through until the least significant code value is successfully output. Although the Serial-to-digital-to-analog converter Serial-to-DAC 201 has the number of unit capacitors always kept at 2 no matter how the resolution N of the Serial-to-successive approximation analog-to-digital converter increases, the Serial-to-digital-to-analog converter has two excellent characteristics of high area efficiency and low power consumption. However, compared with the N-bit binary capacitance weighted successive approximation type analog-digital converter, the number of the periods of the quantization stage is increased from the previous N periods to the existing N periods
Figure BDA0001759245410000021
And (4) one period. Higher resolution means more conversion cycles, which poses a serious challenge to implementing high speed analog to digital converters. Worse, in the serial capacitive digital-to-analog converter C-DAC201, since the switch is directly connected to the upper plate of the capacitor, extra channel charge is introduced into the capacitor each time the switch is opened and closed, so that the capacitor C is charged2Voltage V at output terminalDACGenerating non-linearities that limit various performances of the analog-to-digital converter ADC, including integral non-linearity (INL), differential non-linearity (DNL), Spurious Free Dynamic Range (SFDR), significant bit number (ENOB), etc.; therefore, the resolution of the analog-digital converter of the common capacitance serial successive approximation type is not more than 8 bits.
For the two conventional architectures of successive approximation analog-to-digital converters described above, the input common mode level of the comparator must meet the input signal range if the use of an additional sample-and-hold circuit is considered. However, the limited common mode rejection ratio of the comparator causes the input offset of the comparator to be dependent on the input common mode level, thereby deteriorating the overall performance of the analog-to-digital converter. In general, the resolution of successive approximation analog-to-digital converter implementation in this sampling mode does not exceed 8 bits.
Disclosure of Invention
Aiming at a series of defects of low area efficiency and high power consumption of the traditional binary capacitance weight type successive approximation type analog-digital converter, low speed and introduced channel charge of the capacitance serial successive approximation type analog-digital converter, correlation of comparator input common mode level along with input signals in the traditional sampling mode and the like, the invention provides a successive approximation analog-digital converter with a composite structure and a quantization method thereof, wherein the successive approximation analog-digital converter with the composite structure uses a capacitance weight type digital-analog conversion unit 302 for sampling and realizes the quantization of analog input through two-step conversion, and the first step uses the capacitance weight type digital-analog conversion unit 302 as a core to realize the quantization of high bits; the second step is to use the second serial capacitor C in the serial capacitive digital-to-analog converting unit 301 based on the serial capacitive digital-to-analog converting unit 3012The stored charges are transferred to the capacitive weighted digital-to-analog conversion unit 302, so that a smaller step voltage is generated at the high-order output end of the capacitive weighted digital-to-analog conversion unit 302 to realize the conversion of the low order bits; after the charge transfer, channel charges introduced due to the on or off of the switch are well inhibited, so that the whole circuit absorbs the advantages of high area efficiency, low power consumption and high conversion speed of two traditional successive approximation analog-to-digital converters, and simultaneously, the input common mode level of the comparison module 303 is independent of an input signal due to the optimization of the sampling mode, and the input offset of the comparison module 303 is ensured to be independent of the input signal.
The technical scheme of the invention is as follows:
a composite structure successive approximation analog-to-digital converter comprises a digital-to-analog conversion module, a comparison module 303 and a successive approximation logic module 304,
the digital-to-analog conversion module comprises a capacitance weighted digital-to-analog conversion unit 302 and a serial capacitance digital-to-analog conversion unit 301, wherein the low-order output end of the capacitance weighted digital-to-analog conversion unit 302 is connected with the output end of the serial capacitance digital-to-analog conversion unit 301, and the high-order output end of the capacitance weighted digital-to-analog conversion unit is connected with the input end of the comparison module 303;
the comparison module 303 compares the voltage signal output by the capacitance weighted digital-to-analog converter unit 302 with a reference signal, and the obtained comparison result is converted into an output code of the composite structure successive approximation analog-to-digital converter through the successive approximation logic module 304;
the successive approximation logic module 304 includes a capacitance weighted successive approximation logic unit for controlling a switch in the capacitance weighted digital-to-analog conversion unit 302 and a serial successive approximation logic unit for controlling a switch in the serial capacitance digital-to-analog conversion unit 301.
Specifically, the serial capacitive digital-to-analog conversion unit 301 includes a first serial capacitor C1A second serial capacitor C2A first switch S1A second switch S2And a third switch S3And a fourth switch S4And a fifth switch S5Wherein the first series capacitor C1And a second series capacitor C2Are equal;
first switch S1Connected to the first series capacitor C1Upper plate of and a second series capacitor C2Between the upper polar plates;
a second switch S2Connected to the first series capacitor C1Upper plate of and a high reference voltage VTTo (c) to (d);
third switch S3Connected to the first series capacitor C1Upper plate of and low reference voltage VBTo (c) to (d);
fourth switch S4One end of is connected with a second serial capacitor C2Upper pole ofThe other end of the plate is used as the output end of the serial capacitance type digital-to-analog conversion unit 301;
fifth switch S5Is connected to the second serial capacitor C2Upper plate of and low reference voltage VBTo (c) to (d);
first series capacitor C1And a second series capacitor C2The lower polar plate is connected with a low reference voltage VB。
Specifically, the capacitance weighted digital-to-analog conversion unit 302 includes a high-stage capacitor array, a low-stage capacitor array, and a coupling capacitor CSAnd a reset switch;
the high-stage capacitor array comprises a plurality of capacitors, the upper electrode plates of all the capacitors of the high-stage capacitor array are connected with the high-order output end of the capacitor weight type digital-to-analog conversion unit 302, and the lower electrode plates are respectively connected with the low reference voltage V through switchesBHigh reference voltage VTOr an input voltage VIN；
The low-stage capacitor array comprises a plurality of capacitors, wherein the upper plate of the lowest capacitor of the low-stage capacitor array is connected with the upper plates of the rest capacitors of the low-stage capacitor array after passing through a switch and is connected with the low-stage output end of the weighted digital-to-analog conversion unit 302 of the capacitor, and the lower plate of the low-stage capacitor array is connected with a low reference voltage VB(ii) a The lower pole plates of the rest capacitors of the low-section capacitor array are respectively connected with a low reference voltage V after passing through switchesBOr a high reference voltage VT；
Coupling capacitor CSIs connected between the high-order output end and the low-order output end of the capacitance weighted digital-to-analog conversion unit 302;
the reset switch comprises a high-stage reset switch SHAnd a low-stage reset switch SLSaid high-stage reset switch SHThe high-order output end of the capacitance weighted digital-to-analog conversion unit 302 is connected with a high reference voltage VTIn the low stage reset switch SLA low reference voltage V connected to the low-order output terminal of the capacitance weighted digital-to-analog conversion unit 302BIn the meantime.
A quantification method of a composite structure successive approximation analog-to-digital converter comprises a digital-to-analog conversion module, wherein the digital-to-analog conversion module comprises a capacitance weighted digital-to-analog conversion unit 302 and a serial capacitance digital-to-analog conversion unit 301;
the serial capacitive digital-to-analog conversion unit 301 comprises a first serial capacitor C1A second serial capacitor C2A first switch S1A second switch S2And a third switch S3And a fourth switch S4And a fifth switch S5Wherein the first series capacitor C1And a second series capacitor C2Are equal;
first switch S1Connected to the first series capacitor C1Upper plate of and a second series capacitor C2Between the upper polar plates;
a second switch S2Connected to the first series capacitor C1Upper plate of and a high reference voltage VTTo (c) to (d);
third switch S3Connected to the first series capacitor C1Upper plate of and low reference voltage VBTo (c) to (d);
fourth switch S4One end of is connected with a second serial capacitor C2The other end of the upper polar plate is used as the output end of the serial capacitance type digital-to-analog conversion unit 301;
fifth switch S5Is connected to the second serial capacitor C2Upper plate of and low reference voltage VBTo (c) to (d);
first series capacitor C1And a second series capacitor C2The lower polar plate is connected with a low reference voltage VB；
The capacitance weighted digital-to-analog conversion unit 302 comprises a high-stage capacitor array and a low-stage capacitor array;
the high-stage capacitor array comprises M +1 quantization capacitors, the upper electrode plates of the M +1 quantization capacitors are all connected with the high-order output end of the capacitor weight type digital-to-analog conversion unit 302, and the lower electrode plates are respectively connected with a low reference voltage V through switchesBHigh reference voltage VTOr an input voltage VIN；
The low-stage capacitor array comprises L quantized capacitors, and the upper plate of the lowest quantized capacitor of the low-stage capacitor array passes through a switch S of the upper plate of the lowest quantized capacitorTThen connected to the upper plate of the other quantized capacitors of the low-stage capacitor array and connected to the low-order output terminal of the weighted DAC unit 302, and the lower plate thereof is connected to a low reference voltage VB(ii) a The lower pole plates of the rest quantized capacitors of the low-section capacitor array are respectively connected with a low reference voltage V after passing through switchesBOr a high reference voltage VT；
The reset switch comprises a high-stage reset switch SHAnd a low-stage reset switch SLSaid high-stage reset switch SHThe high-order output end of the capacitance weighted digital-to-analog conversion unit 302 is connected with a high reference voltage VTIn the low stage reset switch SLA low reference voltage V connected to the low-order output terminal of the capacitance weighted digital-to-analog conversion unit 302BTo (c) to (d);
the composite structure successive approximation analog-to-digital converter carries out P + Q times of quantization, wherein P is M + L, Q is a positive integer, and the quantization process comprises the following steps:
a. turn off the fourth switch S4The digital-to-analog conversion module only includes the capacitance weighted digital-to-analog conversion unit 302, and quantizes the capacitance weighted digital-to-analog conversion unit 302 to obtain the high P bits of the output code of the successive approximation analog-to-digital converter with the composite structure;
b. closing the fourth switch S4The digital-to-analog conversion module comprises a capacitance weighted digital-to-analog conversion unit 302 and a serial capacitance digital-to-analog conversion unit 301, and the digital-to-analog conversion module is sequentially subjected to low-Q quantization to obtain a low-Q bit of an output code of the successive approximation analog-to-digital converter with the composite structure, wherein j is a positive integer and P +1 is not less than j and not more than P + Q:
b1, opening the first switch S1And a third switch S3And a fourth switch S4Closing the second switch S2And a fifth switch S5A first series capacitor C1Electricity (D) fromCharging to CU×(VT-VB) Second series capacitor C2Initializing the charge of (a) to 0;
b2, opening the second switch S2And a third switch S3And a fourth switch S4And a fifth switch S5Closing the first switch S1A first series capacitor C1And a second series capacitor C2Is equally distributed to the first series capacitance C1And a second series capacitor C2The above step (1);
b3, connecting the lower plates of all the quantization capacitors in the capacitance weighted digital-to-analog conversion unit 302 with a low reference voltage VBClosing the high-stage reset switch SHAnd a low-stage reset switch SLConnecting the upper plates of all the quantization capacitors of the low-stage capacitor array in the capacitor weighted digital-to-analog conversion unit 302 with a low reference voltage VBConnecting the upper electrode plates of all the quantized capacitors of the high-section capacitor array with a high reference voltage VT；
b4, if j is P +1, performing step b6, and if j > P +1, performing step b 5;
b5, starting from the j-1 th bit of the output code of the composite structure successive approximation analog-digital converter to the P +1 th bit, sequentially judging whether the first serial capacitor C is the second serial capacitor C according to the value of the s-th bit of the output code of the composite structure successive approximation analog-digital converter1Charging or discharging is carried out, wherein s is a positive integer, P +1 is not less than s not more than j-1, and the specific judgment method is as follows:
b51, when the S-th bit of the output code of the successive approximation analog-to-digital converter with the composite structure is 0, the second switch S is switched off2Closing the third switch S3A first series capacitor C1The charge of (2) is discharged to 0; when the S-th bit of the output code of the successive approximation analog-to-digital converter with the composite structure is 1, the third switch S is switched off3Closing the second switch S2A first series capacitor C1Charge of to CU×(VT-VB)；
b52, repeating the step b 2;
b6, turning off the high-stage reset switch S in sequenceHMost preferablyLow-order quantization capacitor upper plate switch STAnd a low-stage reset switch SL；
b7, opening the first switch S1And a fifth switch S5Closing the fourth switch S4A second serial capacitor C2Accessing the capacitance weight type digital-to-analog conversion unit 302 to obtain an output signal of a high-order output end of the capacitance weight type digital-to-analog conversion unit 302;
b8, comparing the output signal of the high-order output end of the capacitance weighted digital-to-analog converter unit 302 with a reference signal to obtain the j-th-order output code of the successive approximation analog-to-digital converter with the composite structure.
The invention has the beneficial effects that: the digital-to-analog conversion module comprises a capacitance weighted digital-to-analog conversion unit 302 and a serial capacitance digital-to-analog conversion unit 301, so that the whole quantization process is divided into two steps, wherein the first step takes the capacitance weighted digital-to-analog conversion unit 302 as a core to realize the quantization of high P bits, and the second step takes the serial capacitance digital-to-analog conversion unit 301 as a basis to convert a second serial capacitance C into a second serial capacitance C through a reasonable time sequence2The stored charges are transferred to the capacitance weighted digital-to-analog conversion unit, so that smaller step voltage is generated at the output end of the digital-to-analog conversion module to realize the conversion of low Q bits; the channel charge introduced by the on or off of the switch is well inhibited at the output end of the digital-to-analog conversion module due to the charge transfer effect, so the total unit capacitance is 2 of the N-bit capacitance type binary weight successive approximation type analog-to-digital converterNDown to 2M+2L+2, conversion period from N-bit capacitance type serial successive approximation type A/D converter
Figure BDA0001759245410000061
Is reduced to
Figure BDA0001759245410000062
Therefore, the invention has high area efficiency, low power consumption and high conversion speed. Because the composite structure successive approximation analog-to-digital converter uses a capacitance weighted digital modeThe high-section capacitor in the analog conversion unit 302 is sampled, so that the input common-mode level of the comparator is independent of the input signal, and the input offset of the comparator is independent of the input signal.
Drawings
FIG. 1 is a circuit diagram of a conventional N-bit capacitive binary weighted successive approximation analog-to-digital converter.
Fig. 2 is a circuit diagram of a conventional N-bit capacitive serial successive approximation analog-to-digital converter.
Fig. 3 is a schematic structural diagram of a successive approximation analog-to-digital converter with a composite structure according to the present invention.
Fig. 4 is a schematic structural diagram of a fully differential successive approximation analog-to-digital converter with a composite structure according to the present invention.
Fig. 5 is a schematic diagram of a dynamic monte carlo simulation result of a successive approximation analog-to-digital converter with a composite structure according to the present invention.
Fig. 6 is a schematic diagram of a simulation result of static performance monte carlo of a successive approximation analog-to-digital converter with a composite structure according to the present invention.
Fig. 7 is a schematic diagram of a simulation result of capacitance switching power consumption of a successive approximation analog-to-digital converter with a composite structure according to the present invention.
Detailed Description
The technical scheme of the invention is further explained by embodiments in the following with reference to the attached drawings.
Fig. 3 shows an overall schematic structure diagram of a successive approximation analog-to-digital converter with a composite structure according to the present invention, which includes a digital-to-analog conversion module, a comparison module 303, and a successive approximation logic module 304. The digital-to-analog conversion module comprises a capacitance weighted digital-to-analog conversion unit 302 and a serial capacitance digital-to-analog conversion unit 301, wherein the low-order output end of the capacitance weighted digital-to-analog conversion unit 302 is connected with the output end of the serial capacitance digital-to-analog conversion unit 301, and the high-order output end of the capacitance weighted digital-to-analog conversion unit is connected with the input end of the comparison module 303. The comparison module 303 compares the voltage signal output from the high-order output terminal of the capacitance weighted digital-to-analog converter unit 302 with a reference signal, and the obtained comparison result is converted into an output code of the successive approximation analog-to-digital converter with a composite structure through the successive approximation logic module 304. The successive approximation logic module 304 includes a capacitance weighted successive approximation logic unit and a serial successive approximation logic unit, the capacitance weighted successive approximation logic unit outputs a switch control signal for controlling a switch in the capacitance weighted digital-analog conversion unit 302, and the serial successive approximation logic unit outputs a switch signal for controlling a switch in the serial capacitance digital-analog conversion unit 301.
The structure of the serial capacitive digital-to-analog conversion unit 301 is shown in fig. 3, and includes a first serial capacitor C1A second serial capacitor C2A first switch S1A second switch S2And a third switch S3And a fourth switch S4And a fifth switch S5Wherein the first series capacitor C1And a second series capacitor C2The capacitance values of the first and second capacitors C are equal, and the first serial capacitor C is provided in this embodiment1And a second series capacitor C2Are all unit capacitors CUThe lower polar plates are all connected with a low reference voltage VB. A second switch S2A charge charging switch connected to the first series capacitor C1Upper plate of and a high reference voltage VTBetween, the third switch S3Is a charge discharge switch connected to the first series capacitor C1Upper plate of and low reference voltage VBA second switch S2And a third switch S3For controlling the first series capacitance C1Charging and discharging; first switch S1Is a charge redistribution switch connected to the first series capacitor C1And a second series capacitor C2Between the upper plates of the first and second capacitors for controlling the first series capacitance C1And a second series capacitor C2Redistribution of the charge; fourth switch S4Is an output switch, one end of which is connected with a second serial capacitor C2The other end of the upper polar plate is used as the output end of the serial capacitance type digital-analog conversion unit and is used for connecting the output of the serial capacitance type digital-analog conversion unit to the capacitance weight type digital-analog conversion unit; fifth switch S5Is connected to the second serial capacitor C as a reset switch2Upper plate of and low reference voltage VBIn between, useFor the second serial capacitor C2Resetting is performed.
The capacitance weighted digital-to-analog converter module 302 includes a capacitor array, which may be a segmented structure or a non-segmented structure, and the segmented capacitor array is connected by a coupling capacitor in the segmented structure, and in this embodiment, the structural connection and the working process of the capacitance weighted digital-to-analog converter module 302 with the segmented structure are described in detail by taking the capacitance weighted digital-to-analog converter module 302 as an example.
As shown in FIG. 3, the structure of the segmented capacitor array is shown, and the capacitive weighted DAC module 302 includes the segmented capacitor array and the coupling capacitor CSAnd a reset switch. The capacitor array comprises a high-stage capacitor array and a low-stage capacitor array, wherein the high-stage capacitor array comprises M +1 quantized capacitors, M is a positive integer, upper plates of all the quantized capacitors of the high-stage capacitor array are connected with a high-stage output end of the capacitor weight type digital-to-analog conversion unit 302, and lower plates of the high-stage capacitor array are respectively connected with a low reference voltage V through switches in the quantization processBOr a high reference voltage VT(ii) a Due to the adoption of high-section capacitance sampling, the lower polar plate needs to be connected to the input signal V through the sampling switch in the sampling processIN. The low-stage capacitor array comprises L quantization capacitors, wherein L is a positive integer, and the upper plate of the lowest quantization capacitor of the low-stage capacitor array passes through a switch STThe low-order output end of the post-connection capacitance weight type digital-to-analog conversion unit 302 is connected with the lower pole plate of the post-connection capacitance weight type digital-to-analog conversion unitB(ii) a The upper electrode plates of the other quantized capacitors of the low-stage capacitor array are connected with the low-order output end of the capacitor weight type digital-to-analog conversion unit 302, and the lower electrode plates are respectively connected with a low reference voltage V after passing through switchesBOr a high reference voltage VT(ii) a Coupling capacitor CSConnected between the high-order output terminal and the low-order output terminal of the capacitance weighted digital-to-analog conversion unit 302. The reset switch comprises a high-stage reset switch SHAnd a low-stage reset switch SLHigh-stage reset switch SHConnected to the high-order output terminal of the capacitor weighted digital-to-analog conversion unit 302 and the high reference voltage VTMiddle and low reset switch SLLow and low connected to the low output terminal of the capacitive weighted digital-to-analog conversion unit 302Reference voltage VBIn the meantime.
All quantized capacitances in segmented capacitance weighted digital-to-analog conversion unit 302 are according to highest order Ca21To the lowest position Ca2M+L+1Numbering and recording Ca2i(i ═ 1,2,3, …, M + L +2), and the capacitance value is as shown in formula (1):
Figure BDA0001759245410000081
wherein C isUIs a unit capacitance value, and coupling capacitor C is used to ensure equal weight ratio of the segmented capacitance weighted digital-to-analog conversion unit 302SHas a capacitance value of
Figure BDA0001759245410000082
Weight of high-section capacitor arrayMSB(i) Weight with low-end capacitor arrayLSB(i) Is represented by the formula (2):
Figure BDA0001759245410000091
wherein C isMSB_TotIs the sum of quantized capacitance values of the high-section capacitor array, CLSB_TotIs the sum of quantized capacitance values of the low-stage capacitor array, CSIs the capacitance value of the coupling capacitor.
When the present invention is applied to a single-ended analog-to-digital converter, one input terminal of the comparison module 303 is connected to the voltage signal V output by the high-order output terminal of the capacitance weighted digital-to-analog converter module 302dachThe other input end of the high-voltage power supply is connected with a high reference voltage VTAs a reference signal.
Besides the application in single-end analog-to-digital converter, the successive approximation analog-to-digital converter with composite structure provided by the invention can also be used for quantizing fully differential signals, at the moment, two input ends of a comparison module are respectively connected with the differential output ends of a digital-to-analog conversion module with differential structure, and differential input signals are subjected to capacitance weighted digital-to-analog conversionThe unit 402 generates a differential output signal, and the comparison module compares the difference of the differential output signal with a reference voltage, where the reference voltage is 0. Fig. 4 is a schematic structural diagram of a fully differential successive approximation analog-to-digital converter with a composite structure, which includes a digital-to-analog conversion module with a differential structure, a comparison module 403, and a successive approximation logic module 404. The digital-to-analog conversion module with the differential structure comprises a serial capacitive digital-to-analog conversion unit 401 with the differential structure and a capacitive weighted digital-to-analog conversion unit 402 with the differential structure. The differential output terminal of the capacitance weighted digital-to-analog converter unit 402 is connected to the two input terminals of the comparison module 403, and the comparison module 403 compares the differential output signal V of the capacitance weighted digital-to-analog converter unit 402dach,nAnd Vdach,nThe obtained comparison result is converted into an output code of the successive approximation analog-to-digital converter with a composite structure through the successive approximation logic module 404. Similarly, in the single-ended analog-to-digital converter structure, the successive approximation logic module 404 includes a capacitance weighted successive approximation logic unit and a serial successive approximation logic unit, the capacitance weighted successive approximation logic unit outputs a switch control signal for controlling a switch in the capacitance weighted digital-to-analog conversion unit 402 of the differential structure, and the serial successive approximation logic unit outputs a switch signal for controlling a switch in the serial capacitance digital-to-analog conversion unit 401 of the differential structure.
The quantization bit number of the composite structure successive approximation analog-to-digital converter provided by the invention is P + Q, the quantization method is divided into two parts, the first part is the quantization of high P bit, the second part is the quantization of low Q bit, wherein P and Q are both positive integers, P is determined by a capacitance weighted digital-to-analog conversion unit, the process of quantization is illustrated by taking a single-end successive approximation analog-to-digital converter with a segmented structure as an example of the capacitance weighted digital-to-analog conversion unit 302 shown in FIG. 3, because the capacitance weighted digital-to-analog conversion unit 302 comprises M +1 quantization capacitors, and the low-section capacitor array comprises L quantization capacitors, P is M + L.
When the first part carries out the quantization of high P bits, the fourth switch S is switched4At this time, the DAC module only includes the weighted DAC unit 302, the successive approximation logic block 304 only has a capacitor weighted successive approximation logic unit, the quantization of the high P bit is the same as that of the conventional capacitor weighted successive approximation analog-to-digital converter, the capacitor weighted successive approximation logic unit provides control logic to switch the voltage at the output end of the capacitor weighted digital-to-analog conversion unit 302 from the highest bit capacitor under the drive of the clock CLK, and then the comparator block 303 and the high reference voltage V are used to compare the voltage with the voltage at the output end of the capacitor weighted digital-to-analog conversion unit 302TAnd comparing to obtain a comparison result, judging whether the capacitance of the bit needs to be switched back according to the comparison result, and giving a control logic of the next bit of capacitance by the capacitance weighted successive approximation logic unit, and repeating the steps until the lowest bit of capacitance is switched, so that the successive approximation logic module 304 obtains the high P bit of the output code of the successive approximation analog-to-digital converter with the composite structure according to the comparison result obtained by each switching.
After the quantization of the high P bit is completed, the second serial capacitor C in the serial capacitance type digital-to-analog conversion unit is coded according to the low bit quantization2Performing charge, discharge and charge redistribution operations, closing the fourth switch S4The serial capacitance type digital-analog conversion unit 301 is added into the digital-analog conversion module and is stored in the second serial capacitance C2The charges are transferred to the capacitance weighted digital-to-analog conversion unit 302 in a capacitance exchange manner, so that a smaller step voltage is generated at the output end of the capacitance weighted digital-to-analog conversion unit 302 to realize the quantization of the second part of low Q bits, wherein the j-th quantization specifically comprises the following steps, j is a positive integer, and P +1 is not less than j and not more than P + Q:
1. the first series capacitor C is needed before each bit of the low-K bits is quantized1And a second series capacitor C2Performing initial reset operation, and turning off the first switch S by the output switch control signal of the serial successive approximation logic unit1And a third switch S3And a fourth switch S4Closing the second switch S2And a fifth switch S5Thereby connecting the first series capacitance C1Amount of electric charge Q1Is precharged to CU×(VT-VB) Second series capacitor C2Amount of electric charge Q2Initializing to 0;
2. after the initialization is finished, the first serial capacitor C needs to be connected1And a second series capacitor C2The second switch S is disconnected by the serial successive approximation logic unit outputting a switch control signal2And a third switch S3And a fourth switch S4And a fifth switch S5Closing the first switch S1A first series capacitor C1And a second series capacitor C2Is equally distributed to the first series capacitance C1And a second series capacitor C2The above step (1);
but in the second switch S2And a fifth switch S5While being turned off, the first series capacitors C are respectively connected to the second series capacitors C1And a second series capacitor C2Injecting a certain amount of channel charge + Qchs2、-Qchs5(ii) a At the first switch S1When turned on, will absorb a certain amount of charge-Qchs1，iTherefore, the first series capacitor C is formed after the charge sharing is finished1Amount of electric charge Q1And a second series capacitor C2Amount of electric charge Q2Respectively shown in formula (3):
Figure BDA0001759245410000101
3. before the charge transfer of the following steps, the capacitor weighted digital-to-analog conversion unit needs to be reset to ensure the second serial capacitor C2The charge can be correctly transferred, and the resetting step is to connect the lower plates of all the quantization capacitors in the capacitance weighted digital-to-analog conversion unit with a low reference voltage VBClosing the reset switch to connect the upper plates of all the quantized capacitors of the low-stage capacitor array 302 in the capacitor weighted digital-to-analog conversion unit with a low reference voltage VBThe upper polar plates of all the quantized capacitors of the high-section capacitor array are connected with a high reference voltage VT(ii) a Step 3 may be performed simultaneously with steps 1 and 2;
4. after the above steps, if the quantization of j ═ P +1 bits is performed at this time, step 6 is performed; if the quantization of j > P +1 bits is performed at this time, step 5 is performed;
5. starting from the j-1 th bit of the output code of the successive approximation analog-to-digital converter with the composite structure until the P +1 th bit, and judging the first serial capacitor C according to the value of the s-th bit of the output code of the successive approximation analog-to-digital converter with the composite structure1S is a positive integer, P +1 is more than or equal to s is less than or equal to j-1, namely, the first serial capacitor C is judged according to the j-1 th bit of the output code of the successive approximation analog-to-digital converter with the composite structure1After the state of (1), carrying out charge sharing once, namely step 2, and then judging the first serial capacitor C according to the j-2 th bit of the output code of the successive approximation analog-to-digital converter with the composite structure1The first serial capacitor C is judged according to the P +1 th bit of the output code of the composite structure successive approximation analog-to-digital converter1After the first charge sharing is performed, step 6 is performed, in which the first serial capacitor C is determined1The specific method of the state of (1) is as follows:
5.1, when the S-th bit of the output code of the successive approximation analog-to-digital converter with the composite structure is 0, disconnecting the second switch S2Closing the third switch S3A first series capacitor C1The charge of (2) is discharged to 0; when the S-th bit of the output code of the successive approximation analog-to-digital converter with the composite structure is 1, the third switch S is switched off3Closing the second switch S2A first series capacitor C1Charge of to CU×(VT-VB)；
5.2, repeating the step 2, namely turning off the second switch S by outputting a switch control signal through the serial successive approximation logic unit 3012And a third switch S3And a fourth switch S4And a fifth switch S5Closing the first switch S1A first series capacitor C1And a second series capacitor C2Is equally distributed to the first series capacitance C1And a second series capacitor C2The above step (1);
6. before the charge transfer, the high-section capacitance reset switch S is turned off in sequenceHLowest order quantization capacitor CM+L+1Upper polar plate openingOff STAnd a low-stage reset switch SL(ii) a Due to channel electric injection, the charge of the upper electrode plate node of the low-stage capacitor array is not 0, but is the high-stage capacitor reset switch SHLowest order quantization capacitor CM+L+1Upper polar plate switch STAnd a low-stage reset switch SLSum of injected charge amounts Q of three switchesS；
7. The charge transfer is carried out, and the first switch S is turned off1And a fifth switch S5Closing the fourth switch S4A second serial capacitor C2A capacitance weighted digital-to-analog conversion unit 302 is accessed; at this time, the second serial capacitors C are respectively connected to2Injecting and absorbing a certain amount of channel charge-Qchs1,o、+Qchs4. The charge of the upper plate of the low-stage capacitor array of the final capacitive weighted digital-to-analog conversion unit 302 is as shown in equation (4):
Figure BDA0001759245410000111
8. after the charge transfer is finished, the capacitance weighted successive approximation logic unit generates a switch control signal according to the high P-bit quantization code to control the quantization capacitance lower plate switch of the capacitance weighted digital-analog conversion unit 302, so as to obtain a voltage signal V at the output end of the capacitance weighted digital-analog conversion unit 302dachAs shown in formula (5):
Figure BDA0001759245410000121
wherein C isMSB_Tot＝2M×CU，CLSB_Tot＝(2L-1)×CU。
9. Voltage signal V at output end of capacitance weighted digital-to-analog conversion unit 302dachAnd a high reference voltage VTAnd comparing to obtain the j bit output code of the successive approximation analog-to-digital converter with the composite structure.
It can be found by the equation (5) that the influence of the channel charge of the switching MOS on the output voltage is attenuated by 2M+L+2L-1 time. In the unit capacitance CU100fF, high reference voltage VT1.9V, low reference voltage VBWhen the voltage is equal to 0.7V, the channel charge can be applied to the second serial capacitor C by setting appropriate switch and virtual switch sizes2The introduced voltage deviation is controlled to be 3 delta less than or equal to 5mV, namely the formula (6):
Figure BDA0001759245410000122
therefore, for a capacitive serial successive approximation analog-to-digital converter, the resolution does not generally exceed 8 bits. But the influence of the channel charge on the output voltage can be greatly suppressed by the charge transfer technique. When P + Q is 14, P is 9, M is 6, and L is 3, the deviation generated by channel charge injection is 5mV/519 ≈ 9.63 μ V which is much smaller than 14 bits 1LSB ≈ 72.82 μ V. Therefore, the output end voltage V of the upper polar plate of the high-section capacitordachIt can be abbreviated as formula (7):
Figure BDA0001759245410000123
at the moment, the voltage V at the output end of the upper polar plate of the high-section capacitordachThe variable quantity of the capacitor weight type digital-to-analog conversion unit is equivalent to the lowest bit quantization capacitor C of the capacitor weight type digital-to-analog conversion unitM+L+1Half of the weight, extending the resolution from M + L bits to M + L +1 bits.
Matlab simulation is performed on the successive approximation analog-to-digital converter with the composite structure, and a schematic diagram of a dynamic performance (no stray dynamic range SFDR, effective digit ENOB) Monte Carlo simulation result, a schematic diagram of a static performance (differential nonlinear DNL, integral nonlinear INL) Monte Carlo simulation result and a schematic diagram of a capacitor switching power consumption simulation result of the successive approximation analog-to-digital converter are obtained, and are respectively shown in fig. 5, 6 and 7, in simulation setting, a unit capacitance value is CU100uf, unit capacitance mismatch error of
Figure BDA0001759245410000124
The number of monte carlo simulations was 1000.
From simulation results, the composite structure successive approximation analog-to-digital converter still has good dynamic performance and excellent static indexes on the premise of ensuring high area efficiency, and the average values of the Spurious Free Dynamic Range (SFDR), the effective Bit number (ENOB), the Differential Nonlinearity (DNL) and the Integral Nonlinearity (INL) after 1000 times of simulation are respectively 88.5dB, 13.21Bit, 0.994LSB and 1.655 LSB. The switching power consumption of the switched capacitor is only 77.8662CV because the whole capacitor array has extremely high area efficiency2. Therefore, the composite structure successive approximation analog-to-digital converter provided by the invention has excellent performance indexes.
The capacitance weighted digital-to-analog converter in the conventional capacitance binary weight successive approximation analog-to-digital converter is based on the principle of charge conservation, that is, the initial charge of the conventional capacitance binary weight successive approximation analog-to-digital converter is fixed and is also kept unchanged in the quantization process, and if the initial charge is modified, quantization errors are caused. While the single capacitive serial successive approximation type analog-to-digital converter is almost a failed structure, under the current CMOS process, the requirement of high speed and high precision can not be realized at all due to charge injection, and since the framework is proposed in 1978, the framework is never used again. The invention provides a composite structure successive approximation analog-to-digital converter and a quantization method thereof, because a digital-to-analog conversion module comprises a serial capacitance type digital-to-analog conversion unit 301 and a capacitance weight type digital-to-analog conversion unit 302, the whole quantization process is divided into two steps of quantization: the first step is to realize the quantization of the high P bit by taking a capacitance weighted digital-to-analog conversion unit 302 as a core; the second step is to use the second serial capacitor C based on the serial capacitor type digital-to-analog conversion unit 3012The stored charge is transferred to the capacitance weighted digital-to-analog converting unit 302, so that a smaller step voltage is generated at the output end of the capacitance weighted digital-to-analog converting unit 302 to realize the conversion of the low Q bit. The quantization process is combined with a charge transfer method to reasonably transfer the charge of the serial capacitance type digital-to-analog conversion unit into the capacitance weight type digital-to-analog conversion unit, so that the initial charge quantity of the capacitance weight type digital-to-analog conversion unit is modifiedAnd due to the charge transfer effect, channel charges introduced by the on or off of the switch are well inhibited, so that the whole circuit has high area efficiency, low power consumption and high conversion speed. Because the successive approximation analog-to-digital converter with the composite structure can use the high-section capacitor sampling in the capacitor weighted digital-to-analog conversion unit 302, the input common-mode level of the comparison module is independent of the input signal, and the input offset of the comparison module is ensured to be independent of the input signal.
It should be noted that although the contents of the composite-structure successive approximation analog-to-digital converter and the quantization method thereof proposed by the present invention have been disclosed by way of example, the present invention is not limited thereto, and those skilled in the art should make insubstantial changes or modifications without departing from the spirit of the present invention, which fall within the scope of the appended claims.

Claims (4)

1. A composite structure successive approximation analog-to-digital converter comprises a digital-to-analog conversion module, a comparison module (303) and a successive approximation logic module (304),
the digital-to-analog conversion module is characterized by comprising a capacitance weighted digital-to-analog conversion unit (302) and a serial capacitance digital-to-analog conversion unit (301), wherein the low-order output end of the capacitance weighted digital-to-analog conversion unit (302) is connected with the output end of the serial capacitance digital-to-analog conversion unit (301), and the high-order output end of the capacitance weighted digital-to-analog conversion unit is connected with the input end of the comparison module (303);
the comparison module (303) compares the voltage signal output by the capacitance weighted digital-to-analog converter unit (302) with a reference signal, and the obtained comparison result is converted into an output code of the composite structure successive approximation analog-to-digital converter through the successive approximation logic module (304);
the successive approximation logic module (304) comprises a capacitance weighted successive approximation logic unit and a serial successive approximation logic unit, wherein the capacitance weighted successive approximation logic unit is used for controlling a switch in the capacitance weighted digital-analog conversion unit (302), and the serial successive approximation logic unit is used for controlling a switch in the serial capacitance digital-analog conversion unit (301).
2. The composite successive approximation analog-to-digital converter according to claim 1, characterized in that said serial capacitive digital-to-analog conversion unit (301) comprises a first serial capacitance (C)1) A second serial capacitor (C)2) A first switch (S)1) A second switch (S)2) And a third switch (S)3) And a fourth switch (S)4) And a fifth switch (S)5) Wherein the first series capacitance (C)1) And a second series capacitance (C)2) Are equal;
a first switch (S)1) Connected to the first series capacitor (C)1) And a second serial capacitor (C)2) Between the upper polar plates;
a second switch (S)2) Connected to the first series capacitor (C)1) And a high reference voltage (V)T) To (c) to (d);
third switch (S)3) Connected to the first series capacitor (C)1) Upper plate of (d) and a low reference voltage (V)B) To (c) to (d);
fourth switch (S)4) Is connected to the second serial capacitance (C)2) The other end of the upper polar plate is used as the output end of the serial capacitance type digital-to-analog conversion unit (301);
fifth switch (S)5) Is connected to the second serial capacitor (C)2) Upper plate of (d) and a low reference voltage (V)B) To (c) to (d);
first series capacitance (C)1) And a second series capacitance (C)2) Is connected with a low reference voltage (V)B)。
3. The composite successive approximation analog-to-digital converter according to claim 1, characterized in that the capacitance weighted digital-to-analog conversion unit (302) comprises a high-stage capacitor array, a low-stage capacitor array, a coupling capacitor (C)S) And a reset switch;
the high-section capacitor array comprises a plurality of capacitors, and all capacitors of the high-section capacitor arrayThe upper polar plates are connected with the high-order output end of the capacitance weight type digital-to-analog conversion unit (302), and the lower polar plates are respectively connected with a low reference voltage (V) through switchesB) High reference voltage (V)T) Or input voltage (V)IN)；
The low-section capacitor array comprises a plurality of capacitors, wherein the upper polar plate of the lowest capacitor of the low-section capacitor array is connected with the upper polar plates of the rest capacitors of the low-section capacitor array after passing through a switch and is connected with the low-position output end of the weighted capacitor digital-to-analog conversion unit (302), and the lower polar plate of the low-section capacitor array is connected with a low reference voltage (V)B) (ii) a The lower electrode plates of the other capacitors of the low-section capacitor array are respectively connected with a low reference voltage (V) after passing through switchesB) Or a high reference voltage (V)T)；
Coupling capacitance (C)S) The capacitor weighted digital-to-analog conversion unit (302) is connected between the high-order output end and the low-order output end of the capacitor weighted digital-to-analog conversion unit;
the reset switch comprises a high-stage reset switch (S)H) And a low-stage reset switch (S)L) Said high-section reset switch (S)H) Connected to the high-order output terminal of the capacitance weighted digital-to-analog conversion unit (302) and a high reference voltage (V)T) In the low stage reset switch (S)L) A low-order output end connected with the capacitance weighted digital-analog conversion unit (302) and a low reference voltage (V)B) In the meantime.
4. The quantization method of the composite structure successive approximation analog-to-digital converter is characterized in that the composite structure successive approximation analog-to-digital converter comprises a digital-to-analog conversion module, and the digital-to-analog conversion module comprises a capacitance weighted digital-to-analog conversion unit (302) and a serial capacitance digital-to-analog conversion unit (301);
the serial capacitive digital-to-analog conversion unit (301) comprises a first serial capacitance (C)1) A second serial capacitor (C)2) A first switch (S)1) A second switch (S)2) And a third switch (S)3) And a fourth switch (S)4) And a fifth switch (S)5) Wherein the first series capacitance (C)1) And a second serial capacitor(C2) Are equal;
a first switch (S)1) Connected to the first series capacitor (C)1) And a second serial capacitor (C)2) Between the upper polar plates;
a second switch (S)2) Connected to the first series capacitor (C)1) And a high reference voltage (V)T) To (c) to (d);
third switch (S)3) Connected to the first series capacitor (C)1) Upper plate of (d) and a low reference voltage (V)B) To (c) to (d);
fourth switch (S)4) Is connected to the second serial capacitance (C)2) The other end of the upper polar plate is used as the output end of the serial capacitance type digital-to-analog conversion unit (301);
fifth switch (S)5) Is connected to the second serial capacitor (C)2) Upper plate of (d) and a low reference voltage (V)B) To (c) to (d);
first series capacitance (C)1) And a second series capacitance (C)2) Is connected with a low reference voltage (V)B)；
The capacitance weighted digital-to-analog conversion unit (302) comprises a high-stage capacitor array and a low-stage capacitor array;
the high-section capacitor array comprises M +1 quantization capacitors, the upper polar plates of the M +1 quantization capacitors are all connected with the high-order output end of the capacitor weight type digital-to-analog conversion unit (302), and the lower polar plates are respectively connected with a low reference voltage (V) through switchesB) High reference voltage (V)T) Or input voltage (V)IN)；
The low-stage capacitor array comprises L quantized capacitors, and the upper plate of the lowest quantized capacitor of the low-stage capacitor array is switched by the upper plate of the lowest quantized capacitor (S)T) Then the upper pole plate of the other quantized capacitors of the low-stage capacitor array is connected with the low-order output end of the capacitor weight type digital-to-analog conversion unit (302), and the lower pole plate of the capacitor weight type digital-to-analog conversion unit is connected with a low reference voltage (V)B) (ii) a The lower electrode plates of the other quantized capacitors of the low-section capacitor array are respectively connected with a low reference voltage (V) through switchesB) Or a high reference voltage (V)T)；
The reset switch comprises a high-stage reset switch (S)H) And a low-stage reset switch (S)L) Said high-section reset switch (S)H) Connected to the high-order output terminal of the capacitance weighted digital-to-analog conversion unit (302) and a high reference voltage (V)T) In the low stage reset switch (S)L) A low-order output end connected with the capacitance weighted digital-analog conversion unit (302) and a low reference voltage (V)B) To (c) to (d);
the composite structure successive approximation analog-to-digital converter carries out P + Q times of quantization, wherein P is M + L, Q is a positive integer, and the quantization process comprises the following steps:
a. the fourth switch is turned off (S)4) The digital-to-analog conversion module only comprises the capacitance weighted digital-to-analog conversion unit (302), and the capacitance weighted digital-to-analog conversion unit (302) is quantized to obtain a high P bit of an output code of the successive approximation analog-to-digital converter with the composite structure;
b. closing the fourth switch (S)4) The digital-analog conversion module comprises a capacitance weighted digital-analog conversion unit (302) and a serial capacitance digital-analog conversion unit (301), and the digital-analog conversion module is sequentially subjected to low-Q quantization to obtain a low-Q bit of an output code of the successive approximation analog-digital converter with the composite structure, wherein j is a positive integer and P +1 is more than or equal to j and less than or equal to P + Q:
b1, opening the first switch (S)1) And a third switch (S)3) And a fourth switch (S)4) Closing the second switch (S)2) And a fifth switch (S)5) A first series capacitance (C)1) Is precharged to CU×(VT-VB) Second serial capacitance (C)2) Initializing the charge of (a) to 0;
b2, opening the second switch (S)2) And a third switch (S)3) And a fourth switch (S)4) And a fifth switch (S)5) Closing the first switch (S)1) A first series capacitance (C)1) And a second series capacitance (C)2) Is equally distributed to the first series capacitance (C)1) And a second series capacitance (C)2) The above step (1);
b3, connecting the lower plates of all the quantization capacitors in the capacitance weighted digital-to-analog conversion unit (302) with a low reference voltage (V)B) Closing the high-stage reset switch (S)H) And a low-stage reset switch (S)L) Connecting the upper plates of all the quantized capacitors of the low-stage capacitor array in the capacitance weighted digital-to-analog conversion unit (302) with a low reference voltage (V)B) Connecting the upper plates of all the quantized capacitors of the high-section capacitor array with a high reference voltage (V)T)；
b4, if j is P +1, performing step b6, and if j > P +1, performing step b 5;
b5, starting from the j-1 th bit of the output code of the composite structure successive approximation analog-digital converter to the P +1 th bit, sequentially judging whether the first serial capacitance (C) is the first serial capacitance according to the value of the s-th bit of the output code of the composite structure successive approximation analog-digital converter1) Charging or discharging is carried out, wherein s is a positive integer, P +1 is not less than s not more than j-1, and the specific judgment method is as follows:
b51, when the S-th bit of the output code of the successive approximation analog-to-digital converter of the composite structure is 0, the second switch is turned off (S)2) Closing the third switch (S)3) A first series capacitance (C)1) The charge of (2) is discharged to 0; when the S-th bit of the output code of the successive approximation analog-to-digital converter with the composite structure is 1, the third switch is turned off (S)3) Closing the second switch (S)2) A first series capacitance (C)1) Charge of to CU×(VT-VB)；
b52, repeating the step b 2;
b6, turning off the high-stage reset switch in sequence (S)H) The lowest position quantization capacitor upper plate switch (S)T) And a low-stage reset switch (S)L)；
b7, opening the first switch (S)1) And a fifth switch (S)5) Closing the fourth switch (S)4) A second serial capacitor (C)2) Accessing the capacitance weight type digital-to-analog conversion unit (302) to obtain an output signal of a high-order output end of the capacitance weight type digital-to-analog conversion unit (302);
b8, comparing the output signal of the high-order output end of the capacitance weighted digital-to-analog converter unit (302) with a reference signal to obtain the j-th-order output code of the successive approximation analog-to-digital converter with the composite structure.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101228697A (en) * 2005-06-16 2008-07-23 高通股份有限公司 Gain error correction in an analog-to-digital converter
CN101263656A (en) * 2005-08-12 2008-09-10 模拟装置公司 Analog-to-digital converter
US7978117B2 (en) * 2008-12-22 2011-07-12 Electronics And Telecommunications Research Institute Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same
US8049654B2 (en) * 2009-02-23 2011-11-01 Texas Instruments Incorporated Digital trimming of SAR ADCs
CN102324934A (en) * 2011-07-04 2012-01-18 电子科技大学 Resistance-string multiplexing circuit structure of SAR ADC (successive approximation analog to digital converter)
CN106992781A (en) * 2017-03-27 2017-07-28 电子科技大学 The prediction quantization method of binary system charge redistribution type gradually-appoximant analog-digital converter
CN107888191A (en) * 2017-12-11 2018-04-06 电子科技大学 Gradually-appoximant analog-digital converter and its quantization method based on adaptive prediction section

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101228697A (en) * 2005-06-16 2008-07-23 高通股份有限公司 Gain error correction in an analog-to-digital converter
CN101263656A (en) * 2005-08-12 2008-09-10 模拟装置公司 Analog-to-digital converter
US7978117B2 (en) * 2008-12-22 2011-07-12 Electronics And Telecommunications Research Institute Multi-stage dual successive approximation register analog-to-digital convertor and method of performing analog-to-digital conversion using the same
US8049654B2 (en) * 2009-02-23 2011-11-01 Texas Instruments Incorporated Digital trimming of SAR ADCs
CN102324934A (en) * 2011-07-04 2012-01-18 电子科技大学 Resistance-string multiplexing circuit structure of SAR ADC (successive approximation analog to digital converter)
CN106992781A (en) * 2017-03-27 2017-07-28 电子科技大学 The prediction quantization method of binary system charge redistribution type gradually-appoximant analog-digital converter
CN107888191A (en) * 2017-12-11 2018-04-06 电子科技大学 Gradually-appoximant analog-digital converter and its quantization method based on adaptive prediction section

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
A 10-bit 100MS/s subrange SAR ADC with time-domain quantization;Ling Du 等;《2014 IEEE International Symposium on Circuits and Systems》;20140605;355-359 *
一种基于电压窗口技术的超低功耗SAR ADC;汪正锋 等;《电子学报》;20160115;213-215 *
一种采用电阻串复用结构的12位SAR ADC;关允超 等;《微电子学》;20120620;311-314 *

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