CN106533443B - A kind of high speed dynamic comparer offset voltage calibration circuit - Google Patents

A kind of high speed dynamic comparer offset voltage calibration circuit Download PDF

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CN106533443B
CN106533443B CN201611024728.3A CN201611024728A CN106533443B CN 106533443 B CN106533443 B CN 106533443B CN 201611024728 A CN201611024728 A CN 201611024728A CN 106533443 B CN106533443 B CN 106533443B
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offset voltage
output end
calibration circuit
input
register
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CN106533443A (en
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唐鹤
陈正
何生生
彭传伟
车来晟
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1014—Calibration at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error
    • H03M1/1023—Offset correction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
    • H03M1/1245—Details of sampling arrangements or methods
    • H03M1/125—Asynchronous, i.e. free-running operation within each conversion cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
    • H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
    • H03M1/462—Details of the control circuitry, e.g. of the successive approximation register

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

The invention belongs to Analogous Integrated Electronic Circuits technical fields, and in particular to a kind of high speed dynamic comparer offset voltage calibration circuit.The circuit includes: pulse-modulator, digital analog converter, comparator, register logic unit and offset voltage calibration circuit, circuit is sampled using upper step, comparator input terminal connects digital analog converter output end or common mode electrical level, the input terminal of the output end connection digital analog converter of offset voltage calibration circuit.Comparator imbalance voltage of the invention is compensated by calibration circuit and digital analog converter.The present invention is digital calibration, and hardware requirement is low, high reliablity, low in energy consumption, calibration is accurate.

Description

A kind of high speed dynamic comparer offset voltage calibration circuit
Technical field
The invention belongs to Analogous Integrated Electronic Circuits technical fields, and in particular to one kind is converted for high speed successive approximation modulus The dynamic comparer offset voltage calibration circuit of device (hereinafter referred to as SAR ADC).
Background technique
ADC is a kind of circuit that analog circuit signal is converted into Digital Circuit Signal, is widely used in communication, signal In all kinds of electronic systems such as processing, storage, and play irreplaceable role.Currently, electronic information technology development is swift and violent, market Especially Communications Market is very big to high speed, middle precision, low-voltage, the ADC demand of low-power consumption.Compared to the ADC of other structures, SAR ADC structure is simple, area is small.SAR ADC analogue unit is less simultaneously, with the continuous contracting of semiconductor fabrication process size Small, SAR ADC becomes the emphasis and hot spot studied both at home and abroad.
SAR ADC nuclear structure mainly includes comparator, digital analog converter (hereinafter referred to as DAC) and logic unit.Wherein Comparator is part the most key in SAR ADC, it directly determines the conversion accuracy and conversion speed of SAR ADC.Compare Main problem in device design includes comparing speed, resolution ratio, offset voltage；Compare speed and resolution ratio is largely determined by ratio Compared with the structure snd size of device, offset voltage is mainly caused by the threshold voltage mismatch and W/L mismatch as input crystal to pipe, and normal The offset voltage of dynamic comparer in high speed SAR ADC is very big, it directly affects the linearity and dynamic model of SAR ADC It encloses.Therefore, it to guarantee dynamic range and precision, needs to calibrate the offset voltage of comparator.
In industry, current SAR ADC product is mainly the middle low speed ADC, this SAR that sample rate is lower than 10Msps ADC mostly uses static comparison device, and comparator imbalance calibration voltage technology is based on multistage AC coupled technology；It is answered in high-speed ADC In, dynamic comparer carries out offset voltage calibration by subtracting output average value, and the shortcomings that this collimation technique is to subtract The small dynamic range of SAR ADC；In academic research, pass through the differential pair to a pair of of the biasing in parallel to pipe of comparator input difference Pipe, to calibrate offset voltage, the input of differential pair generallys use capacitor storage charge-, however the shortcomings that this collimation technique It is analog quantity in the calibration information of storage, therefore anti-interference ability is weak, and stability is poor, is difficult to apply to practical application.
Summary of the invention
The invention proposes a kind of imbalance electricity for being suitable for high speed, medium accuracy (8-10) SAR ADC dynamic comparer Pressure calibration circuit, not only can accurately compensate the offset voltage of dynamic comparer, but also calibration range also greatly increases.
The technical scheme is that a kind of high speed dynamic comparer offset voltage calibration circuit, which is characterized in that including Comparator, pulse-modulator, digital analog converter, register logic unit, sampling hold circuit, asynchronous clock and register and mistake Adjust voltage calibration circuit；Wherein:
The input terminal of the comparator and the output end of digital analog converter connect, the input clock and asynchronous clock of comparator And the output clock connection of register；
The input of the pulse-modulator terminates external input clock, for adjusting calibration mode and data transfer module Clock；
The input end of clock of the digital analog converter connects the output end of pulse-modulator, the data input pin of digital analog converter The output end of offset voltage calibration circuit and the output end of sampling hold circuit are connect, digital analog converter is used to store up in the calibration mode Deposit the offset voltage of comparator；Data conversion is used under data transfer module；
The input end of clock of the register logic unit connects the output end and asynchronous clock and register of pulse-modulator Output end, register logic unit is used to store the imbalance code of the offset voltage of comparator in the calibration mode；Turn in data For data output sequence under mold changing formula；
The input end of clock of the offset voltage calibration circuit connects the output end of pulse-modulator, offset voltage calibration circuit Data input pin connect the output end of register logic unit, offset voltage calibration circuit is for calculating offset voltage and controlling number The switch of mode converter.
Further, the offset voltage calibration circuit includes subtracter, register and switching logic；Wherein:
The input signal of subtracter includes subtrahend and minuend, the input terminal of subtrahend and the output end of register logic unit Connection；The output data level that the voltage of minuend is input voltage when being zero；
The input terminal of register and the output end of subtracter connect, and control register by external control signal；
Switching logic input terminal is connect with register output end, and switching logic output end and digital analog converter connect It connects
The invention has the following beneficial effects: structure is simple, by increasing part logic circuit and being switched using existing DAC circuit Calibration can be realized, therefore hardware requirement is low, high reliablity, power consumption is extremely low, calibration is accurate, and does not need to refresh in real time.
Detailed description of the invention
Fig. 1 is the SAR ADC structural schematic diagram using offset voltage calibration circuit of the present invention；
Fig. 2 is that signal and pulse-modulated signal timing diagram are controlled in the present invention；
Fig. 3 is the schematic diagram of SAR ADC offset voltage calibration circuit；
Fig. 4 is that conventional dynamic comparator imbalance voltage calibration circuit and offset voltage calibration circuit of the present invention comparison are illustrated Figure；
Fig. 5 is offset voltage calibration circuit of the present invention switching sequence explanatory diagram in the calibration mode；Wherein, (a) is sampling Stage (b) is reseting stage, is (c) processing terminate stage；
Fig. 6 is offset voltage calibration circuit of the present invention in normal work (data conversion) mode lower switch sequence explanatory diagram； Wherein, (a) is sample phase, (b) is reseting stage, is (c) processing terminate stage.
Specific embodiment
With reference to the accompanying drawing, the present invention is described in detail:
Fig. 1 is the SAR ADC structural schematic diagram using offset voltage calibration circuit of the present invention, comprising with lower module: one Pulse-modulator, a sampling hold circuit, a digital analog converter, a comparator, a register logic unit, one Asynchronous clock generation circuit and register, an offset voltage calibration circuit；Wherein pulse-modulator is used as calibration control circuit, Function includes: clock division, clock duty cycle adjustment and the switching of ADC operating mode.
There are two types of modes by SAR ADC of the invention: calibration mode and normal mode of operation are controlled by calibration signal, As shown in Figure 2.When calibration signal is in low level, pulse-modulator generates periodic logic unit and Cai Bao switching signal Clock as register logic unit and sampling hold circuit；When calibration signal is in high level, pulse-modulator generates week Clock of the phase property calibration switch signal as mistuning calibration function potential circuit.
Fig. 3 is the offset voltage calibration circuit diagram in the present invention, and comprising with lower module: a subtracter, one is posted Storage and a switching logic.
Fig. 4 is that conventional dynamic comparator imbalance voltage calibration circuit and offset voltage calibration circuit of the present invention comparison are illustrated Figure.Fig. 4 (a) and (b) are conventional dynamic comparator imbalance voltage calibration circuit working principle diagram；Fig. 4 (c), (d), (e), (f), (g) and (h) is offset voltage calibration circuit fundamental diagram of the present invention.Traditional comparator imbalance voltage be by comparator come Calibration, and comparator imbalance voltage of the invention is compensated by digital analog converter.
The working principle of the invention: offset voltage is converted into digital code by analog-to-digital conversion by SAR ADC, then using existing Some digital analog converters and offset voltage calibration circuit compensation offset voltage.The present invention can reduce the offset voltage of comparator To a least significant bit (LSB) voltage (LSB).
For easy analysis, it is assumed that comparator imbalance voltage value is that a LSB (is greater than one for comparator imbalance voltage The case where LSB, analysis method are similar).Fig. 5 and Fig. 6 is respectively offset voltage calibration circuit in calibration mode and works normally mould Switching sequence explanatory diagram under formula, all capacitors are all specific capacitances in figure, and are labelled with highest order, interposition, lowest order； The lowest order of C and D capacitor array is (DAC of this structure is referred to as pseudo-differential DAC) that cannot be changed.
When offset voltage calibration circuit in the calibration mode when (Fig. 5), subtracter in offset voltage calibration circuit and post Storage is respectively at work and reset state.The change-over period of SAR ADC includes sampling and two stages of coded treatment, and this hair The bright change-over period includes sampling, reset and coded treatment three phases.In sample phase, sampling switch (401) and output switch (403) it disconnects, the lower step of comparator Differential Input short switch (402) closure, CDAC connects common-mode voltage；Resetting rank Section, sampling switch (401), comparator Differential Input short switch (402) and output switch (403) all disconnect, the junior of CDAC Plate connects common-mode voltage；In the coded treatment stage: sampling switch (401), comparator Differential Input short switch (402) and output (403) are switched to disconnect, comparator carries out repeating comparison at this stage, until exporting last a data, then register logical All data are put into offset voltage calibration circuit and calibrated by unit.
In calibration mode sample phase, CDAC charging charge are as follows:
Q=C (Vin-Vcm)=C (Vdac+Voffset-Vcm) (1)
Wherein VinFor comparator input voltage (Vin=Vdac+Voffset), VdacFor DAC output voltage, VcmFor common-mode voltage, VoffsetFor offset voltage, C is total capacitance value.Since the voltage of sample phase input voltage and lower step is all identical value, because This:
Q=CVoffset (2)
Such as Fig. 5 (c): under the condition analysis, the digital output code of SAR ADC is 1001, and reference value 1000 passes through mistake Adjusting voltage calibration circuit to obtain mistuning digital code is 0001.
When offset voltage calibration circuit in the normal mode of operation when (Fig. 6), subtracter in offset voltage calibration circuit It stops working, and register is in preservation state.In sample phase, sampling switch (401) and output switch (403) closure, than It is disconnected compared with device Differential Input short switch (402), junior's switching plate of CDAC connects offset voltage calibration circuit switch signal；? Reseting stage, sampling switch (401) and comparator Differential Input short switch (402) disconnect, and output switch (403) is closed CDAC Lower step connect common-mode voltage；In the coded treatment stage, sampling switch (401) and comparator Differential Input short switch (402) it disconnects, output switch (403) closure, comparator carries out repeating comparison at this stage, until exporting last a data.
In normal mode of operation sample phase, CDAC charging charge are as follows:
Q=C (Vin-Vcm-Vcalibration)=C (Vdac+Voffset-Vcm-Vcalibration) (3)
Wherein VcalibrationFor calibration voltage value, C is total capacitance value.Under normal mode of operation, difference common mode VcmVoltage is 0, therefore
Q=C (Vin+Voffset-Vcalibration) (4)
For no offset voltage comparator, should meet:
Qideal=CVin (5)
Offset voltage by above formula, after being calibrated are as follows:
Offset voltage V in above formulaoffsetIt is a fixed value, V under identical operating conditioncalibrationResolution ratio be about 1 LSB, for any one offset voltage value, | Voffset-Vcalibration| minimum value be no more than 0.5 LSB.Therefore this hair Bright comparator imbalance error can reach 0.5 LSB.As a result such as Fig. 6 (c): the input for being 0 for a Differential Input after calibration Voltage, the transformation result of the ADC are 1000.
In conclusion the invention proposes a kind of comparator imbalance voltage calibration circuits applied to high speed SAR ADC.

Claims (2)

1. a kind of high speed dynamic comparer offset voltage calibration circuit, which is characterized in that including comparator, pulse-modulator, number Mode converter, register logic unit, sampling hold circuit, asynchronous clock and register and offset voltage calibration circuit；Wherein:
The output end of the input terminal of the comparator and digital analog converter connects, and the input clock of comparator and asynchronous clock and posts The output clock of storage connects；
The input of the pulse-modulator terminates external input clock, for adjust calibration mode and data transfer module when Clock；
The input end of clock of the digital analog converter connects the output end of pulse-modulator, and the data input pin of digital analog converter connects mistake The output end of voltage calibration circuit and the output end of sampling hold circuit are adjusted, digital analog converter is used to store ratio in the calibration mode Compared with the offset voltage of device；Data conversion is used under data transfer module；
The input end of clock of the register logic unit connect pulse-modulator output end and asynchronous clock and register it is defeated Outlet, register logic unit are used to store the imbalance code of the offset voltage of comparator in the calibration mode；In data conversion mould For data output sequence under formula；
The input end of clock of the offset voltage calibration circuit connects the output end of pulse-modulator, the number of offset voltage calibration circuit According to the output end of input termination register logic unit, offset voltage calibration circuit turns for calculating offset voltage and controlling digital-to-analogue The switch of parallel operation.
2. a kind of high speed dynamic comparer offset voltage calibration circuit according to claim 1, which is characterized in that the mistake Adjusting voltage calibration circuit includes subtracter, register and switching logic；Wherein:
The input signal of subtracter includes subtrahend and minuend, and the input terminal of subtrahend and the output end of register logic unit connect It connects；The output data level that the voltage of minuend is input voltage when being zero；
The input terminal of register and the output end of subtracter connect, and control register by external control signal；
Switching logic input terminal is connect with register output end, and switching logic output end is connect with digital analog converter.
CN201611024728.3A 2016-11-16 2016-11-16 A kind of high speed dynamic comparer offset voltage calibration circuit Active CN106533443B (en)

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WO2019113772A1 (en) * 2017-12-12 2019-06-20 深圳市汇顶科技股份有限公司 Method for analog-digital conversion and analog-digital converter
CN108519115B (en) * 2018-03-14 2020-09-15 无锡思泰迪半导体有限公司 Offset voltage correction method applied to Hall device
CN109120268B (en) * 2018-08-28 2021-09-24 电子科技大学 Dynamic comparator offset voltage calibration method
CN109586696B (en) * 2018-11-30 2020-08-04 西安电子科技大学 Offset voltage correction circuit for dynamic comparator
CN110149117A (en) * 2019-07-05 2019-08-20 成都博思微科技有限公司 A kind of self calibration comparator imbalance voltage cancellation circuit
CN110286405B (en) * 2019-07-10 2020-09-15 中国科学院近代物理研究所 Application of calibration device of deep space detector system
CN111262561B (en) * 2020-02-05 2023-03-31 电子科技大学 Metastable state detection circuit of comparator
CN113607329B (en) * 2021-07-13 2022-10-18 复旦大学 Pressure sensor signal temperature compensation method and pressure sensor
CN115913229B (en) * 2022-12-15 2023-10-03 江苏润石科技有限公司 Dynamic configuration method and circuit of comparator of SAR ADC, SAR ADC and chip

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