CN106527098A - Low-power-consumption high-precision array-type time digital conversion circuit based on multiple VCOs (voltage controlled oscillators) - Google Patents
Low-power-consumption high-precision array-type time digital conversion circuit based on multiple VCOs (voltage controlled oscillators) Download PDFInfo
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- CN106527098A CN106527098A CN201610901004.6A CN201610901004A CN106527098A CN 106527098 A CN106527098 A CN 106527098A CN 201610901004 A CN201610901004 A CN 201610901004A CN 106527098 A CN106527098 A CN 106527098A
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- G—PHYSICS
- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention discloses a low-power-consumption high-precision array-type time digital conversion circuit based on multiple VCOs (voltage controlled oscillators). The low-power-consumption high-precision array-type time digital conversion circuit comprises an ultrahigh-phase TDC (time-to-digital converter) circuit, a high-phase TDC circuit, a middle-phase TDC circuit, a low-phase TDC circuit and a DFF latch chain, the ultrahigh-phase TDC circuit, the high-phase TDC circuit and the DFF latch chain are in a pixel exclusive circuit and are arranged in a pixel, and the middle-phase TDC circuit and the low-phase TDC circuit are in a global shared circuit and arranged outside the pixel; measuring of time interval is completed through orderly cooperation of the ultrahigh-phase TDC circuit, the high-phase TDC circuit, the middle-phase TDC circuit and the low-phase TDC circuit, and finally the time interval is converted into a numerical value for representation. The low-power-consumption high-precision wide-range four-phase array-type time digital conversion circuit can be used for an array-type detector timing system and can obviously improve resolution of the system and lower power consumption of the system.
Description
Technical field
The present invention relates to a kind of based on the low of multiple VCO (Voltage Controlled Oscillator, voltage-controlled ring shake)
Power consumption high accuracy array type time-to-digital conversion circuit, is a kind of low power consumption high-precision that can be applicable to infrared sensing reading circuit
Four-part form array type time-to-digital conversion circuit, the circuit can effectively improve system on the premise of elemental area is not affected
Resolution ratio simultaneously reduces system power dissipation.
Background technology
According to TOF (Time of Flight) time measurement principle, infrared ROIC (Readout Integrated
Circuit) the different space length of different pixels single photon transmitting-receiving interval time correspondence in reading circuit, by pel array
Relative distance between each pixel can present the profile of object under test, and the TDC circuits of high accuracy, wide scope are then to visit
Examining system can obtain the guarantee of more precise information in farther distance, but under the application conditions of pel array, area and
The restriction of power consumption significantly increases TDC (Time-to-Digital Converter, time figure conversion) quantization performance and realizes
Technical difficulty, therefore array type TDC is more difficult to compared to general single pixel TDC in design.
In order to be applied to the application of big array structure, overwhelming majority TDC is using shared or local shared structure, the knot at present
TDC under structure is not for single pixel detection service, but for multiple or even global pixel service.But due to general multistage
There is thinner error and extract and quantizing process in formula structure, it is necessary to there is the response time, it is impossible to while another time quantum is detected,
Therefore multisection type TDC is difficult to apply in big array, so being concentrated mainly on two sections suitable for the array type TDC of big array at present
In formula structure.It is applied to TDC framework Gonna breakthrough ranges and the restriction of precision of array detection timekeeping system, it is necessary to pursue multisection type
TDC structures.
The content of the invention
Goal of the invention：In order to alleviate the problem that range in prior art, precision and power consumption are mutually restricted to a certain extent,
The invention provides a kind of new low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO, in typical case
Two-part array type TDC technical foundation on, by introducing asynchronous subtraction count device structure and multiple respectively in high section and low section
Ring shakes the mode of structure so that under the premise of system pixel area and range is not affected, realize raising and the work(of systemic resolution
The reduction of consumption.
Technical scheme：For achieving the above object, the technical solution used in the present invention is：
A kind of low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO, it is electric including freeboard section TDC
Road, high section TDC circuit, stage casing TDC circuits, low section of TDC circuit and DFF latch chain, wherein freeboard section TDC circuits, high section TDC electricity
Road and DFF latch chain and exclusively enjoy circuit for pixel and be placed in pixel, and stage casing TDC circuits and low section of TDC circuit are globally shared electricity
Road and it is placed in outside pixel；The measurement of time interval is by freeboard section TDC circuits, high section TDC circuit, stage casing TDC circuits and low section of TDC
The cooperation of four partial order of circuit is completed, final to realize that time interval is converted to digital value represents；
The freeboard section TDC circuits configure double mode LFSR counter (Linear Feedback Shifting
Register, linear feedback shift register), high section TDC circuit configures double mode asynchronous subtraction count device, and stage casing TDC is electric
The voltage-controlled ring in road configuration stage casing shakes and double rotary single circuit, low section of TDC circuits configuration Dual-DLL and VCO loop, the VCO loops by
X forms with the out of phase low section of voltage-controlled ring vibration level connection of frequency, and each low section of voltage-controlled ring shakes by Y identical low section of time delay
Unit cascaded to form, each low section of voltage-controlled ring cascades a low section of delay path before shaking, and i-th low section of delay path is by XiIt is individual complete
Exactly the same delay unit cascade is formed, X >=2, Y >=2；LFSR counter forms mixing after being serially connected in asynchronous subtraction count device
Counter, the shake high frequency clock signal H_CK of generation of the voltage-controlled ring in stage casing drive asynchronous subtraction count device, the asynchronous subtraction count devices of Jing
The high frequency clock signal H_LFSR of frequency dividing synchronously drives LFSR counter；
The quantized result of freeboard section TDC circuits is latched in LFSR counter by the pattern for switching LFSR counter,
The quantized result of high section TDC circuit is latched in asynchronous subtraction count device by the pattern for switching asynchronous subtraction count device, in
The quantized result of section TDC circuits and low section of TDC circuit latches chain by DFF and is latched；The LFSR counter, asynchronous subtract
Method counter and DFF latch chain and are mainly made up of DFF, and reading, freeboard section TDC circuits, high section TDC circuit, stage casing TDC are electric
During the quantized result of road and low section of TDC circuit, latch data by corresponding DFF (d type flip flop) series connection after in binary form
The Serial output by turn from a high position to low level.
Time-to-digital conversion circuit proposed by the present invention, it is electric by freeboard section TDC circuits, high section TDC circuit, stage casing TDC
Road and low section of TDC circuit complete to quantify to time interval respectively, can be on the premise of system range is not affected so that array TDC
Precision break through digital gate circuit minimum delay；Meanwhile, asynchronous subtraction count device is added before the lowest order of LFSR counter,
The shake high frequency clock signal H_CK of generation of stage casing voltage-controlled ring can be divided and driven LFSR counter, to reduce LFSR counter
Synchronised clock frequency；As LFSR counter and asynchronous subtraction count device are placed in pixel, therefore freeboard section TDC circuits and height
The design of section TDC circuits can effectively reduce system power dissipation on the premise of system range is not affected.
Specifically, in the low section of TDC circuit, Dual-DLL is that (Delay Locked Loop postpone lock phase to two-stage DLL
Ring) structure, be divided into main DLL and time DLL, acted on by the close loop negative feedback of Dual-DLL and offer is shaken with work to low section of voltage-controlled ring
Skill, supply voltage, the high stability voltage-controlled voltage of temperature change；
It is provided with main DLL by the unit cascaded main voltage controlled delay line of N number of master delay, the input signal of main DLL is
External reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrf, will
External reference clock signal REF_CLK and N level master delay unit carries out phase state phase demodulation, voltage-controlled voltage VctrfAutomatically adjust
Main voltage controlled delay line, makes the phase state of external reference clock signal REF_CLK and N level master delay unit identical；
It is provided with secondary DLL by the secondary voltage controlled delay line of M delay cell cascade, the input signal of secondary DLL is
External reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrs, root
Go out n-th grade of master delay unit according to the delay selection of required secondary voltage controlled delay line, by n-th grade of master delay unit and M levels time
Delay cell carries out phase state phase demodulation, voltage-controlled voltage VctrsTime voltage controlled delay line is automatically adjusted, n-th grade of master delay unit is made
Phase state is identical with the phase state of M levels time delay cell.
Specifically, the voltage-controlled voltage VctrfAll low section of time delay list of all low sections voltage-controlled ring centers of percussion is supplied to simultaneously
Unit, voltage-controlled voltage VctrsWhile all delay units in being supplied to all low section of delay paths；Signal EN is started counting up by X
Bar time delay different low section of delay path controls X low section of voltage-controlled ring respectively and shakes beginning starting of oscillation, and adjacent low section voltage-controlled
Ring shake due to starting of oscillation first phase is different thus produce delay time error, the delay time error passes through voltage-controlled voltage VctrsPrecise control, passes through
Adjust voltage-controlled voltage VctrsMake adjacent low section of voltage-controlled ring certain sequential be met between shaking, finally cause X low section of voltage-controlled ring to shake
Between it is seamless linking coordinate.
In low section of TDC circuit, the split-phase number that single low section of voltage-controlled ring shakes expands to 4Y by 2Y, whole low section of TDC electricity
The split-phase number on road reaches 4YX, solve low section of TDC circuit of tradition cannot take into account frequency of oscillation that single low section of voltage-controlled ring shake and
Contradiction between split-phase number, is shaken by multiple low section of voltage-controlled rings and is cooperated, and systemic resolution can be made to break through digital gate circuit
Minimum time delay, significantly improves systemic resolution.The low section of TDC circuit is direct when count stop signal STOP rising edges arrive
Latch the quantized result of freeboard section TDC circuits, high section TDC circuit, stage casing TDC circuits and low section of TDC circuit, it is not necessary to extra
Response time, it is possible to achieve array application.
Specifically, the stage casing TDC circuits are designed based on time difference quantization principles, and adopt DLL-OSC frameworks, that is, lead to
The close loop negative feedback of the main DLL crossed in Dual-DLL is acted on shakes offer with technique, supply voltage, temperature change to the voltage-controlled ring in stage casing
High stability voltage-controlled voltage Vctrf；The voltage-controlled ring in the stage casing shakes including the difference by N/2 differential delay cells cascade
Divide delay line (noise of power supply and substrate can effectively be suppressed using differential delay line) and Logic control module：When starting counting up
When signal EN rising edges arrive, differential delay line is opened by Logic control module；Arrive when signal EN trailing edges are started counting up
When, differential delay line is turned off by Logic control module；The output end of each grade of differential delay cells connects double turns of single electricity
The both-end difference output of differential delay cells is converted to Single-end output by double rotary single circuit, and output signal is carried out by road
Shaping.TDC circuits in stage casing proposed by the present invention, when the multi-phase clock shaken using the voltage-controlled ring in stage casing is to one of high section TDC circuit
The clock cycle is uniformly differentiated, and the N/2 node state that the voltage-controlled ring in stage casing shakes can produce N group states per circulation primary, work as counting
When stop signal STOP rising edge arrives, the state that chain latches current N/2 node is latched by DFF, you can complete stage casing TDC
The quantization of circuit.
Specifically, the clock signal input terminal and data signal input of each DFF in asynchronous subtraction count device
One MUX of front each setting is believed as Logic control module, the control for starting counting up signal EN as MUX
Number：When start counting up signal EN for high level when, the voltage-controlled ring in stage casing to shake and provide high frequency clock signal H_ for asynchronous subtraction count device
CK, asynchronous subtraction count device are operated in count mode；When start counting up signal EN for low level when, external low-frequency clock signal is
Asynchronous subtraction count device provides low-frequency clock signal, and asynchronous subtraction count device is operated in mode of serial transmission；Counted by being multiplexed
And transmission structure, circuit area can be reduced, system power dissipation is reduced.When count stop signal STOP arrives, LFSR counter
Stop input high frequency clock signal simultaneously with asynchronous subtraction count device, and current quantisation result is latched, signal to be started counting up
By the quantized result for latching successively Serial output when EN trailing edges arrive.
Beneficial effect：The low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO that the present invention is provided,
Carry out structure on the basis of classical two-part TDC to improve and optimization design：Add before the lowest order of LFSR counter different
Step subtraction count device is divided to the high frequency clock signal being input into, it is ensured that reduce system work(on the premise of system range
Consumption；TDC circuit in stage casing adopts DLL-OSC frameworks, and introduces the close loop negative feedback circuit of DLL, improves the property of stage casing TDC circuits
Can level；Low section of TDC circuit introduces multiple VCO structures, controls and using its relative phase, is capable of achieving split-second precision and differentiates.
Four sections of TDC circuits of the present invention can be latched by count stop signal STOP, do not need to add extra latency or sound
The work of circuit is completed between seasonable, thus the demand of array application can be met.
Description of the drawings
Fig. 1 is the schematic diagram of the low power consumption high-precision array type time-to-digital conversion circuit of double VCO；
Fig. 2 is the circuit diagram of the mixing counter for constituting freeboard section TDC circuits and high section TDC circuit；
Circuit diagrams of the Fig. 3 for stage casing TDC circuits；
Circuit diagrams of the Fig. 4 for the differential delay cells in the TDC circuits of stage casing；
Circuit diagrams of the Fig. 5 for the double rotary single circuit in the TDC circuits of stage casing；
Sequential charts of the Fig. 6 for stage casing TDC circuits；
Fig. 7 is the circuit diagram of the Dual-DLL in low section of TDC circuit；
Fig. 8 is the circuit diagram that type TDC circuit is distinguished in high-precision phase position subdivision；
Fig. 9 is the sequential chart of low section of TDC circuit.
Specific embodiment
Below in conjunction with the accompanying drawings the present invention is further described.
A kind of low power consumption high-precision array type time-to-digital conversion circuit based on double VCO is illustrated in figure 1, between the time
Every measurement quantified by freeboard section TDC circuits, high section TDC circuit, stage casing TDC circuits and low section of four partial segments of TDC circuits
Into realizing clocking capability.The freeboard section TDC circuits and high section TDC circuit being placed in pixel be respectively adopted LFSR counter and
Asynchronous subtraction count device is designed, on the premise of the wide-range time detecting needed for realizing, by asynchronous subtraction count device
The synchronous high frequency clock signal of LFSR counter is divided, and then greatly reduces system power dissipation.
Valid period when signal EN is high level is being started counting up, external reference clock signal REF_CLK drives pressurized
Control voltage VctrfThe voltage-controlled ring in stage casing of control shakes work, produce just align and with technique, supply voltage, temperature change height
Stable embedded clock HCK, drives the integral multiple that high section TDC circuit completes the clock cycle to count, realizes the thick amount of time detecting
Change function；Meanwhile, the uniform clock of multiphase of stage casing TDC circuits enters row interpolation quantization to the time margin of high section TDC circuit, completes
The fraction of clock cycle is counted again.Low section of TDC circuit is that type TDC circuit is distinguished in high-precision phase position subdivision, is provided by Dual-DLL
Two different voltage-controlled voltage VctrfAnd Vctrs, due to signal EN being started counting up by two low section of delay paths start two
Low section of voltage-controlled ring shakes, and can produce two with the out of phase ring retard of frequency, be completed to stage casing TDC circuits by the double VCO structures
High frequency clock signal frequency multiplication, and then using frequency multiplied clock signal the time margin of stage casing TDC circuits is entered row interpolation quantization.
In Digital Logical Circuits, the square-like clock signal that a switching frequency is f is provided with, then the work(of the Digital Logical Circuits
Consuming P is：
Power consumption P of Digital Logical Circuits from gate circuit under on off state to load capacitance CLThe electric energy of discharge and recharge disappears
Consumption, therefore power consumption P and load capacitance CL, supply voltage VDDQuadratic sum switching frequency f be directly proportional, it is contemplated that gate circuit it is quiet
Only non-switch state, insertion switch activity factor α (0≤α≤1) are modified to power consumption.Broadly, Digital Logical Circuits can be with
Time-sharing work is under different switching frequency f, therefore α f can also be equivalent to the average frequency of switching of Digital Logical Circuits.
High section TDC circuit is mainly used in improving count upper-limit, and then expanded range；Simplify in view of structure and high frequency draws
With we expect using LFSR counter.As LFSR counter is driven using synchronised clock, so when switching frequency is raised
When, the power consumption of LFSR counter also linearly can increase therewith, cause the LFSR counter power consumption under high frequency very big；As LFSR is counted
Number device is built in pixel, therefore for reducing the power consumption of pel array, need to reduce driving clock frequency f of LFSR counterCLK。
On the premise of other performances are not interfered with, it is contemplated that asynchronous counter has a division function, therefore we are by high section TDC circuit
The mode that LFSR counter is combined with asynchronous counter is designed as, to reduce power consumption；Additionally, we are also examined as follows
Consider：(1) asynchronous counter belongs to asynchronous clock control circuit, and per many one, clock will postpone the time delay of a DFF, in order to
The certainty of measurement of system is not affected, the digit of asynchronous subtraction count device is unsuitable excessive；(2) between in order to realize counting and transmitting
Patten transformation, it is each before the clock signal input terminal and data signal input of each DFF in asynchronous counter to arrange one
Individual MUX is used as Logic control module；(3) due to the output end rising edge of asynchronous subtraction count device can be designed to
The even-multiple rising edge alignment of high frequency clock signal H_CK, is more convenient for counting, therefore asynchronous counter selects asynchronous subtraction count
Device；(4) in order to reach the purpose for simplifying area, asynchronous subtraction count device is built in pixel.Consider factor above, we
It is built-in mixing counter by high section TDC circuit design, as shown in Fig. 2 wherein asynchronous subtraction count device is 2bit, LFSR meters
Number device is 7bit.
Middle section TDC circuits use DLL-OSC frameworks, as shown in figure 3, shaking including the voltage-controlled ring in stage casing and double turns of single electricity
Road, the voltage-controlled ring in stage casing shake including the differential delay line by 4 differential delay cells cascades and Logic control module, middle section
TDC circuits provide clock frequency for high section TDC circuits, and its remainder error is carefully quantified by low section TDC circuits, is played and is held
On open under key effect.In order to realize that the voltage-controlled ring in stage casing shakes controllable and determines its original state, Logic control module is added to enter
Row control：When the arrival of signal EN rising edges is started counting up, differential delay line is opened by Logic control module so as to which first phase is true
It is fixed, additional circuit need not be added to eliminate initial phase errors, it is convenient to count；When the arrival of signal EN trailing edges is started counting up, pass through
Logic control module turns off differential delay line, to reduce system power dissipation.But the introducing of Logic control module can make difference at different levels
There is serious mismatch in delay cell, reduce system linear degree；In order in ensureing section TDC circuit multi-phase clocks it is uniform
Property to realize effectively resolution, the time delay of Logic control module and first order differential delay cells should be readjusted, logic control is made
The time delay sum of molding block and first order differential delay cells is exactly equal to the time delay sum of other differential delay cells.Press in stage casing
The frequency that control ring shakes is produced with technique, electricity by the close loop negative feedback effect of main DLL by the main DLL controls in low section of TDC circuit
The high stability voltage-controlled voltage V of source voltage, temperature changectrf, the frequency that the stable voltage-controlled ring in stage casing shakes, reduce its receive technique,
The impact of supply voltage, temperature change.
In order to reduce phase noise and extend output voltage swing, the voltage-controlled ring in stage casing shakes and employs differential delay line, single difference
Divide delay unit as shown in Figure 4；The differential delay cells are input into (MN1 and MN2), one group of PMOS positive feedback pair by one group of NMOS
(MP2 and MP3), one group of PMOS Diode are to (MP1 and MP4) and controlled voltage VctrlThe MP5 compositions of control, wherein MP2
The vibration that positive feedback maintains the voltage-controlled ring in stage casing to shake is constituted with MP3.Control voltage VctrlThe bias voltage of the MP5 of control is propped up to change
Road electric current, when control voltage VctrlDuring increase, branch current becomes hour, and the mutual conductance of MP1 and MP4 diminishes but equivalent electric resistive is big, most
The output resistance and timeconstantτ increase of differential delay cells is caused eventually, i.e., so that the time delay of difference delay unit becomes big；Cause
This, by changing control voltage VctrlThe frequency that the voltage-controlled ring in stage casing shakes being made up of the differential delay cells can be controlled.In addition,
MP2 and MP3 are connected directly to supply voltage VDD, therefore output voltage swing is improve, carrier power is increased, and can also reduce making an uproar
Acoustical power, improves phase noise performance.
Key component of the double rotary single circuit as middle section TDC circuits, the both-end difference output of differential delay cells is turned
For Single-end output, its circuit structure is as shown in Figure 5；Double single modules that turn mainly have following effect or feature：(1) to differential delay list
The output of unit carries out shaping；(2) node state of Single-end output is easy to data to latch；(3) clock frequency f of Single-end outputCLKCan
To directly drive high section TDC circuits；(4) as middle section TDC circuits use DLL-OSC frameworks, therefore low section of TDC electricity
The master delay unit of the main DLL in road is also required to adopt differential delay cells, and phase discriminator be to main voltage controlled delay line first
Individual and last signal carries out phase state phase demodulation, now also requires that main voltage controlled delay line is Single-end output.When starting counting up
When signal EN is high level, backfeed loop conducting, the voltage-controlled ring in stage casing are shaken unlatching, and the voltage-controlled ring in stage casing shakes sequential such as Fig. 6 of each node
It is shown.
In order to provide two stable delay times to low section of TDC circuit, using Dual-DLL structures, as shown in Figure 7；
Dual-DLL is two-stage DLL structure, and the frequency for being divided into main DLL and time DLL, external reference clock signal REF_CLK is fREF.It is main
In DLL, by voltage-controlled voltage VctrfMain voltage controlled delay line is automatically adjusted, external reference clock signal REF_CLK and N level master is made
The phase state of delay cell is identical, and the time delay for obtaining every grade of master delay unit is t1=1/ (N × fREF)；In secondary DLL, pass through
Voltage-controlled voltage VctrsTime voltage controlled delay line is automatically adjusted, phase state and the M levels time delay cell of n-th grade of master delay unit is made
Phase state it is identical, the time delay for obtaining per grade of time delay cell is t2=n/ (M × N × fREF).By the closed loop of Dual-DLL
Negative feedback give low section of voltage-controlled ring shake provide with technique, supply voltage, temperature change high stability time delay；
As shown in figure 8, low section of TDC circuit includes that low section of voltage-controlled ring of two structure identicals shakes and two low section of time delay roads
Footpath, each low section of voltage-controlled ring to shake and receive same voltage-controlled voltage V including two-stagectrfLow section of delay unit of control；Prolonged by two low section
When unit cascaded low section of voltage-controlled ring to shake be that low section of voltage-controlled ring of simple structure shakes, its ring vibration frequency is relative to more than three
It is highest that low section of voltage-controlled ring of low section of delay unit cascade shakes.Start counting up signal EN each not by two time delays
Low section of delay path of identical controls two low section of voltage-controlled rings respectively and shakes beginning starting of oscillation, and two low section of voltage-controlled rings shake due at the beginning of starting of oscillation
Mutually different thus produce delay time error, the delay time error passes through voltage-controlled voltage VctrsPrecise control, by adjusting voltage-controlled voltage Vctrs
Make two low section of voltage-controlled rings meet certain sequential between shaking, finally cause two low section of voltage-controlled rings between shaking seamless linking match somebody with somebody
Close.The split-phase number that single low section of voltage-controlled ring shakes expands to 8 by 4, and the split-phase number of whole low section of TDC circuit reaches 16, solves
Traditional low section of TDC circuit cannot take into account the contradiction between the frequency of oscillation that single low section of voltage-controlled ring shake and split-phase number.And in list
Individual low section of voltage-controlled ring center of percussion, if the series of low section of delay unit is more, although the increase of split-phase number, ring vibration frequency also can drop therewith
It is low, therefore resolution ratio is not actually improved.
Low section TDC circuits can make the resolution ratio of array type TDC circuits break through the minimum time delay of digital gate circuit, significantly carry
High systemic resolution.Shake to match the voltage-controlled ring in stage casing, need to add dummy circuits, but this can make whole array type TDC circuits
There is fixed 3ns delay time errors, i.e. Dead Time；Therefore, when timing is carried out using such array type TDC circuits, need to add
The constant time lag of upper 3ns.This case is strictly matched to the sequential for needing low section of TDC circuit and stage casing TDC circuits, although at low section
Dummy circuits are introduced in TDC circuits, but still error cannot be completely eliminated, it is therefore desirable to add calibration circuit to do whole circuit
It is further to calibrate.
Fig. 9 is the sequential chart Q of low section of TDC circuitL4～QL1The phase state of composition changes between following 8 states：
1110→1100→1000→1001→0001→0011→0111→0110→1110
When count stop signal STOP rising edges arrive, each section of TDC circuit is quit work simultaneously, and by each section of quantization
As a result be latching in corresponding DFF, wait start counting up signal EN trailing edges arrive when, under the driving of low-frequency clock signal L_CK by
Bits Serial is exported.
The above is only the preferred embodiment of the present invention, it should be pointed out that：For the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (6)
1. a kind of low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO, it is characterised in that：Including superelevation
Section TDC circuits, high section TDC circuit, stage casing TDC circuits, low section of TDC circuit and DFF latch chain, wherein freeboard section TDC circuits, height
Section TDC circuits and DFF latch chain and exclusively enjoy circuit for pixel and be placed in pixel, and stage casing TDC circuits and low section of TDC circuit are the overall situation
Shared circuit and it is placed in outside pixel；The measurement of time interval by freeboard section TDC circuits, high section TDC circuit, stage casing TDC circuits and
Low section of four partial order of TDC circuits cooperation is completed, final to realize that time interval is converted to digital value represents；
The freeboard section TDC circuits configure double mode LFSR counter, and high section TDC circuit configures double mode asynchronous subtraction meter
Number device, the voltage-controlled ring in stage casing TDC circuit configurations stage casing shake and double rotary single circuit, and low section of TDC circuits configuration Dual-DLL and VCO is returned
Road, the VCO loops are formed with the out of phase low section of voltage-controlled ring vibration level connection of frequency by X, and each low section of voltage-controlled ring shakes complete by Y
Exactly the same low section of delay unit cascade is formed, and each low section of voltage-controlled ring cascades a low section of delay path before shaking, i-th low section
Delay path is by XiIndividual identical delay unit cascade is formed, X >=2, Y >=2；LFSR counter is serially connected in asynchronous subtraction meter
Form mixing counter after number devices, the shake high frequency clock signal H_CK of generation of the voltage-controlled ring in stage casing drives asynchronous subtraction count device,
The high frequency clock signal H_LFSR of the asynchronous subtraction count device frequency dividings of Jing synchronously drives LFSR counter；
The quantized result of freeboard section TDC circuits is latched in LFSR counter by the pattern for switching LFSR counter, is passed through
The pattern for switching asynchronous subtraction count device is latched in the quantized result of high section TDC circuit in asynchronous subtraction count device, stage casing TDC
The quantized result of circuit and low section of TDC circuit latches chain by DFF and is latched；The LFSR counter, asynchronous subtraction meter
Number devices and DFF latch chain be mainly made up of DFF, read freeboard section TDC circuits, high section TDC circuit, stage casing TDC circuits and
During the quantized result of low section of TDC circuit, latch data by corresponding DFF series connection after in binary form from a high position to low level by
Bits Serial is exported.
2. the low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO according to claim 1, which is special
Levy and be：In the low section of TDC circuit, Dual-DLL is two-stage DLL structure, is divided into main DLL and time DLL, by Dual-DLL
Close loop negative feedback act on to low section of voltage-controlled ring shake provide with technique, supply voltage, temperature change high stability voltage-controlled electricity
Pressure；
It is provided with main DLL by the unit cascaded main voltage controlled delay line of N number of master delay, the input signal of main DLL is outside
Reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrf, by outside
Reference clock signal REF_CLK and N level master delay unit carries out phase state phase demodulation, voltage-controlled voltage VctrfAutomatically adjust main pressure
Control delay line, makes the phase state of external reference clock signal REF_CLK and N level master delay unit identical；
It is provided with secondary DLL by the secondary voltage controlled delay line of M delay cell cascade, the input signal of secondary DLL is outside
Reference clock signal REF_CLK and Dual-DLL enabling signal START_DLL, output signal are voltage-controlled voltage Vctrs, according to institute
The delay selection of the secondary voltage controlled delay line for needing goes out n-th grade of master delay unit, and n-th grade of master delay unit and M levels time are postponed
Unit carries out phase state phase demodulation, voltage-controlled voltage VctrsTime voltage controlled delay line is automatically adjusted, the phase place of n-th grade of master delay unit is made
State is identical with the phase state of M levels time delay cell.
3. the low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO according to claim 2, which is special
Levy and be：The voltage-controlled voltage VctrfAll low section of delay unit of all low sections voltage-controlled ring centers of percussion, voltage-controlled electricity is supplied to simultaneously
Pressure VctrsWhile all delay units in being supplied to all low section of delay paths；Signal EN is started counting up by during the delay of X bars
Between low section of different delay path control X low section of voltage-controlled ring respectively and shake beginning starting of oscillation, adjacent low section of voltage-controlled ring shake due to
Starting of oscillation first phase is different thus produce delay time error, and the delay time error passes through voltage-controlled voltage VctrsPrecise control, it is voltage-controlled by adjusting
Voltage VctrsMake adjacent low section of voltage-controlled ring certain sequential be met between shaking, finally cause X low section of voltage-controlled ring seamless between shaking
Gap linking coordinates.
4. the low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO according to claim 2, which is special
Levy and be：The stage casing TDC circuits are designed based on time difference quantization principles, and adopt DLL-OSC frameworks, i.e., by Dual-
The close loop negative feedback of the main DLL in DLL act on to the voltage-controlled ring in stage casing shake provide with technique, supply voltage, temperature change height
Stable voltage-controlled voltage Vctrf；The voltage-controlled ring in the stage casing shakes including the differential delay by N/2 differential delay cells cascade
Line and Logic control module：When the arrival of signal EN rising edges is started counting up, differential delay line is opened by Logic control module；
When the arrival of signal EN trailing edges is started counting up, differential delay line is turned off by Logic control module；Each grade of differential delay list
The output end of unit connects a double rotary single circuit, is converted to the both-end difference output of differential delay cells by double rotary single circuit
Single-end output, and shaping is carried out to output signal.
5. the low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO according to claim 1, which is special
Levy and be：Respectively arrange before the clock signal input terminal and data signal input of each DFF in asynchronous subtraction count device
One MUX starts counting up signal EN as the control signal of MUX as Logic control module：Work as beginning
When count signal EN is high level, the voltage-controlled ring in stage casing to shake and provide high frequency clock signal H_CK for asynchronous subtraction count device, asynchronous to subtract
Method counter works are in count mode；When start counting up signal EN for low level when, external low-frequency clock signal be asynchronous subtraction
Counter provides low-frequency clock signal, and asynchronous subtraction count device is operated in mode of serial transmission.
6. the low power consumption high-precision array type time-to-digital conversion circuit based on multiple VCO according to claim 1, which is special
Levy and be：The low section of TDC circuit directly latches freeboard section TDC circuits, height when count stop signal STOP rising edges arrive
The quantized result of section TDC circuits, stage casing TDC circuits and low section of TDC circuit.
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