CN104333365B - A kind of three-stage time-to-digital conversion circuit - Google Patents
A kind of three-stage time-to-digital conversion circuit Download PDFInfo
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Abstract
The invention discloses a kind of three-stage time figure conversion (TDC) circuit, the measurement of time interval is quantified to complete by section high, stage casing and low section of three partial segments.Section TDC high uses linear feedback shift register (LFSR) structure, realizes the measurement of wide scope；Middle section TDC uses ring oscillator structure, and the position for searching high frequency clock rising edge is differentiated by even phase, triggers latch signal and middle section count signal, and complete stage casing with coincidence counter measuring；The low section ring TDC that shakes completes the finer measurement of quantization error, using with middle section identical structure, and by the way of first decoding and transmitting afterwards.Total data is by logic control circuit Serial output successively in binary form.Compared to traditional three-stage TDC, TDC of the invention can realize that delay cell is multiplexed, so as to obtain more excellent architecture design and smaller chip area.Under identical accuracy of detection, its system power dissipation for producing substantially is reduced, therefore can be applied to the time measurement system of high-speed, high precision.
Description
Technical field
The present invention relates to a kind of three-stage time-to-digital conversion circuit, can be used in high-speed, high precision time measurement system.
Background technology
Time-to-digit converter (Time Digital Converter, TDC) is a kind of common circuit of time measurement, it
It is that time interval is converted into high-precision digital value, and realizes numeral output.It has been widely used in electronics neck at present
Domain, is such as used in all-digital phase-locked loop ADPLL, improves the time response of its test device and signal.In recent years, it is of greatest concern
TDC is the structure for using high speed CMOS digital circuit, and main cause is that signal-under-test can realize time precision higher.It is right
TDC accuracy is studied, and is beneficial to the application and quality assurance of TDC.
Longitudinal directionization with split-second precision quantification technique develops, and is occurred in that in analog IC field a collection of with time figure
Converter is the high-performance analog devices of core, for example high-speed low-power-consumption analog-digital converter and all-digital phase-locked loop etc.,
A series of design challenges of insurmountable analog circuit because of process limitation are overcome, is that the design of analog IC is opened
Brand-new design approach.Therefore, time-to-digit converter will be as contact simulation continuous time signal amount and digital discrete signal
One bridge of amount, a uncharted field as hybrid digital-analog integrated circuit design.
The content of the invention
Goal of the invention：For above-mentioned prior art, a kind of three-stage time-to-digital conversion circuit is proposed, compared to traditional three
Segmentation TDC structures, while wide scope, high-acruracy survey is realized, simplify circuit structure, reduce the area and work(of system
Consumption.
The content of the invention：A kind of three-stage time-to-digital conversion circuit, including section linear feedback shift register high, first phase
Adjustment circuit, delay matching circuit, middle section time-to-digital conversion circuit, adjacent signals extraction unit, low section time figure
Change-over circuit, two binary synchronous counters, directly decoding unit, decoding latch cicuit and serial data output circuits；
Wherein：
The first phase adjustment circuit of the high frequency clock CLK_H and initial signal EN of time quantization inputs, as the initial signal EN
During for high level, the just phase adjustment circuit produces EN0 signals at next rising edge of high frequency clock CLK_H and sends extremely
Section linear feedback shift register high；
Section linear feedback shift register high described in finish time Stop signal input, the section linear feedback high is moved
Bit register be used for the EN0 signals and high frequency clock CLK_H after Stop signal rising edges close to rising edge when
Between be spaced and quantified, obtain section quantized value kT highclk, wherein TclkIt it is the cycle of high frequency clock CLK_H, k is section high
The count value of linear feedback shift register；Section quantized value high is input to string by the section linear feedback shift register high
Row data output circuit；
The delay matching circuit is used to carry out delay disposal to the high frequency clock CLK_H according to the Stop signals,
Make high frequency clock CLK_H after Stop signal rising edges close to the delayed Stop signals t of rising edgeDFF+ANDTime, prolonged
The CLK_M signals for lagging, wherein tDFF+ANDFor the EN0 signals of just phase adjustment circuit generation fall behind high frequency clock CLK_
The inherent delay of H signal；
The CLK_M signals are separately input to middle section time-to-digital conversion circuit and low section time figure conversion electricity
Road；The middle section time-to-digital conversion circuit is annular TDC, including the first voltage-controlled ring being made up of level Four delay cell shakes list
Unit, the first voltage-controlled ring unit that shakes produces rising edge and the Stop signal alignments and the cycle is t according to outside voltage control signalM
=tclk/ 4 periodic signal, and it is input to adjacent signals extraction unit；The adjacent signals extraction unit scans the CLK_M
Signal rising edge is t in the cycleM=tclkInterval where in/4 periodic signal, so as to produce latch signal LOCK；
Two binary synchronous counters are used between the Stop signals and latch signal LOCK rising edges
Time interval carries out quantization measurement, obtains middle section quantized value TCounter=ntM, wherein n is two binary synchronous counters
Count value；Be input into for middle section quantized value and directly decode latch cicuit by the binary synchronous counter；
The low section time-to-digital conversion circuit is annular TDC, including second be made up of level Four delay cell be voltage-controlled
Ring shakes unit, and outside voltage control signal controls the shake ring of unit of the described second voltage-controlled ring to shake the cycle for tL, the CLK_M signals rising
Along as low section quantify gate-control signal, the second voltage-controlled ring shake unit composition eight phase node states through the decoding
After unit enters row decoding, when latch signal LOCK rising edges arrive, the directly decoding latch cicuit is used to latch now
The decoding value m of the decoding unit output, obtains low section quantized value (m/8) tL；
The directly decoding latch cicuit includes d type flip flop and either-or switch, for by middle section quantized value and low section
Position quantized value is latched in d type flip flop, and after being directly decoded into corresponding decimal value, by either-or switch control by data
It is latched into serial data output circuit；
The serial data output circuit is used for section quantized value high, middle section quantized value and low section amount to being input into
Change value Serial output successively, obtain initial signal EN0 and finish time Stop signal after first phase adjustment time interval it is complete
Office's expression formula is T=kTclk-n·tM+(m/8)·tL。
Further, the first voltage-controlled ring of the middle section time-to-digital conversion circuit shakes unit and low section time figure
Second voltage-controlled ring of change-over circuit shakes the delay chain that the unit multiplexed delay cell by the voltage-controlled phase inverter of current-steering is constituted.
Further, the decoding unit is the NOR gate circuit using Gray code decoded mode.
Beneficial effect：Three-stage time-to-digital conversion circuit of the invention, is divided into section high, stage casing and low section of three parts meter
Number, wherein section TDC high uses linear feedback shift register (LFSR), the time for quantifying to realize wide scope using counter surveys
Amount；Stage casing TDC is shaken structure using ring, and the annular oscillation circuit is made up of level Four voltage-controlled delay unit, using end signal Stop as door
Control signal, the frequency of generation provides counting clock signal to binary synchronous counter；Low section TDC is using identical with middle section
Ring shake structure, used as gate-control signal, ring shakes internal phase node state warp the high frequency clock signal CLK_M using delayed shaping
As low section data output after decoding.
In, low section use annular TDC, its closed loop delay line use the voltage-controlled phase inverter of current-steering delay list
Unit, voltage control signal by external setting-up, with fixed voltage value control has the shake frequency of unit output of two voltage-controlled rings
Stability higher.Meanwhile, the first voltage-controlled ring of middle section time-to-digital conversion circuit shakes unit and low section time figure turns
The the second voltage-controlled ring for changing circuit shakes the delay chain that the unit multiplexed delay cell by the voltage-controlled phase inverter of current-steering constitutes, two
TDC is controlled using different gate-control signals, in realization, low section of quantization function while, reduce the area and power consumption of circuit.
Due in first phase adjustment circuit EN0 signals fall behind high frequency clock CLK_H after Stop signal rising edges close to
Rising edge tDFF+ANDTime, the tDFF+ANDTime is the d type flip flop in first phase adjustment circuit and the inherent delay sum with door.In
Use delay matching circuit, the delay matching circuit to be made up of d type flip flop and door and phase inverter before section TDC, believed according to Stop
Number delay disposal is carried out to high frequency clock CLK_H, make high frequency clock CLK_H after Stop signal rising edges close to rising edge
Delayed Stop signals tDFF+ANDTime, the CLK_M signals after being postponed, so that overall measurement time interval is constant, it is real
The delay matching of section high and middle section is showed.
The decoding unit for connecting low section TDC is the NOR gate circuit using Gray code decoded mode, is translated using Gray code
Code mode, greatly reduces logic and obscures, and reduces the output frequency of lowest weightings position, substantially reduces the bit error rate.Using phase
With shaken to voltage-controlled ring in low section TDC eight phase node states of unit of decoding circuit structure enter row decoding, realize and prolong
Match late and symmetrical configuration.
Three-stage time-to-digital conversion circuit can be operated in counting and data transfer both of which, both patterns difference
With high-frequency count clock and low-frequency transmission clock control, enumeration data is in binary data form successively Serial output.
Relative to traditional two-part time-to-digit converter, the three-stage time-to-digital conversion circuit in the present invention can
The performance requirement of certainty of measurement and dynamic range is taken into account well, realizes more accurately time measurement.Intersegmental adjacent signals are extracted
The time interval of adjacent segment is carried out areal survey by technology using different measuring methods, so as to be multiplexed in each section of TDC
Delay chain, acreage reduction simplifies circuit structure.
Brief description of the drawings
Fig. 1 is the structural representation of three-stage time-to-digital conversion circuit；
Fig. 2 is low section of TDC time measurement principle timing diagram in three-stage time-to-digital conversion circuit；
Fig. 3 is low section of TDC circuit structure diagram in three-stage time-to-digital conversion circuit；
Fig. 4 counts/transmits double mode LFSR structures for the section high of three-stage time-to-digital conversion circuit；
Fig. 5 is low section of TDC5 data latch and transmission structure figure in three-stage time-to-digital conversion circuit；
Fig. 6 is the low section of voltage-controlled delay cellular construction figure of TDC in three-stage time-to-digital conversion circuit；
Fig. 7 is the timing diagram of three-stage time-to-digital conversion circuit.
Specific embodiment
The present invention is further described with reference to accompanying drawing.
As shown in figure 1, a kind of three-stage time-to-digital conversion circuit, including section linear feedback shift register high, just
Phase adjustment circuit, delay matching circuit, middle section time-to-digital conversion circuit, adjacent signals extraction unit, low section time number
Word change-over circuit, two binary synchronous counters, directly decoding unit, decoding latch cicuit and serial data output electricity
Road.
Wherein, the first phase adjustment circuit of the high frequency clock CLK_H and initial signal EN of time quantization inputs, as initial signal EN
During for high level, just phase adjustment circuit produces EN0 signals at next rising edge of high frequency clock CLK_H and sends to section high
Position linear feedback shift register.
Finish time Stop signal input section linear feedback shift register high, section linear feedback shift register high
To EN0 signals and high frequency clock CLK_H after Stop signal rising edges close to the time interval of rising edge quantify, obtain
To section quantized value kT highclk, wherein TclkIt it is the cycle of high frequency clock CLK_H, k is section linear feedback shift register high
Count value.Section quantized value high is input to serial data output circuit by section linear feedback shift register high.
Because EN0 signals fall behind high frequency clock CLK_H signal fixed delays tDFF+AND, cause EN0 signals and Stop signals
Time interval it is relatively reduced.Delay matching circuit carries out delay disposal according to Stop signals to high frequency clock CLK_H, makes high frequency
Clock CLK_H after Stop signal rising edges close to the delayed Stop signals t of rising edgeDFF+ANDTime, after being postponed
CLK_M signals, wherein tDFF+ANDFall behind the inherent delay of CLK_H signals for the EN0 signals of first phase adjustment circuit generation.Such as
Fig. 2 show low section of TDC time measurement principle timing diagram in three-stage TDC, and CLK_M is by delay matching, positioned at knot
High frequency clock signal after beam moment Stop signals rising edge.In the case of without any delay, CLK_M should be with Stop signals
Rising edge alignment, due to exist postpone tDFF+AND, the time that CLK_M signals rising edge arrives postpones backward, and CLK_M should be with
Maximum delay between Stop signals is no more than a high frequency clock cycles Tclk.Adding delay matching circuit makes CLK_M signals same
Sample falls behind Stop signals tDFF+ANDFixed delay, so as to realize delay matching, make overall measurement time interval keep it is constant.
CLK_M signals are separately input to middle section time-to-digital conversion circuit and low section time-to-digital conversion circuit,
Middle section time-to-digital conversion circuit is annular TDC, including the first voltage-controlled ring being made up of level Four delay cell shakes unit.First
The voltage-controlled ring unit that shakes produces rising edge and Stop signal alignments and the cycle is t according to outside voltage control signalM=tclk/ 4 cycle letter
Number S0~S3, and it is input to adjacent signals extraction unit.Adjacent signals extraction unit scans CLK_M signal rising edges
tM=tclkInterval where in/4 periodic signal, so as to produce latch signal LOCK.Because the scanning signal cycle is tM=
tclk/ 4, and the time interval of Stop signals and CLK_M signal rising edges is less than Tclk, then CLK_M signals rising edge be necessarily in
In the range of S0~S3 signal spacings.If CLK_M signals rising edge is in the range of S0~S3 signal spacings on two adjacent signals
Rise between, then by the rising edge triggering latch signal LOCK of latter signal.Stop signals rising edge is to latch signal LOCK
The time interval of rising edge is middle section TDC quantized values TCounter, and TCounterNecessarily it is no more than 4tM, therefore the generation of middle section
The value of count signal Count be necessarily not more than 4, then can complete countings with two binary synchronous counters.It is same by this
Step counter carries out quantization measurement to the time interval between Stop signals and latch signal LOCK rising edges, obtains middle section amount
Change value TCounter=ntM, wherein n is two count values of binary synchronous counter.Then, binary synchronous counter will
Middle section quantized value input directly decodes latch cicuit.
CLK_M rising edges are low section ring and shake TDC time of measuring surpluses t to the time interval of LOCK rising edgesR.Low section
Position time-to-digital conversion circuit is annular TDC, including the second voltage-controlled ring being made up of level Four delay cell shakes unit, and outside is voltage-controlled
Signal controls the shake ring of unit of the second voltage-controlled ring to shake the cycle for tL, CLK_M signals rising edge as low section quantify trigger signal,
Second voltage-controlled ring shake unit composition eight phase node state decoded units enter row decoding after, when on latch signal LOCK
Rising during along arriving, directly decoding the decimal system decoding value m of latch circuit latches now decoding unit output, obtain low section and quantify
Value tR=(m/8) tL.The expression formula of low section of time measurement is in then：
TM=TCounter-tR=ntM-tR=ntM-(m/8)·tL (1)
Directly decoding latch cicuit includes d type flip flop and either-or switch, for by middle section quantized value and low section amount
Change value is latched in d type flip flop, and after being directly decoded into corresponding decimal value, is latched data by either-or switch control
To in serial data output circuit.
Serial data output circuit is used for section quantized value high, middle section quantized value and low section quantized value to being input into
Serial output, obtains the global table of the time interval of initial signal EN0 and finish time Stop signal after first phase adjustment successively
It is up to formula：
T=kTclkTM=kTclkn·tM+(m/8·)tL (2)
In above-mentioned three-stage time-to-digital conversion circuit, the first voltage-controlled ring of middle section time-to-digital conversion circuit shakes list
Shaken with the second voltage-controlled ring of low section time-to-digital conversion circuit and be singly multiplexed by the delay cell of the voltage-controlled phase inverter of current-steering
The delay chain of composition.
Low section of TDC circuit structure diagram in being illustrated in figure 3, the logic being made up of d type flip flop and door and phase inverter on the left side
Circuit is delay matching circuit.Middle section annular oscillation circuit with Stop as gate-control signal produces the cycle as tM=tclk/ 4 cycle
S0, S1, S2, S3 signal in signal, i.e. Fig. 2, the interval where for scanning CLK_M signal rising edges.If CLK_M rising edges
Between two adjacent signals rising edges, then latch signal LOCK is produced by the rising edge triggering d type flip flop of latter signal,
The number of periodic signal while the ring recorded between Stop signals and LOCK signal shakes, triggers Count count signals.With CLK_
M for gate-control signal low section annular oscillation circuit produce eight phase node status informations by LOCK signal sample, by by
The decoding circuit that XOR gate is constituted produces low section three data Q0, Q1, Q2.Either-or switch in the annular oscillation circuit and anti-phase
The delay of device matches with the time delay of three delay cells, it is to avoid because path has edge error code problem caused by delay mismatches.
Decoding circuit uses Gray code decoded mode, this eight phase node states is decoded into three data outputs so that low section
The frequency of TDC lowest weightings position data has larger decline, it is to avoid straight binary decoding circuit is led because minimum bit frequency is too high
The d type flip flop error code of cause.Low section ring shake TDC phase states Gray code decoding table as shown in table 1, the decoding of Q0, Q1, Q2 is defeated
The expression formula for going out position is respectively：
Table 1
Section TDC high is as shown in Figure 4 using the/double mode 7bit LFSR structures of transmission, circuit is counted.EN0 is adjusted for first phase
Control signal after whole, works as EN, and when EN0 is all high level, either-or switch gates 1 port, is controlled to count by CLK_H clock signals
Count and latch.Work as EN, when EN0 is all low level, into the Serial output stage controlled by low-frequency transmission clock CLK_L signals,
7 data Q5-Q11 of section TDC high are successively from Q11 ports Serial output.In low section of low 5 data of TDC pass through alternative
Switch flows to the right from the circuit left side, follows section serial mode output high closely.In the present embodiment, 7bit LFSR knots are input to
The CLK_H clock signals of structure are first pre-processed, and high-frequency signal H_CK and signal SH is tied by being input to 7bit LFSR with door
The input of the clock signal of structure, its high frequency signal H_CK is cycle TclkClock signal, signal SH as shown in Figure 3 is logical
The inversion signal of CLK_M signal generations is crossed, the structure plays a part of to turn off CLK_H signals.Due to needing on measurement Stop signals
Rise and be spaced along with close to next CLK_H rising times, so high-frequency count clock must be turned off after taking time interval, it is to avoid
Section TDC miscounts high, its timing diagram is as shown in Figure 7.
Low section of low 5 data-latching circuit of TDC in being illustrated in figure 5, the circuit by two binary synchronous counters,
Five either-or switch and low section data latch d type flip flop composition.The first two either-or switch is by selected middle section Count
Count signal and low-frequency transmission signal CLK_L are counted and transmitted come section in controlling respectively, and three either-or switch and D are triggered afterwards
Device is latched and transmits low section data.When EN is high level, either-or switch gates 1 port, it is allowed to latch signal LOCK pairs
Three data of low section are directly latched, while middle section count signal Count triggers two binary synchronous counters opening
Begin to count, produce stage casing position data Q3, Q4.When EN is low level, latches and counting stops, opening mode of serial transmission.
5 data of low section constitute the output of 12 Bits Serials from rightmost successively Serial output to section TDC transmission circuits high in final
Binary code.
In, low section TDC use voltage-controlled inverting delay cells, as shown in fig. 6, be connected on a pair of voltage-controlled current sources instead by it
Between phase device, by the control of complementary voltage, the propagation delay by being input to output can be effectively controlled.With control voltage OE
Increase, be controlled metal-oxide-semiconductor conducting resistance and reduce, the discharge current of phase inverter increases, and time delay reduces.Meanwhile, work as delay cell
It is input into during for high level, Nixie tube constitutes negative-feedback in the source of control pipe, reduces susceptibility of the electric current to control voltage, increases
The strong stability of delay cell transmission time.
Three-stage time-to-digital conversion circuit of the invention, realizes the time measurement of high measurement accuracy and wide scope, its
Less area is occupied, relatively low power consumption is consumed, the time measurement system of high-speed, high precision is can be applied to.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, under the premise without departing from the principles of the invention, some improvements and modifications can also be made, these improvements and modifications also should
It is considered as protection scope of the present invention.
Claims (3)
1. a kind of three-stage time-to-digital conversion circuit, it is characterised in that：Including section linear feedback shift register high, first phase
Adjustment circuit, delay matching circuit, middle section time-to-digital conversion circuit, adjacent signals extraction unit, low section time figure
Change-over circuit, two binary synchronous counters, directly decoding unit, decoding latch cicuit and serial data output circuits；
Wherein：
The first phase adjustment circuit of the high frequency clock CLK_H and initial signal EN of time quantization inputs, when the initial signal EN is height
During level, the just phase adjustment circuit produces EN0 signals at next rising edge of high frequency clock CLK_H and sends to section high
Position linear feedback shift register；
Section linear feedback shift register high described in finish time Stop signal input, the section linear feedback shift high is posted
Storage be used for the EN0 signals and high frequency clock CLK_H after the Stop signal rising edges close to rising edge time between
Every being quantified, section quantized value kT high is obtainedclk, wherein TclkIt it is the cycle of high frequency clock CLK_H, k is that section high is linear
The count value of feedback shift register；Section quantized value high is input to serial number by the section linear feedback shift register high
According to output circuit；
The delay matching circuit is used to carry out delay disposal to the high frequency clock CLK_H according to the Stop signals, makes height
Frequency clock CLK_H after Stop signal rising edges close to the delayed Stop signals t of rising edgeDFF+ANDTime, after being postponed
CLK_M signals, wherein tDFF+ANDFor the EN0 signals of just phase adjustment circuit generation fall behind high frequency clock CLK_H letters
Number inherent delay；
The CLK_M signals are separately input to middle section time-to-digital conversion circuit and low section time-to-digital conversion circuit；
The middle section time-to-digital conversion circuit is annular TDC, including the first voltage-controlled ring being made up of level Four delay cell shakes unit,
The first voltage-controlled ring unit that shakes produces rising edge and the Stop signal alignments and the cycle is t according to outside voltage control signalM=
tclk/ 4 periodic signal, and it is input to adjacent signals extraction unit；The adjacent signals extraction unit scans the CLK_M letters
Number rising edge is t in the cycleM=tclkInterval where in/4 periodic signal, so as to produce latch signal LOCK；
Two binary synchronous counters were used for the time between the Stop signals and latch signal LOCK rising edges
Interval carries out quantization measurement, obtains middle section quantized value TCounter=ntM, wherein n is two meters of binary synchronous counter
Numerical value；Be input into for middle section quantized value and directly decode latch cicuit by the binary synchronous counter；
The low section time-to-digital conversion circuit is annular TDC, including the second voltage-controlled ring being made up of level Four delay cell shakes
Unit, outside voltage control signal controls the shake ring of unit of the described second voltage-controlled ring to shake the cycle for tL, the CLK_M signals rising edge work
Be low section quantify gate-control signal, the second voltage-controlled ring shake unit composition eight phase node states through the decoding unit
After entering row decoding, when latch signal LOCK rising edges arrive, it is now described that the directly decoding latch cicuit is used for latch
The decoding value m of decoding unit output, obtains low section quantized value (m/8) tL；
The directly decoding latch cicuit includes d type flip flop and either-or switch, for by middle section quantized value and low section amount
Change value is latched in d type flip flop, and after being directly decoded into corresponding decimal value, is latched data by either-or switch control
To in serial data output circuit；
The serial data output circuit is used for section quantized value high, middle section quantized value and low section quantized value to being input into
Serial output, obtains the global table of the time interval of initial signal EN0 and finish time Stop signal after first phase adjustment successively
It is T=kT up to formulaclk-n·tM+(m/8)·tL。
2. a kind of three-stage time-to-digital conversion circuit according to claim 1, it is characterised in that：The middle section time
First voltage-controlled ring of digital conversion circuit shake unit and low section time-to-digital conversion circuit the second voltage-controlled ring shake it is unit multiplexed
The delay chain being made up of the delay cell of the voltage-controlled phase inverter of current-steering.
3. a kind of three-stage time-to-digital conversion circuit according to claim 1, it is characterised in that：The decoding unit is
Using the NOR gate circuit of Gray code decoded mode.
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| CN109814367B (en) * | 2018-12-29 | 2020-07-17 | 西安电子科技大学 | Time-to-digital converter with gating enabling function |
| CN113206668B (en) * | 2021-05-11 | 2022-10-28 | 中国科学技术大学 | Two-stage interpolation time digital converter circuit |
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| CN114114211B (en) * | 2021-12-03 | 2022-09-06 | 武汉市聚芯微电子有限责任公司 | TDC unit, TDC array and ranging system |
| CN114935886B (en) * | 2022-04-21 | 2023-04-28 | 中国科学院上海微***与信息技术研究所 | Two-stage superconducting time-to-digital converter and superconducting detector imaging system |
| CN114815570B (en) * | 2022-05-05 | 2024-02-13 | 陕西科技大学 | Time-to-digital converter based on differential delay loop |
| CN114995092B (en) * | 2022-06-15 | 2024-02-23 | 西安电子科技大学芜湖研究院 | Time-to-digital conversion circuit |
| CN116153362B (en) * | 2023-04-20 | 2023-08-25 | 浙江力积存储科技有限公司 | Delay feedback method and delay feedback storage structure for read latency counter |
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| CN102651685A (en) * | 2011-02-24 | 2012-08-29 | 爱立信(中国)通信有限公司 | Signal delay device and method |
| CN103208994A (en) * | 2013-03-11 | 2013-07-17 | 东南大学 | Two-stage time digital convert (TDC) circuit |
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