CN117368698B

CN117368698B - Chip circuit and testing method thereof

Info

Publication number: CN117368698B
Application number: CN202311447797.5A
Authority: CN
Inventors: 徐嘉俊; 李玲玲; 徐柳明; 刘洋
Original assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Current assignee: Hexin Technology Co ltd; Shanghai Hexin Digital Technology Co ltd
Priority date: 2023-11-01
Filing date: 2023-11-01
Publication date: 2024-05-24
Anticipated expiration: 2043-11-01
Also published as: CN117368698A

Abstract

The invention provides a chip circuit and a testing method thereof, wherein the chip circuit comprises: at least two sub-modules and at least two input stage pipeline modules; each submodule carries out signal input and signal output in a feed-through connection mode, wherein on a feed-through link formed by each submodule, each input port of an input stage submodule is connected to the same top-layer input pin of a chip circuit through different input stage pipeline modules, each output port of an output stage submodule is connected to different top-layer output pins of the chip circuit, and the input stage pipeline modules are used for adjusting the time of an input signal reaching each submodule. The invention solves the problems of the prior art that the research and development cost and the research and development period are increased due to the fact that a plurality of multiplexing sub-modules are separately tested by a plurality of sets of test vectors.

Description

Chip circuit and testing method thereof

Technical Field

The present invention relates to the field of testing technologies, and in particular, to a chip circuit and a testing method thereof.

Background

In large chips, the entire chip is typically diced into a plurality of modules for operation; the DFT (Designfortest) function of the sub-module is independent of the DFT function of the top module, and the input pins on the top module can be directly applied to the sub-module to perform the vector test of ATPG (Automatic TEST PATTERN Generation).

When multiplexing a large number of identical sub-modules, each sub-module usually uses a feed-through (Feedthrough) connection, i.e. a connection where the rear terminal module passes through the front terminal module to the top layer, for compactness; however, the time for the signals input from the top-level input pins to reach each sub-module is not equal, so that the vector test of the ATPG needs to be performed separately by multiple sub-modules and multiple sets of test vectors, which greatly increases the research and development cost of the chip and the research and development period of the physical implementation of the chip.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a chip circuit and a testing method thereof, which are used for solving the problem that in the prior art, the research and development cost and the research and development period are increased due to the separate testing of a plurality of sub-modules multiplexed by a plurality of test vectors.

To achieve the above and other related objects, the present invention provides a chip circuit including at least two sub-modules and at least two input stage pipeline modules;

And each sub-module carries out signal input and signal output in a feed-through connection mode, wherein on a feed-through link formed by each sub-module, each input port of an input stage sub-module is connected to the same top-layer input pin of the chip circuit through different input stage pipeline modules, each output port of an output stage sub-module is connected to different top-layer output pins of the chip circuit, and the input stage pipeline modules are used for adjusting the time for an input signal to reach each sub-module.

Optionally, the number of the input stage sub-modules is one, the number of the output stage sub-modules is one, and the input stage sub-modules and the output stage sub-modules are the same or different sub-modules;

The number of the input ports in each sub-module is reduced from K to one from the input stage sub-module, the number of the output ports is reduced from K to one from the output stage sub-module, the input ports at least comprise the input ports of the present stage, the output ports at least comprise the output ports of the present stage, the number of the input ports of the present stage is one, the number of the output ports of the present stage is one, K is the number of the sub-modules, and K is an integer greater than 1.

Optionally, the number of the input stage sub-modules is two, the number of the output stage sub-modules is one, and the output stage sub-modules and one of the input stage sub-modules are the same sub-modules;

The number of the input ports in each sub-module is (K+1), the number of the output ports is reduced from K to one from the output stage sub-module, the input ports at least comprise the input ports of the present stage, the output ports at least comprise the output ports of the present stage, the number of the input ports of the present stage is two, the two input ports of the present stage are arranged on two opposite sides of the sub-module, input selection is carried out through a two-way selector, the number of the output ports of the present stage is one, and K is the number of the sub-modules and an integer larger than 1.

Optionally, the input stage pipeline module includes M first registers and a first multiplexer, each first register is cascaded to the top input pin to form (m+1) connection points, and is respectively connected to (m+1) selection ends of the first multiplexer, a control end of the first multiplexer receives an input selection control signal, and an output end of the first multiplexer is connected to a corresponding input port of the input stage submodule, where M is an integer greater than 1.

Optionally, the chip circuit further includes at least two output stage pipeline modules, wherein each output port of the output stage sub-modules is connected to a different top-level output pin of the chip circuit through a different output stage pipeline module, and the output stage pipeline module is used for adjusting a time when an output signal of each sub-module reaches each top-level output pin.

Optionally, the output stage pipeline module includes N second registers and second multiplexers, each second register is cascaded to a corresponding output port of the output stage sub-module to form (n+1) connection points, each second register is connected to (n+1) selection ends of the second multiplexers, a control end of the second multiplexers receives an output selection control signal, and an output end of the second multiplexers is connected to a corresponding top layer output pin, where N is an integer greater than 1.

Optionally, each of the submodules is connected to feed-through via a third register.

The invention also provides a testing method of the chip circuit, which comprises the following steps:

the input signals reach each of the sub-modules at the same time by configuring the number of first registers in each of the input stage pipeline modules.

Optionally, the test method further comprises:

By configuring the number of second registers in each output stage pipeline module, the output signals of each submodule reach each top-layer output pin after the same time.

Optionally, when the number of the input stage sub-modules is two, each sub-module performs input selection according to the configuration number of the first registers in each input stage pipeline module.

As described above, the chip circuit and the testing method thereof of the invention adjust the time of the input signal reaching each sub-module through the input stage assembly line module to realize the time sequence convergence of the input signal, thus, the same set of testing vectors can be utilized in a broadcasting mode to test each sub-module multiplexed in the chip at the same time, the testing time is saved, and the testing cost is reduced.

Drawings

Fig. 1 is a schematic diagram showing a chip circuit according to an embodiment of the invention.

Fig. 2 is a schematic diagram showing a chip circuit according to another embodiment of the invention.

Fig. 3 is a schematic diagram showing a chip circuit according to another embodiment of the invention.

Fig. 4 is a schematic diagram showing a chip circuit according to still another embodiment of the invention.

Fig. 5 shows a schematic structural diagram of an input stage pipeline module according to the present invention.

Fig. 6 shows a schematic diagram of the output stage pipeline module according to the present invention.

Description of element reference numerals

100. Chip circuit

110. Sub-module

111. Compression unit

112. Third register

113. Two-way selector

120. Input stage pipeline module

121. First register

122. First multiplexer

130. Output stage pipeline module

131. Second register

132. Second multiplexer

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 6. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Fig. 1 to 4 show different structural schematic diagrams of a chip circuit 100 of the present embodiment, in which an EDT schematic compression unit 111 is used, a Reg3 (e.g., reg31-Reg 35) is used to schematic a third register 112, a MUX3 is used to schematic a two-way selector 113, an IP (e.g., IP1-IP 6) is used to schematic an input stage pipeline module 120, and an OP (e.g., OP1-OP 3) is used to schematic an output stage pipeline module 130; first register 121 is illustrated using Reg1 (e.g., reg11-Reg 34), and first multiplexer 122 is illustrated using MUX 1; the second register 131 is illustrated using Reg2 (e.g., reg21-Reg 24) and the second multiplexer 132 is illustrated using MUX 2.

As shown in fig. 1 to 4, the chip circuit 100 provided in the present embodiment includes at least two sub-modules 110 and at least two input stage pipeline modules 120; each sub-module 110 performs signal input and signal output IN a feed-through connection manner, wherein on a feed-through link formed by each sub-module 110, each input port of an input stage sub-module is connected to the same top input pin IO/IN of the chip circuit 100 through different input stage pipeline modules 120, each output port of an output stage sub-module is connected to different top output pins IO/OUT of the chip circuit 100, and the input stage pipeline modules 120 are used for adjusting time when an input signal reaches each sub-module 110, so that the input signal reaches each sub-module 110 through the same time.

Specifically, each sub-module 110 is configured to compress an input signal (such as a scan chain data signal) and output the compressed input signal, however, other processing of the input signal by each sub-module 110 is also possible, which has no substantial effect on the present embodiment. As an alternative, each sub-module 110 compresses an input signal by the compression unit 111 and outputs the compressed input signal, wherein the compression unit 111 compresses the input signal using a scan test compression scheme of an Embedded Deterministic Test (EDT).

The feed-through connection means a connection mode that the rear terminal module passes through the front terminal module to reach the top layer, and in practical application, each sub-module 110 implements feed-through connection through the third register 112. On the feed-through link formed by the sub-modules 110, the sub-modules 110 located at both ends, such as the head sub-module and the tail sub-module, can be used as an input stage sub-module and an output stage sub-module.

It should be noted that the input stage sub-module refers to a sub-module 110 that introduces an input signal from a top-level input pin IO/IN to a feed-through link, such as the first sub-module 110 IN fig. 1 and 2, the first sub-module 110 and the third sub-module 110 IN fig. 3 and 4; the output stage sub-module refers to a sub-module 110 that directs output signals from the feed-through link to the top-level output pins IO/OUT, such as the first sub-module 110 in fig. 1 and 3, and the third sub-module 110 in fig. 2 and 4.

In one possible implementation, the number of input stage sub-modules is one, the number of output stage sub-modules is one, the input stage sub-modules and the output stage sub-modules are the same sub-module 110 as shown in fig. 1, or the input stage sub-modules and the output stage sub-modules are different sub-modules 110 as shown in fig. 2.

In this implementation, the number of input ports in each submodule 110 decreases from K to one from the input stage submodule, the number of output ports decreases from K to one from the output stage submodule, the input ports at least include the input ports of the present stage, the output ports at least include the output ports of the present stage, the number of the input ports of the present stage is one, the number of the output ports of the present stage is one, K is the number of the submodules 110, and K is an integer greater than 1.

Taking the example that the number of sub-modules 110 is three (i.e., k=3), the first sub-module 110 serves as both an input stage sub-module and an output stage sub-module; the first sub-module 110 includes a compression unit 111, five third registers 112, three input ports IN1-IN3, three output ports OUT1-OUT3, and four transmission ports TR1-TR4, the three input ports IN1-IN3 including a present stage input port IN1, a second stage input port IN2, and a third stage input port IN3, the three output ports OUT1-OUT3 including a present stage output port OUT1, a second stage output port OUT2, and a third stage output port OUT3; the second sub-module 110 includes a compression unit 111, three third registers 112, two input ports IN2-IN3, two output ports OUT2-OUT3, and two transmission ports TR1-TR2, the two input ports IN2-IN3 including a present stage input port IN2 and a three stage input port IN3, the two output ports OUT2-OUT3 including a present stage output port OUT2 and a three stage output port OUT3; the third sub-module 110 includes a compression unit 111, a third register 112, an input port IN3, and an output port OUT3, the input port IN3 and the output port OUT3 being the present stage input port and the present stage output port, respectively; the connections of the various parts and the feed-through paths of the input signal and the output signal are shown in fig. 1.

Of course, the third sub-module 110 is used as both an input stage sub-module and an output stage sub-module, or the first sub-module 110 is used as an input stage sub-module and the third sub-module 110 is used as an output stage sub-module, or even the first sub-module 110 is used as an output stage sub-module and the third sub-module 110 is used as an input stage sub-module, which are all feasible, and only the circuit structure needs to be adaptively adjusted.

Taking the first sub-module 110 as an input stage sub-module and the third sub-module 110 as an output stage sub-module as an example, the first sub-module 110 includes a compression unit 111, two third registers 112, three input ports IN1-IN3, an output port OUT1 and two transmission ports TR1-TR2, and the three input ports IN1-IN3 include a present stage input port IN1, a second stage input port IN2 and a third stage input port IN3; the second sub-module 110 includes a compression unit 111, two third registers 112, two input ports IN2-IN3, two output ports OUT1-OUT2, and two transmission ports TR1-TR2, the two input ports IN2-IN3 including a present stage input port IN2 and a three stage input port IN3, the two output ports OUT1-OUT2 including a present stage output port OUT2 and a one stage output port OUT1; the third sub-module 110 includes a compression unit 111, two third registers 112, an input port IN3, three output ports OUT1-OUT3 and two transmission ports TR1, the input port IN3 being the present stage input port, the three output ports OUT1-OUT3 including a present stage output port OUT3, a first stage output port OUT1 and a second stage output port OUT2; the connections of the various parts and the feed-through paths for the input and output signals are shown in fig. 2.

IN the above implementation manner, the first terminal module or the tail terminal submodule is selected as the input stage submodule on the feed-through link, which is generally determined by the physical distance between the first terminal module and the tail terminal submodule and the top-layer input pin IO/IN, and the submodule 110 with a relatively close physical distance to the top-layer input pin IO/IN is generally selected as the input stage submodule; similarly, the sub-module 110 that is physically closer to the top output pin IO/OUT is generally selected as the output stage sub-module.

In another possible implementation, the number of input stage sub-modules is two, the number of output stage sub-modules is one, and the output stage sub-module and one of the input stage sub-modules are the same sub-module 110, as shown in fig. 3 and 4.

In this implementation manner, the number of input ports in each sub-module 110 is (k+1), the number of output ports is reduced from K to one from the output stage sub-module, the input ports at least include the input ports of the present stage, the output ports at least include the output ports of the present stage, the number of input ports of the present stage is two, the two input ports of the present stage are disposed at two opposite sides of the sub-module 110, and input selection is performed through the two-way selector 113, where the two-way selector 113 is controlled by an internal selection control signal (not shown in the figure), the number of output ports of the present stage is one, K is the number of the sub-module 110, and K is an integer greater than 1.

Taking the example that the number of the sub-modules 110 is three (i.e. k=3), the first sub-module 110 and the third sub-module 110 are used as input stage sub-modules, and the first sub-module 110 is also used as output stage sub-module; the first sub-module 110 includes a compression unit 111, five third registers 112, a two-way selector 113, four input ports IN11-IN13 and IN31, three output ports OUT1-OUT3 and four transmission ports TR1-TR4, the four input ports including two present stage input ports IN11 and IN31, one second stage input port IN12 and one third stage input port IN13, the three output ports OUT1-OUT3 including one present stage output port OUT1, one second stage output port OUT2 and one third stage output port OUT3; the second sub-module 110 comprises a compression unit 111, four third registers 112, a two-way selector 113, four input ports IN12-IN13 and IN31-IN32, two output ports OUT2-OUT3 and three transmission ports TR1-TR3, the four input ports comprising two present stage input ports IN12 and IN32, one three stage input port IN13 and one stage input port IN31, the two output ports comprising one present stage output port OUT2 and one three stage output port OUT3; the third sub-module 110 includes a compression unit 111, three third registers 112, a two-way selector 113, four input ports IN13 and IN31-IN33, an output port OUT3, and two transmission ports TR1-TR2, the four input ports including two present stage input ports IN13 and IN33, a second stage input port IN32, and a first stage input port IN31, the output port OUT3 being the present stage output port; the connections of the various parts and the feed-through paths for the input and output signals are shown in fig. 3.

Of course, the third sub-module 110 is also possible as an output stage sub-module, and IN this case, the first sub-module 110 includes a compression unit 111, two third registers 112, a two-way selector 113, four input ports IN11-IN13 and IN31, an output port OUT1 and two transmission ports TR1-TR2, and the four input ports include two present stage input ports IN11 and N31, a second stage input port IN12 and a third stage input port IN13, and the output port OUT1 is the present stage output port; the second sub-module 110 includes a compression unit 111, three third registers 112, a two-way selector 113, four input ports IN12-IN13 and IN31-IN32, two output ports OUT2-OUT3 and three transmission ports TR1-TR3, the four input ports including two present stage input ports IN12 and IN32, one three stage input port IN13 and one stage input port IN31, the two output ports OUT2-OUT3 including one present stage output port OUT2 and one stage output port OUT1; the third sub-module 110 includes a compression unit 111, four third registers 112, a two-way selector 113, four input ports IN13 and IN31-IN33, three output ports OUT1-OUT3, and four transmission ports TR1-TR4, the four input ports including two present stage input ports IN13 and IN33, one second stage input port IN32, and one first stage input port IN31, the three output ports OUT1-OUT3 including one present stage output port OUT3, one second stage output port OUT2, and one first stage output port OUT1; the connections of the various parts and the feed-through paths for the input and output signals are shown in fig. 4.

IN the above implementation manner, each sub-module 110 performs input selection through the two-way selector 113, and the path length of each sub-module 110 to the top input pin IO/IN is optimized by selecting the input direction so as to obtain a relatively shorter input path; the first terminal module or the tail terminal sub-module is selected as the output stage sub-module on the feed-through link, and is generally determined by the physical distances between the first terminal module and the tail terminal sub-module and the top output pin IO/OUT, and the sub-module 110 having a relatively close physical distance with the top output pin IO/OUT is generally selected as the output stage sub-module.

Specifically, as shown IN fig. 5, the input stage pipeline module 120 includes M first registers 121 and first multiplexers 122, each first register 121 is cascaded to a top input pin IO/IN to form (m+1) connection points, and is respectively connected to (m+1) selection ends of the first multiplexers 122, a control end of the first multiplexers 122 receives an input selection control signal ctl_in, and an output end of the first multiplexers is connected to a corresponding input port of the input stage submodule, where M is an integer greater than 1.

The number of the first registers 121 connected between the top input pin IO/IN and the corresponding input port of the input stage submodule is selected by the first multiplexer 122 to adjust the register stage number of the input signal reaching each submodule 110, ensure that the input signal reaches each submodule 110 after the same time, and realize the time sequence convergence of the input signal.

Further, as shown in fig. 1 to 4, the chip circuit 100 of the present embodiment further includes at least two output stage pipeline modules 130, wherein each output port of the output stage sub-modules is connected to a different top-level output pin IO/OUT of the chip circuit 100 through a different output stage pipeline module 130, and the output stage pipeline module 130 is configured to adjust a time when an output signal of each sub-module 110 reaches each top-level output pin IO/OUT, so that each output signal reaches each top-level output pin IO/OUT through the same time.

Specifically, as shown in fig. 6, the output stage pipeline module 130 includes N second registers 131 and second multiplexers 132, each second register 131 is cascaded to a corresponding output port of the output stage sub-module to form (n+1) connection points, and is respectively connected to (n+1) selection ends of the second multiplexers 132, a control end of the second multiplexers 132 receives an output selection control signal ctl_out, and an output end is connected to a corresponding top-level output pin IO/OUT, where N is an integer greater than 1.

The number of the second registers 131 between the corresponding output ports of the output stage submodules and the corresponding top-level output pins IO/OUT is selected by the second multiplexer 132 to adjust the number of register stages through which the output signals of the corresponding submodules 110 reach the corresponding top-level output pins IO/OUT, so that the output signals of the submodules 110 reach the corresponding top-level output pins IO/OUT at the same time, and the output of each submodule 110 is observed conveniently.

It should be noted that fig. 1 to fig. 4 show different schematic structures corresponding to the number of the sub-modules 110 being three, in practice, schemes with the number of the sub-modules 110 being greater than 1 are feasible, such as 2,3,4, etc., and only the circuit structure needs to be adaptively adjusted; of course, fig. 5 and 6 are also examples only, and other numbers of registers greater than 1 are possible.

Correspondingly, the embodiment also provides a testing method of the chip circuit 100, which comprises the steps S1 and S2; the chip circuit 100 is realized by the circuit configuration described above. When testing the chip circuit 100, the following steps are performed.

Step S1: by configuring the number of first registers 121 in each input stage pipeline module 120, the input signal reaches each sub-module 110 over the same time.

For the case where the number of input stage sub-modules is one, taking fig. 1 and 2 as an example, when the first sub-module 110 is the input stage sub-module;

IN the first sub-module 110, an input signal introduced by the top input pin IO/IN passes through the first input stage pipeline module 120 (i.e., IP 1) and then reaches the compression unit 111 of the first sub-module 110; IN the second sub-module 110, an input signal introduced by the top input pin IO/IN sequentially passes through the second input stage pipeline module 120 (i.e., IP 2) and the first third register 112 (i.e., reg 31) IN the first sub-module 110, and then reaches the compression unit 111 of the second sub-module 110; IN the third sub-module 110, an input signal introduced by the top input pin IO/IN sequentially passes through the third input stage pipeline module 120 (i.e., IP 3), the second third register 112 (i.e., reg 32) IN the first sub-module 110, and the first third register 112 (i.e., reg 31) IN the second sub-module 110, and then reaches the compression unit 111 of the third sub-module 110;

At this time, the number of the first registers 121 connected between the top input pin IO/IN and the current input port IN1 of the first sub-module 110 IN the first input stage pipeline module 120 (i.e., IP 1) is configured to be two, so that the input signals reach the compression unit 111 of the first sub-module 110 through the two stages of registers IN total; configuring the number of first registers 121 IN the second input stage pipeline module 120 (i.e., IP 2) connected between the top input pin IO/IN and the second input port IN2 of the first sub-module 110 to be one, so that the input signals reach the compression unit 111 of the second sub-module 110 through the two stages of registers IN total; configuring zero number of first registers 121 IN the third input stage pipeline module 120 (i.e., IP 3) connected between the top input pin IO/IN and the three-stage input port IN3 of the first sub-module 110, so that the input signals reach the compression unit 111 of the third sub-module 110 through the two stages of registers IN total; in this manner, the input signal may arrive at each sub-module 110 at the same time.

For the case that the number of the input stage submodules is two, the principle of configuring the first registers 121 IN each input stage pipeline module 120 is the same, but each submodule 110 can perform input selection, each submodule 110 can perform input selection according to the configuration number of the first registers 121 IN each input stage pipeline module 120, and optimization of the path length of each submodule 110 to the top input pin IO/IN by selecting the input direction is realized so as to obtain a relatively shorter input path.

Taking fig. 3 and fig. 4 as an example, IN the first sub-module 110, through selection of the two-way selector 113, an input signal introduced by the top input pin IO/IN passes through the first input stage pipeline module 120 (i.e., IP 1) and then reaches the compression unit 111 of the first sub-module 110; IN the second sub-module 110, through selection of the two-way selector 113, an input signal introduced by the top input pin IO/IN sequentially passes through the second input stage pipeline module 120 (i.e., IP 2) and the first third register 112 (i.e., reg 31) IN the first sub-module 110, and then reaches the compression unit 111 of the second sub-module 110; IN the third sub-module 110, the input signal introduced by the top input pin IO/IN passes through the fourth input stage pipeline module 120 (i.e., IP 4) and reaches the compression unit 111 of the third sub-module 110 through the selection of the two-way selector 113;

At this time, the number of the first registers 121 connected between the top input pin IO/IN of the first input stage pipeline module 120 (i.e., IP 1) and the present stage input port IN11 of the first sub-module 110 is configured to be one, the number of the first registers 121 connected between the top input pin IO/IN of the second input stage pipeline module 120 (i.e., IP 2) and the second stage input port IN12 of the first sub-module 110 is configured to be zero, and the number of the first registers 121 connected between the top input pin IO/IN of the third input stage pipeline module 120 (i.e., IP 3) and the third stage input port IN33 of the third sub-module 110 is configured to be one, so that the input signal reaches the compression unit 111 of each sub-module 110 through the first stage registers IN total.

Of course, it is also possible that the input signal introduced by the top input pin IO/IN of the second sub-module 110 passes through the fifth input stage pipeline module 120 (i.e. IP 5) and the first third register 112 (i.e. Reg 31) IN the third sub-module 110 IN sequence, and then reaches the compression unit 111 of the second sub-module 110.

Step S2: by configuring the number of second registers 131 in each output stage pipeline module 130, the output signals of each sub-module 110 reach each top-level output pin IO/OUT at the same time.

The second register 131 in each output stage pipeline module 130 is configured in the same principle as the first register 121 in the input stage pipeline module 120, and will not be described herein.

It should be noted that, the configuration of the first register 121 IN the input stage pipeline module 120 is realized by inputting the selection control signal ctl_in to control the first multiplexer 122; the configuration of the second register 131 in the output stage pipeline module 130 is realized by outputting the selection control signal ctl_out to control the second multiplexer 132; of course, when the input selection is performed to each sub-module 110, the two-way selector 131 is controlled by the internal selection control signal.

Taking two input stage sub-modules as an example, when performing DFT test on each sub-module 110 multiplexed IN the chip circuit 100, the chip circuit 100 is enabled to enter a test mode, and input signals (such as scan chain data signals) are input through a top input pin IO/IN and transmitted IN a broadcast manner;

Each sub-module 110 selects a left side input or a right side input through a respective two-way selector 113 to obtain a relatively short input path, then, the corresponding input stage pipeline module 120 is configured through a corresponding first multiplexer 122 to adjust the register stage number, so that an input signal reaches the compression unit 111 of each sub-module 110 through registers with the same stage number, and finally, the corresponding output stage pipeline module 130 is configured through a corresponding second multiplexer 132 to adjust the register stage number, so that an output signal of each sub-module 110 reaches each top layer output pin IO/OUT through registers with the same stage number;

in this way, each sub-module 110 can utilize the same set of test vectors in the test mode, the DFT test of all sub-modules 110 can be completed through one test, and the test result of each sub-module 110 is observed according to the output of each top-layer output pin IO/OUT, so that the test time is saved, and the test cost is reduced.

In practical applications, when DFT testing is performed on each sub-module 110 multiplexed in the chip circuit 100, selection signals of the two-way selector 113, the first multiplexer 122, and the second multiplexer 132 can be generated together with the test vectors and transmitted to the chip circuit 100.

In summary, according to the chip circuit and the testing method thereof, the input signal reaches each sub-module by adjusting the time of the input signal through the input stage pipeline module, so as to realize the time sequence convergence of the input signal, and thus, the sub-modules multiplexed in the chip can be tested simultaneously by using the same set of testing vectors in a broadcasting mode, the testing time is saved, and the testing cost is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. The chip circuit is characterized by comprising at least two submodules and at least two input-stage pipeline modules;

2. The chip circuit of claim 1, wherein the number of input stage sub-modules is one, the number of output stage sub-modules is one, and the input stage sub-modules and the output stage sub-modules are the same or different sub-modules;

3. The chip circuit of claim 1, wherein the number of input stage sub-modules is two, the number of output stage sub-modules is one, and the output stage sub-modules and one of the input stage sub-modules are the same sub-modules;

4. The chip circuit of claim 1, wherein the input stage pipeline module comprises M first registers and first multiplexers, each of the first registers is cascaded to the top-level input pins to form (m+1) connection points, each of the first registers is connected to (m+1) selection terminals of the first multiplexers, a control terminal of the first multiplexers receives an input selection signal, and an output terminal of the first multiplexers is connected to a corresponding input port of the input stage sub-module, wherein M is an integer greater than 1.

5. The chip circuit of any one of claims 1-4, further comprising at least two output stage pipeline modules, wherein each output port of the output stage sub-modules is connected to a different top-level output pin of the chip circuit through a different one of the output stage pipeline modules, the output stage pipeline modules being configured to adjust a time for an output signal of each of the sub-modules to reach each of the top-level output pins.

6. The chip circuit of claim 5, wherein the output stage pipeline module includes N second registers and second multiplexers, each of the second registers is cascaded to a corresponding output port of the output stage sub-module to form (n+1) connection points, and each of the second registers is connected to (n+1) selection terminals of the second multiplexers, a control terminal of the second multiplexers receives an output selection signal, and an output terminal of the second multiplexers is connected to a corresponding top-level output pin, wherein N is an integer greater than 1.

7. The chip circuit of claim 1, wherein each of the sub-modules is connected via a third register via a feed-through.

8. A method of testing a chip circuit according to any one of claims 1-7, the method comprising:

9. The method of testing a chip circuit of claim 8, further comprising:

10. The method according to claim 8, wherein when the number of the input stage sub-modules is two, each of the sub-modules performs input selection according to the number of the first registers arranged in each of the input stage pipeline modules.