CN114237019B - Event-driven time-to-digital converter applied to array system and conversion method - Google Patents

Abstract

The invention discloses an event-driven time-to-digital converter applied to an array system and a conversion method. When a single pixel in the array detects a trigger signal in the effective period of an enable signal, the single pixel TDC starts to quantize, the low-section TDC latches the phase of a high-frequency clock signal, and the middle-section TDC and the high-section TDC record the number of edges of the high-frequency clock signal until the falling edge of the enable signal comes. The TDC data recorded by each pixel is selectively output by a parallel-serial data interface circuit under the coordination of a time sequence control circuit according to an address coding signal. Under the condition of effective data and consistent precision, lower average power consumption and smaller data volume output are realized.

Description

Event-driven time-to-digital converter applied to array system and conversion method

Technical Field

The invention relates to an event-driven time-to-digital converter applied to an array system, in particular to a circuit system with rare and random event characteristics, belonging to the technical field of time-to-digital converter circuit design.

Background

The time measurement is widely applied to various fields such as scientific research, engineering technology and the like, and plays a significant role in telecommunication, military aviation, atomic physics and the like. A Time-to-Digital Converter (TDC) is used for high-precision Time measurement, and converts a duration interval defined by two asynchronous signals into a Digital quantity for output. Compared with an Analog-to-Digital Converter (ADC), the TDC is used as an ADC applied in a specific situation, more conveniently realizes direct conversion of time signals, has unique advantages of simple structure, low hardware resource consumption, strong reliability and the like, and gradually replaces the ADC to become the best choice in the time measurement field. The TDC circuit is widely applied to various systems such as photon or particle flight time detection, pulse signal duration detection and the like, and the development of infrared sensing detection and temperature detection technologies is strongly supported.

The conventional array TDC generally performs time digital quantization on each pixel unit to generate a conversion result, and performs serial or parallel output on the conversion result of each pixel point in a row or column mode, and a measured signal generally has the characteristics of randomness and short-time density. The event-driven TDC circuit provided by the design solves the problem of limitation of data volume and power consumption to a certain extent, and has important significance for application of an array system.

Disclosure of Invention

The technical problem is as follows: compared with the traditional array TDC structure, the event-driven time-to-digital converter and the event-driven time-to-digital conversion method applied to the array system greatly reduce the output data volume, the transient power consumption and the overall average power consumption of a circuit on the premise of ensuring the data consistency.

The technical scheme is as follows: in order to achieve the above object, an event-driven time-to-digital converter applied to an array system of the present invention includes a single-pixel TDC circuit, a data selective output circuit, an address information encoding circuit, a timing control circuit, a synchronization signal circuit, and a parallel-to-serial data interface circuit; wherein: a single pixel in the pixel array system comprises a single pixel TDC circuit, a data selective output circuit and an address information coding circuit, wherein a data transmission starting mark and an end mark generated by a time sequence control circuit are connected with a synchronous signal circuit, a data transmission window signal generated by the time sequence control circuit is connected with a parallel-serial data interface circuit, and the output end of the pixel array system is connected with the parallel-serial data interface circuit. The global signal comprises an enable signal EN, a reset signal REC and clock signals HCK 1-HCK 4, and the clock signals are accessed into each pixel of the whole array through a symmetrical H-Tree type distribution network.

The time-to-digital conversion method of the event-driven time-to-digital converter applied to the array system comprises the following steps: when the single-pixel TDC circuit detects a trigger signal in the effective period of an enable signal EN, time interval quantization is started, and meanwhile, TDC quantized data of a pixel passing through an address information encoding circuit (3) are put into a data path by the data selective output circuit; if the pixel does not detect a trigger signal in the effective period of the enable signal EN, the data selective output circuit can shield the TDC quantized data of the pixel out of a data path;

when data is read out, the time sequence control circuit controls the data ports at different time periods, so that the data is uniformly and sequentially read out according to a preset sequence; the synchronous signal circuit generates a mark signal corresponding to the output data to ensure the accuracy of data reading, and finally, the TDC quantized data is serially read out in sequence through the parallel-serial data interface circuit.

When the single-pixel TDC circuit (1) detects a trigger signal in the effective period of an enable signal EN, a time quantization starting signal START signal jumps from 0 to 1; at this time, the rising edge of the START signal is used as a high-frequency clock enabling signal and a starting signal of the middle-stage and high-stage counting of the single-pixel TDC circuit, so that the middle-stage and high-stage TDC STARTs to count; meanwhile, the rising edge of the START signal is used as a latch signal of a low section, and the phase information of a high-frequency clock is recorded; enabling signal EN is as the count stop signal of middle section and high section, and specific process is: when the falling edge of the enable signal EN comes, the transmission gates of the middle section and the high section are turned off, and the high-frequency counting clock signals entering the TDC of the middle section and the high section are shielded; finally obtaining the arrival time of the trigger signal as T _measured ＝T _EN -T _TDC (ii) a Wherein T is _EN For the high time of enable signal EN, T _TDC The time quantized for the single pixel TDC.

The data selective output circuit comprises a control signal generation module and a data path switching circuit module, and realizes the function of selectively outputting TDC quantized data in pixels; in the effective period of the enable signal EN, if the pixel detects a trigger signal, when the falling edge of the enable signal EN arrives, the Control signal generated by the Control signal generation module is 1, and then the data path switching circuit module controls the quantized data of the TDC in the pixel to be accessed into the data path; if the trigger signal is not detected, when the falling edge of the enable signal EN arrives, the Control signal generated by the Control signal generation module is '0', and the TDC invalid quantized data in the pixel cannot enter the data path.

The address information coding circuit uses 1bit data in each single pixel circuit to represent whether the current pixel detects a trigger signal in the effective period of an enable signal EN; when data is read out, 1-bit data in all pixels in each row is read out in series, and because the number of pixels in each row is fixed, the pixel position of the TDC data is determined according to the correspondence between the address data in each row and the read TDC data, namely when the 1-bit data in each pixel is read out in series, the 1-bit data can carry address information.

The time sequence control circuit consists of a counter driven by a data reading clock LCK and a timing control logic, and enables different control signals in different time periods to enable data to be read out in a unified and ordered mode according to a preset sequence; when the counter counts a count value corresponding to the timing logic, the timing logic generates a corresponding narrow pulse signal to drive and reset a corresponding D flip-flop to form a corresponding time window interval for corresponding data reading and processing.

The synchronous signal circuit mainly provides a mark signal for identifying serial output DATA, and the circuit mainly generates three synchronous signals of a FRAME signal (FRAME), a WORD signal (WORD) and a BIT signal (BIT) corresponding to the output DATA, and combines the three synchronous signals with a DATA output (DATA _ OUT) to facilitate subsequent DATA processing; the correspondence of the BIT signal (BIT) to the WORD signal (WORD) depends on the number of BITs of data to be read out, the FRAME signal (FRAME) depends on the start (RC 1) and end (VCTRL _ LCK) signals of the transmission of a set of data, and the synchronization signal circuit can therefore be designed on the basis of the synchronization counter principle.

After receiving a data transmission window signal RCi generated by the time sequence control circuit, the parallel-serial data interface circuit generates a data transmission clock signal RC _ LCKi through carrying out AND operation on a clock LCK signal, wherein the signal is effective in a correspondingly set pulse width high level of the data transmission window RCi, and data on a corresponding path is normally transmitted at the moment; the low-frequency clock is shielded outside the pulse width high level of the RCi in the data transmission window, and the data transmission is forbidden; and the parallel-serial data interface circuit completes serial output of data under the control of the corresponding RC _ LCKi signal.

Has the advantages that: compared with the prior art, the event-driven TDC circuit provided by the invention has the following technical effects:

1. the invention is applied to a TDC array circuit with the characteristics of sparsity and randomness of signals, and only when a trigger signal is detected, the TDC is started to carry out time digital quantization, and the arrival time of the trigger signal is calculated according to the time digital quantization. Compared with the conventional scheme, after the system starts to work, all the pixel TDCs are started to work at the same time, and at this time, although the trigger signal is not detected in the EN effective period, the pixel TDCs still keep working in the whole enable signal high level period. In the scheme of the invention, if the trigger signal is not detected in the EN effective period, the middle and high sections of the pixel TDC do not work, so when the scheme is applied to a TDC array with the sparsity characteristic of the detected signal, the average power consumption of the system can be greatly reduced. Meanwhile, because all pixel units in each row do not detect the trigger signal at the same time and start to work, the transient power consumption and the transient voltage drop are also reduced to a certain extent.

2. The TDC array circuit is applied to TDC array circuits with the characteristics of sparseness and randomness of signals, data are selectively output, namely data generated by pixels which detect the trigger signals can be output, data generated by pixels which do not detect the trigger signals cannot be output, and the whole data reading time can be reduced to a certain extent to reduce the data reading power consumption.

Drawings

FIG. 1 is a schematic diagram of an event driven type time-to-digital converter applied to an array system according to the present invention;

among them are: the device comprises a single-pixel TDC circuit 1, a data selective output circuit 2, an address information encoding circuit 3, a time sequence control circuit 4, a synchronous signal circuit 5 and a parallel-serial data interface circuit 6.

FIG. 2 is a block diagram of a data path switching circuit;

FIG. 3 is a block diagram of an address information encoding circuit and a control signal generating module;

FIG. 4 is a diagram of a timing control circuit;

FIG. 5 is a circuit diagram of a synchronization signal;

FIG. 6 is a diagram of a parallel-to-serial data interface circuit;

FIG. 7 is a conventional array TDC operational timing;

figure 8 is the event driven array TDC operation timing of the present invention.

Detailed Description

The present invention will be further described with reference to the accompanying drawings.

As shown in fig. 1, the schematic diagram of the structure of an array-level event-driven TDC includes a single-pixel TDC circuit 1, a data selective output circuit 2, an address information encoding circuit 3, a timing control circuit 4, a synchronization signal circuit 5, and a parallel-serial data interface circuit 6; wherein: a single pixel in the pixel array system comprises a single pixel TDC circuit 1, a data selective output circuit 2 and an address information coding circuit 3, a data transmission start mark (RC 1) and an end mark (VCTRL _ LCK) generated by a time sequence control circuit 4 are connected with a synchronous signal circuit 5, a data transmission window signal (RCi) generated by the time sequence control circuit 4 is connected with a parallel-serial data interface circuit 6, and the output end of the pixel array system is connected with the parallel-serial data interface circuit 6. The global signal comprises an enable signal EN, a reset signal REC and clock signals HCK 1-HCK 4, and the clock signals are accessed into each pixel of the whole array through a symmetrical H-Tree type distribution network.

The time-to-digital conversion method of the event-driven time-to-digital converter applied to the array system is characterized in that when the single-pixel TDC circuit 1 detects a trigger signal in the effective period of an enable signal EN, time interval quantization is started, and meanwhile, the data selective output circuit 2 can put TDC quantized data of a pixel passing through an address information coding circuit 3 into a data path; if the pixel does not detect a trigger signal within the effective period of the enable signal EN, the data selective output circuit 2 will mask the TDC quantization data of the pixel out of the data path;

when data is read out, the time sequence control circuit 4 controls the data ports at different time periods, so that the data is uniformly and sequentially read out according to a preset sequence; the synchronous signal circuit 5 generates a mark signal corresponding to the output data to ensure the accuracy of data reading, and finally, the TDC quantized data is serially read out in sequence through the parallel-serial data interface circuit 6.

Enabling signals EN, reset signals REC and clock signals HCK 1-HCK 4 enter each pixel of the whole array through an H tree; a TDC module is arranged in each pixel, and the counting mode of the TDC module is event-driven counting; during the period that the enable signal EN is effective and after the trigger signal is detected, the TDC starts to work and is a pseudo-random number counter; during data reading, the TDC module is switched to a left shift register, and TDC quantized data are read in series; judging whether a trigger signal arrives in the effective period of the enable signal through a circuit module built in each pixel, and if the trigger signal arrives, entering data of the pixel into a data path and outputting the data in series; if no trigger signal arrives, the data of the pixel cannot enter the data path and cannot be output; when data is read out, the data is output by sharing one data port through time division multiplexing.

In order to realize the function of 'data selective output', the single pixel circuit designed by the invention comprises a TDC circuit, and a circuit module for controlling the switching of a data path and a circuit module for generating data carrying address information are added in the single pixel circuit. The driving counting mode is adopted, so that the single-pixel TDC circuit has the main functions of performing coarse counting and fine counting on complementary time of time to be measured in one period, latching quantized data and finishing the work of data output under the coordination of a system control signal.

The actually measured trigger signal arrival times are: t is _measured ＝T _EN -T _TDC 。

Wherein T is _EN For the high time of the enable signal (EN), T _TDC Is the time of quantization of the single pixel TDC.

The data selective output circuit module comprises a data path switching circuit module and a control signal generation module, so that a judgment circuit is designed, and whether the trigger signal is detected in the effective period of the enable signal EN is used as the judgment basis for judging whether the pixel data is effective.

The DATA path switching circuit is shown in fig. 2, where the red line represents the path through which DATA flows, and DATA represents a TDC connected to a shift register and carrying quantized DATA when DATA is read out. Pixels that do not detect a trigger signal will not be in the data path even if there is invalid data; the data in the pixel where the trigger signal is detected is output through the data path for subsequent data processing.

The specific functions of the control signal generation module in fig. 3 are: in the period of validity of the enable signal, if the pixel detects the trigger signal, when the EN falling edge arrives, the Control signal generated by the circuit is '1'; if the trigger signal is not detected, the Control signal generated by the circuit is "0" when the EN falling edge arrives. And further controlling whether the data path switching circuit accesses the TDC quantized data into the data path.

Since not all data is read out in this readout scheme, address data is needed to determine the pixel location corresponding to the current data for subsequent operations. 1-bit data is used in each single pixel circuit to characterize whether the current pixel detects a trigger signal during the period that the enable signal is active. When data are read in series, data close to the outer side (the side where the data reading port is located) of the array are read first, and according to the characteristic of data series reading, address data in each row correspond to the read TDC data, the pixel position of the read TDC data is determined, namely when 1-bit data in each pixel are read in series, the 1-bit data carry address information.

The address information encoding circuit in fig. 3 can implement the above functions, and the specific working flow is as follows:

under the action of the global RESET signal, the data output Q ends of all D triggers in the circuit module are RESET to be 0. When a trigger signal arrives in the enabled signal active period (EN is high level), the data output end a of the D flip-flop DFF1 jumps to "1", and the selector MUX1 connects a to the data input D end of the DFF3 under the control of EN _ DELAY; will be provided with

And the DATA _ OUT DATA is connected to the clock terminals of the DFF2 and DFF3, and when the EN falling edge arrives, the DATA _ OUT DATA is changed into 1, which indicates that the current pixel detects a trigger signal in the period when the enable signal is effective. When the trigger signal is not detected during the active period of the enable signal, the DATA output terminal a of DFF1 is maintained at "0", and when the EN falling edge arrives, the DATA _ OUT DATA is 0, indicating that the current pixel does not detect the trigger signal during the active period of the enable signal. When the low level of the signal EN _ DELAY comes, MUX1 connects in series the D flip-flops (DFF 3 in fig. 3) in all the single-pixel circuits in this row, which generate signals indicating whether the trigger signal is detected, into a shift register, and waits for a valid read signal to read out the 1-bit data in all the single pixels in this row in series.

The timing control circuit shown in fig. 4 enables different control signals in different time periods, so that data are uniformly and sequentially read out according to a preset sequence. The time sequence control circuit is composed of a counter driven by a data reading clock LCK and a timing control logic, a binary asynchronous adder is adopted to count the period of the data reading clock LCK, corresponding data transmission windows RCi (i =1,2,3.. N) are generated by the timing logic to select and control the array, and then RCi signals are further processed to drive address data and TDC quantized data in each pixel sub-array to be read out in a set sequence in the high-level pulse width of the corresponding RCi signals. Taking an 8 × 8 system array as an example, a 4-path parallel readout mode is adopted, the 8 × 8 array is divided into 4 8 × 2 sub-arrays, and each sub-array shares 16 pixels to share one data output I/O port for data transmission. In each 8 × 2 sub-array, each row of data is output in series by the row selection control and parallel-serial output interface circuit, and the data of the pixels close to the output pins are always read out first. The specific working process is as follows:

when the counter counts a count value corresponding to the timing logic, the timing logic generates a corresponding narrow pulse signal to drive and reset a corresponding D trigger, and 4 time window intervals formed are RC1 (P1-P2), RC2 (P2-P3), RC3 (P3-P4) and RC4 (P4-P5). The counting value limits the working time of the system, and the system needs to complete the operations of circuit reset, trigger signal detection, counting and the like in the interval of 0 to P1. The time window intervals RC1 and RC2 are time windows for reading the first row of address information and the first row of TDC quantized data, respectively, and the RC2 window interval completes a pixel data transmission operation for detecting a trigger signal in one row of pixels. The window intervals of RC3 and RC4 are the same as RC1 and RC2, respectively, for reading the corresponding data of the second row of pixels.

The synchronous signal circuit mainly provides a flag signal for identifying serial output data, and a schematic diagram of the circuit structure is shown in fig. 5. The module mainly generates three synchronous signals of a FRAME signal (FRAME), a WORD signal (WORD) and a BIT signal (BIT) corresponding to output DATA, and combines the three synchronous signals with a DATA output (DATA _ OUT) to facilitate subsequent DATA processing. The RC1 and VCTRL _ LCK signals are provided by a time sequence control module, the output BIT signal is synchronously generated by the LCK signal, the corresponding relation between BIT and WORD depends on the BIT number of data to be read out, the output address data and TDC quantized data are respectively marked by a dual-mode counter, and the FRAME signal depends on a start (RC 1) and an end (VCTRL _ LCK) signal for transmitting a group of data, so that the synchronous signal module is designed and realized based on the principle of a synchronous counter.

Fig. 6 shows a parallel-serial data interface module, which also takes an 8 × 8 system array as an example, under the control of the timing control circuit shown in fig. 4, RC1 to RC4 and LCK generate data transmission clock signals RC _ LCK1, RC _ LCK2, RC _ LCK3 and RC _ LCK4 through and operation. The RC _ LCKi signal is effective in the high level of the correspondingly set RCi pulse width, and data on a corresponding path are normally transmitted at the moment; and the low frequency clock is masked out of the high level pulse width of the RCi, and data transmission is disabled. And the parallel-serial data interface circuit completes serial output of data under the control of the corresponding RC _ LCKi signal.

The specific circuit working process is as follows: when RC1 is "1", RC _ LCK1 is an effective low-frequency clock, and other RC _ LCKi are all "0", and at this time, address data of the first row of pixels (denoted by A1 in the figure) is transmitted; when RC2 is 1, RC _ LCK2 is an effective low-frequency clock, and TDC quantized data of the pixels in the first row are transmitted at the moment; similarly, RC3 and RC4 respectively control the transmission of the address data and TDC quantized data of the second row of pixels; what is finally seen in the output pin OUT is the sequential serial readout of the address data and the TDC quantization data in 2 rows of pixels.

After the system is reset, the rising edge of an enable signal EN of the traditional array TDC arrives, all pixels of the TDC start timing, and when a pixel point detects a trigger signal, a corresponding pixel can generate a STOP signal to STOP timing and store TDC data. If the pixel point does not detect the trigger signal in the whole EN signal high level period, the TDC counts up the whole gating period and stores the data. When data are output, timing data of all pixel points are sequentially output in a serial mode, but the data which are counted in the whole gating period are invalid data and need to be removed through an algorithm in a later period. The problems with the conventional array TDC are: (1) After the rising edge of the enable signal EN of the circuit arrives, all pixel TDC starts to work, so that the transient power consumption of the circuit is overlarge, and the power supply voltage is insufficient. (2) The pixel TDC which does not detect the trigger signal continuously works in the whole gating period, and especially for a system with sparse trigger signals, the average power consumption of the system is large; (3) The system architecture has large output data volume, all data need to be output in series, and for a system with sparse trigger signals, a large amount of invalid data exist in the output total data.

The event-driven time-to-digital converter applied to the array system well overcomes the defects in the traditional scheme, and due to the fact that the gating time of the enable signal EN is fixed, after the trigger signal is detected, a START signal generated by a pixel is used for driving a TDC to START timing, timing is stopped when the falling edge of the EN signal arrives, the time between the arrival time of the trigger signal and the EN gating end time is quantized, and the time when the EN gates and the TDC quantization time are differed, so that the arrival time of the trigger signal can be obtained. The TDC low section latches the high frequency clock signal phase, and the middle and high sections serve as counting functions. The data output is to output the address information of the pixel of the detected trigger signal and then sequentially output the effective data of the pixel TDC. Time-driven TDCs compare to conventional solutions: (1) The problem of power consumption caused by the fact that after the rising edge of the enable signal EN arrives, all pixel TDC starts to work is solved, the TDC only starts to work after the trigger signal is detected, and due to the uncertainty of the trigger signal, the low-section TDC is used for latching the phase of the clock signal to ensure the precision. (2) The output of a large amount of invalid data is avoided, but because the valid data are not continuously arranged, the address coding processing needs to be carried out on the pixels according to whether the trigger signal is detected in each row, the first data to be output is the address data, the valid data are sequentially output, and the time when the trigger signal reaches each pixel point can be restored through the combination of the address data and the valid data.

The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention, and such modifications and adaptations are intended to be within the scope of the invention.

Claims (8)

1. An event-driven time-to-digital converter applied to an array system is characterized by comprising a single-pixel TDC circuit (1), a data selective output circuit (2), an address information encoding circuit (3), a time sequence control circuit (4), a synchronous signal circuit (5) and a parallel-serial data interface circuit (6); wherein: a single pixel in the pixel array system comprises a single pixel TDC circuit (1), a data selective output circuit (2) and an address information coding circuit (3), a data transmission start mark RC1 and an end mark VCTRL _ LCK generated by a time sequence control circuit (4) are connected with a synchronous signal circuit (5), a data transmission window signal RCi generated by the time sequence control circuit (4) is connected with a parallel-serial data interface circuit (6), the output end of the pixel array system is connected with the parallel-serial data interface circuit (6), a global signal comprises an enable signal EN, a reset signal REC and clock signals HCK 1-HCK 4, and the enable signal EN, the reset signal REC and the clock signals HCK 1-HCK 4 are connected into each pixel of the whole array through a symmetrical H-Tree type distribution network; the data selective output circuit (2) comprises a control signal generation module and a data path switching circuit module, and is used for judging whether the enabling signal EN detects a trigger signal in the effective period as the basis for judging whether the pixel data is effective or not and controlling the data path switching circuit to connect TDC quantized data into a data path or not.

2. A time-to-digital conversion method for an event-driven time-to-digital converter applied to an array system according to claim 1, wherein the single-pixel TDC circuit (1) starts time interval quantization when detecting a trigger signal during the period of enabling the enable signal EN, and the data selective output circuit (2) puts the TDC quantized data of the pixel passing through the address information encoding circuit (3) into the data path; if the pixel does not detect a trigger signal in the effective period of the enable signal EN, the data selective output circuit (2) masks the TDC quantized data of the pixel out of a data path;

when data are read out, the time sequence control circuit (4) controls the data ports at different time periods, so that the data are uniformly and sequentially read out according to a preset sequence; and finally, the TDC quantized data is serially read out in sequence through the parallel-serial data interface circuit (6).

3. The time-to-digital conversion method of event-driven type time-to-digital converter according to claim 2, wherein the single-pixel TDC circuit (1) is set on the effective period of the enable signal ENWhen the trigger signal is detected in the time interval, the START signal of the time quantization starting signal jumps from 0 to 1; at the moment, the rising edge of the START signal is used as a high-frequency clock enabling signal and a starting signal of the middle-stage and high-stage counting of the single-pixel TDC circuit (1), so that the middle-stage and high-stage TDC STARTs to count; meanwhile, the rising edge of the START signal is used as a latch signal of a low section, and the phase information of a high-frequency clock is recorded; the enabling signal EN is used as a counting stop signal of the middle section and the high section, and the specific process is as follows: when the falling edge of the enable signal EN comes, the transmission gates of the middle section and the high section are turned off, and the high-frequency counting clock signals entering the TDC of the middle section and the high section are shielded; finally obtaining the arrival time of the trigger signal as T _measured ＝T _EN -T _TDC (ii) a Wherein T is _EN For the high time of the enable signal EN, T _TDC The time quantized for the single pixel TDC.

4. The time-to-digital conversion method of event-driven type time-to-digital converter according to claim 2, wherein the data selective output circuit (2) comprises a control signal generation module and a data path switching circuit module, and implements the function of selectively outputting the TDC quantized data in the pixel; in the effective period of the enable signal EN, if the pixel detects a trigger signal, when the falling edge of the enable signal EN arrives, the Control signal generated by the Control signal generation module is 1, and then the data path switching circuit module controls the quantized data of the TDC in the pixel to be accessed into the data path; if the trigger signal is not detected, when the falling edge of the enable signal EN arrives, the Control signal generated by the Control signal generation module is '0', and the TDC invalid quantized data in the pixel cannot enter the data path.

5. The time-to-digital conversion method of an event driven type time-to-digital converter according to claim 2, wherein the address information coding circuit (3) uses 1bit data in each single pixel circuit to characterize whether the current pixel detects a trigger signal within a period during which the enable signal EN is valid; when data is read out, 1-bit data in all pixels in each row is read out in series, and because the number of pixels in each row is fixed, the pixel position of the TDC data is determined according to the correspondence between the address data in each row and the read TDC data, namely when the 1-bit data in each pixel is read out in series, the 1-bit data can carry address information.

6. The time-to-digital conversion method of event-driven type time-to-digital converter according to claim 2, wherein the timing control circuit (4) is composed of a counter driven by a data readout clock LCK and a timing control logic, and by enabling different control signals in different time periods, data are uniformly and sequentially read out in a preset order; when the counter counts a count value corresponding to the timing logic, the timing logic generates a corresponding narrow pulse signal to drive and reset a corresponding D flip-flop to form a corresponding time window interval for corresponding data reading and processing.

7. The time-to-digital conversion method for event-driven time-to-digital converter according to claim 2, characterized in that said synchronization signal circuit (5) mainly provides a flag signal for identifying serial output DATA, and generates three synchronization signals of FRAME signal FRAME, WORD signal WORD and BIT signal BIT corresponding to the output DATA, in combination with DATA output DATA _ OUT, for facilitating subsequent DATA processing; the BIT signal BIT corresponds to the WORD signal WORD in dependence on the number of BITs of the data to be read out, the FRAME signal FRAME depends on the start RC1 and end VCTRL _ LCK signals for transmitting a set of data, and the synchronization signal circuit (5) can thus be designed on the basis of the synchronization counter principle.

8. The time-to-digital conversion method of the event-driven time-to-digital converter according to claim 2, wherein the parallel-serial data interface circuit (6) generates a data transmission clock signal RC _ LCKi by performing an and operation with a clock LCK signal after receiving a data transmission window signal RCi generated by the timing control circuit, the signal being valid within a correspondingly set pulse width high level of the data transmission window signal RCi, and data on a corresponding path is normally transmitted at this time; the low-frequency clock is shielded outside the high level of the pulse width of the data transmission window signal RCi, and the data transmission is forbidden; and the parallel-serial data interface circuit completes serial output of data under the control of the corresponding RC _ LCKi signal.

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