CN114460830A - Novel time-to-digital conversion integrated circuit - Google Patents

Abstract

The invention provides a novel time-to-digital conversion integrated circuit, which is characterized in that: the device consists of an external input starting signal (1), an external input stopping signal (2), an external input reference clock signal (3), a starting signal port (4), a stopping signal port (5), a reference clock signal port (6), a delay phase-locked loop module (7), a global counter (9), a starting signal counting module (10), a stopping signal counting module (11) and a reading circuit (12); the invention relates to a novel time-to-digital conversion integrated circuit, which adopts a structure of recycling a small amount of time-to-digital conversion circuits (TDCs), solves the problem of large area of precision improvement by using an array TDC, can be widely applied to laser radar and remote sensing imaging technology, and belongs to the technical field of integrated circuits.

Description

Novel time-to-digital conversion integrated circuit

Technical Field

The invention relates to a novel time-to-digital conversion integrated circuit, which can be widely applied to laser radar and remote sensing imaging technology and belongs to the technical field of integrated circuits and ranging.

Background

The laser ranging chip as a chip system capable of converting analog time into digital sensor has been widely applied to the fields of laser radar, remote sensing imaging, space mission, unmanned driving, deep sea detection and the like. At present, the research heat of laser ranging chips is continuously improved, and the laser ranging chips are developing towards the directions of high integration, large dynamic range and high precision; since the speed V of light propagating in the air is 3x108m/S and the principle of laser ranging measurement is S-V T/2, an accurate distance can be obtained as long as an accurate time T is obtained, and thus, it can be seen that the performance of determining the large dynamic range and the high accuracy of the laser ranging chip is mainly a time-to-digital conversion (TDC) circuit therein, and therefore, it is of great significance to develop a TDC with a large dynamic range and high accuracy.

Villa et al published a paper SPAD Smart Pixel for Time-of-Flight and Time-corrected Single-Photon Counting measures in 2012, and a TDC in the ranging chip adopts an interpolation and flash type structure based on a Delay Locked Loop (DLL) clock circuit to realize the characteristic of large dynamic range; niclass et al published a paper A100-m Range 10-Frame/s 34096-Pixel Time-of-Flight Depth Sensor in 0.18-m CMOS in 2013, and the TDC in the ranging chip adopts a flash type structure based on a phase-locked loop (PLL) clock circuit to realize the characteristic of large dynamic Range; federaca A.Villa et al published a paper A High-Linearity,17 ps Precision Time-to-Digital Converter Based on a Single-Stage Vernier Delay Fine interpolaration in 2013, and the TDC adopts a Single-Stage Vernier Delay ring structure Based on an Interpolation method to reduce errors caused by mismatch of devices, thereby realizing large dynamic range and High-Precision measurement; wujin et al developed a three-stage time-to-digital conversion circuit (Chinese patent: CN201610176977.8) based on a phase-locked loop and a low-power-consumption high-precision array time-to-digital conversion circuit (Chinese patent: CN201610901004.6) based on a multiple VCO in 2016, and the TDC of the circuit is based on a PLL and a DLL clock respectively, and adopts a multi-stage structure to realize the characteristics of large dynamic range and high resolution; a TDC circuit (CN201810712395.6) based on a tap dynamically adjustable carry chain fine time interpolation delay line realizes the characteristics of large dynamic range and high resolution based on the output of a high-frequency clock and by using an adjustable carry delay chain; the TDC measurement structure described above is based on the clock phase output of DLL or PLL, and each clock phase output of DLL and PLL cannot achieve a complete phase difference coincidence, and there is no way to control in which time phase the START measurement signal and the STOP measurement signal are measured during the actual measurement, resulting in a random error introduced into the measurement result, and thus high-precision measurement cannot be achieved.

To overcome the above problems, Jansson et al published a paper Enhancing Nutt-Based Time-to-Digital Converter Performance with Internal systematical conversion in 2019, whichThe TDC is based on Nutt and adopts an internal system averaging method, and minimizes an interpolation error by sampling irrelevant errors for multiple times, so that the measurement precision is improved under the condition of a large dynamic range; pekka

In 2019, a paper 256 × TDC Array With Cyclic Interpolators Based on Calibration-Free 2 × Time Amplifier was published, the TDC combines Cyclic interpolation and Time amplification, and uses a TDC Array to continuously measure a single Time interval for multiple times, thereby realizing high-precision measurement in a large dynamic range;

however, the above techniques have the following disadvantages: 1. the effective utilization rate of a plurality of TDC channels is insufficient when the TDC array is used for improving the system precision, 2, the system area is large when the TDC array is used for improving the system precision, which is not beneficial to being applied to an actual ranging or imaging system.

The invention discloses a time-to-digital conversion circuit with large dynamic range and high precision, wherein a TDC circuit in the system adopts a method of averaging in a circulating system, 1, a few TDC channels are used for replacing a TDC array to carry out system averaging at a single time interval, and the whole chip area is reduced, 2, meanwhile, due to the circulating method, the mismatching of devices is reduced, so that the measurement precision of the system is improved again, and 3, the time-to-digital conversion with high precision and large dynamic range is realized while the integration degree is high.

Disclosure of Invention

The invention relates to a novel time-to-digital conversion integrated circuit which can be widely applied to laser radar and remote sensing imaging technologies and belongs to the technical field of integrated circuits.

The invention is realized by the following steps: the device consists of an external input starting signal (1), an external input stopping signal (2), an external input reference clock signal (3), a starting signal port (4), a stopping signal port (5), a reference clock signal port (6), a delay phase-locked loop module (7), a global counter (9), a starting signal counting module (10), a stopping signal counting module (11) and a reading circuit (12); the delay phase-locked loop module (7) consists of a high-level delay phase-locked loop (27) and a low-level delay phase-locked loop (28), the starting signal counting module (10) consists of a starting signal middle counter (13) and a starting signal low counter array (14), and the stopping signal counting module (11) consists of a stopping signal middle counter (15) and a stopping signal low counter array (16); the internal structure connection, the working principle and the output form of the stop signal counting module (11) are the same as those of the start signal counting module (10); an external input reference clock signal (3) is transmitted to a reference clock input end 1 of a delay phase-locked loop module (7) and a reference clock input end 2 of a global counter (9) through a reference clock signal port (6), a plurality of clock output ends 1 of the delay phase-locked loop module (7) output a plurality of multiphase clock signals with equal phase difference, the delay phase-locked loop module (7) is connected to a clock input end 1 of the start signal counting module (10) and a clock input end 2 of the stop signal counting module (11), a control voltage 1 output end outputs a control voltage 1 to a first input end of the start signal counting module (10) and a first input end of the stop counting module (11), and a control voltage 2 output end outputs a control voltage 2 to a second input end of the start signal counting module (10) and a second input end of the stop signal counting module (11); an external input start signal (1) passes through a start signal port (4) to a third input end of a start signal counting module (10) and a start counting input end of a global counter (9), when the external input start signal (1) generates a pulse signal, a rising edge of the pulse signal triggers the global counter (9) to start counting clock rising edges of an external input reference clock signal (3), the rising edge of the pulse signal also triggers the start signal counting module (10) to enable an enable pulse signal to appear in a period, each enable pulse signal rising edge appears between rising edges of all adjacent multiphase clock signals of a high-level delay phase-locked loop (7) in sequence, a phase difference between each enable pulse signal rising edge and a reference clock signal rising edge is measured and converted into a digital signal, and the obtained phase difference is a middle section time interval and a low section time interval of the start signal, the obtained digital signal is output to a multiplex input end 1 of a reading circuit (12) through a digital signal output end of a starting signal counting module (10); an external input stop signal (2) passes through a stop signal port (5) to a third input end of a stop signal counting module (11) and a stop counting input end of a global counter (9), when the external input stop signal (2) generates a pulse signal, a rising edge of the pulse signal triggers the global counter (9) to output a counting result of the global counter (9) at the moment, the obtained counting result is a high-stage time interval, the counting result is output from an output end of the global counter (9) to a multiplexing input end 2 of a reading circuit (12) in the form of a digital signal, and the rising edge of the pulse signal also triggers the stop signal counting module (11) to output the digital signal representing the phase difference to a multiplexing input end 3 of the reading circuit (12), namely the middle-stage time interval and the low-stage time interval of the stop signal; finally, the measured digital signal is serially output through a readout circuit (12), so that the time interval between the rising edge of the pulse signal of the external input start signal (1) and the rising edge of the pulse signal of the external input stop signal (2) is measured and output in the form of a digital signal.

The time interval between the rising edge of the pulse signal of the external input starting signal (1) and the rising edge of the pulse signal of the external input stopping signal (2) consists of a high-stage time interval of a global counter (9), a plurality of middle-stage time intervals and low-stage time intervals generated by a starting signal counting module (10), and a plurality of middle-stage time intervals and low-stage time intervals generated by a stopping signal counting module (11); averaging a plurality of middle-segment signal time intervals and low-segment time intervals generated by the start signal counting module (10) to obtain more accurate middle-segment signal time intervals and low-segment time intervals of the start signal, and similarly, obtaining more accurate middle-segment time intervals and low-segment time intervals of the stop signal by the stop signal counting module (11); the total time interval is the high interval plus the more accurate start signal mid-range time interval and low interval minus the more accurate stop signal mid-range time interval and low interval.

The reference clock signal input end 1 of the time delay phase-locked loop module (7) is connected with an advanced time delay phase-locked loop (27), a plurality of clock phase signals of the advanced time delay phase-locked loop (27) are connected with a plurality of clock output ends 1 of the time delay phase-locked loop module (7), the advanced time delay phase-locked loop (27) outputs a control voltage 1 to the control voltage 1 output end of the time delay phase-locked loop module (7), the low-level time delay phase-locked loop (28) outputs a control voltage 2 to the control voltage 2 output end of the time delay phase-locked loop module (7), and the clock phase input end 1 and the clock phase input end 2 of the low-level time delay phase-locked loop (28) are respectively connected with the last two clock phase signals output by the plurality of clock phase signals in the advanced time delay phase-locked loop (27); the advanced delay phase-locked loop (27) consists of a coarse single-ended voltage-controlled delay chain, a phase frequency detector, a charge pump and a low-pass filter, and has the functions that the advanced delay phase-locked loop (27) receives a reference clock signal of a reference clock input end 3 of the advanced delay phase-locked loop, and the advanced delay phase-locked loop (1) provides a stable control voltage 1 and a plurality of clock phase signals which do not change along with the process, the power supply voltage and the temperature under the action of a phase-locked loop of the advanced delay phase-locked loop; the low-level delay phase-locked loop (28) consists of a thin single-ended voltage-controlled delay chain, a phase frequency detector, a charge pump and a low-pass filter, and has the functions that the low-level delay phase-locked loop (28) receives clock phase signals of a clock phase input end 1 and a clock phase input end 2, and the low-level delay phase-locked loop (28) provides stable control voltage 2 which does not change along with the process, the power supply voltage and the temperature through the action of a phase-locked loop of the low-level delay phase-locked loop.

The starting signal middle counter (13) consists of a cycle controller 1 and an interpolator 1, the cycle controller 1 of the starting signal middle counter (13) consists of a pulse generator, a single-ended voltage-controlled delay chain, a multilevel counter, a decoder and a digital logic gate, and the cycle controller 1 has the functions of outputting periodic enable pulse signals to the measurement starting input ends of a plurality of starting signal low-stage counters in a starting signal low-stage counter array (14), outputting enable control signals to control the plurality of starting signal low-stage counters in the starting signal low-stage counter array (14), respectively connecting a plurality of output signals in the enable control signals to the enabling input ends of the plurality of starting signal low-stage counters, and enabling the plurality of starting signal low-stage counters to receive the pulse signals in order; the input of the pulse generator is connected with the third input end of the start signal counting module (10), the output of the pulse generator is connected with the single-ended voltage-controlled delay chain, the single-ended voltage-controlled delay chain is controlled by a control voltage 1, the input of the pulse generator is respectively connected with one port of the AND gate and the input of the delay unit, the output of the delay unit is connected with the other port of the AND gate after passing through the phase inverter, and the output port of the AND gate is the output port of the pulse generator; when an external input start signal (1) generates a pulse signal, the rising edge of the pulse signal triggers a pulse generator, the pulse generator can generate a pulse signal at the output, the pulse signal output by the pulse generator is input to one input end of an exclusive-OR gate, the output signal of the exclusive-OR gate generates the same pulse signal and is input to the input end of a single-ended voltage-controlled delay chain, the single-ended voltage-controlled delay chain is controlled by a control voltage 1, through the delay time of the single-ended voltage-controlled delay chain, the output of the single-ended voltage-controlled delay chain generates a first enable pulse signal, the enable pulse signal is connected with an NMOS tube and is input to the other port of the exclusive-OR gate, the output signal of the exclusive-OR gate is at a low level, the enable pulse signal enables the output signal of the exclusive-OR gate to generate the same pulse signal, the single-ended voltage-controlled delay chain enables the output of the single-ended voltage-controlled delay chain to generate a second enable pulse signal, repeating the steps to enable the circulation controller 1 to output a plurality of enable pulse signals; a plurality of enabling pulse signals are input to the measurement input ends of a multi-system counter and a start signal low-stage counter array (14), the rising edge of each enabling pulse signal enables the multi-system counter to count by one, when the multi-system counter counts and is full, the multi-system counter outputs a reset signal, the high level of the reset signal is input to the grid of an NMOS tube to stop circulation, a single-ended voltage-controlled delay chain does not output the enabling pulse signals any more, a plurality of low level outputs of the multi-system counter are connected to a decoder, the decoder obtains a thermal unique code output through decoding, the thermal unique code output is an enabling control signal, the enabling input end is in the high level and works normally, the enabling input end does not work at the low level, when the counter counts and is added, the output signal of the decoder is shifted to the high level by one bit, the enabling control signal controls the next start signal low-stage counter to receive the enabling pulse signals, and by the mode, the start signal low counter array (14) can be enabled to output a plurality of middle time intervals and low time intervals respectively; the interpolator 1 consists of an arbiter array, the input end of IN1 of each arbiter IN the arbiter array is connected with an enable pulse signal, the input end of IN2 is connected with the clock input end 1 of a start signal counting module (10), and the output of each arbiter is input to the storage input end of each start signal low-stage counter IN a start signal low-stage counter array (14); the function of the arbiter is to identify which input port rising edge of the two input ends of the arbiter arrives faster, when the enable pulse signal arrives preferentially than the clock step signal, the arbiter outputs high level, otherwise outputs low level; when the rising edge of the enable pulse signal triggers the interpolator 1, the arbiter array of the interpolator 1 will output as the function of the arbiter and the outputs of all the arbiters in the arbiter array will be input to the storage input of each start signal low segment counter in the start signal low segment counter array (14).

The start signal low segment counter array (14) is composed of a plurality of start signal low segment counters; each starting signal low-stage counter consists of a synchronous circuit 1, a fine computing circuit 1 and a register 1; each starting signal low-stage counter in the starting signal low-stage counter array (14) consists of a synchronous circuit 1, a fine computing circuit 1 and a register 1; the function is to obtain the low-segment time interval and send it to the fine counting circuit for measurement, wherein the synchronous circuit 1 is composed of two multi-input N-type pseudo-OR gates and an arbitrator, the gates of all NMOS tubes of one multi-input N-type pseudo-OR gate are connected to the synchronous signal input end of the START signal low-segment counter, the multi-input N-type pseudo-OR gates output STOP signals, the gate of one NMOS tube of the other multi-input N-type pseudo-OR gate is connected with the output of the arbitrator, the other inputs are connected with the ground, the IN1 input of the arbitrator is connected with the output of the enable pulse signal, the IN2 is connected with the ground, the multi-input N-type pseudo-OR gates output START signals, the START signals represent the rising edge of the enable pulse signal, the STOP signals represent the rising edge of the adjacent multiphase clock signal, the time interval between the rising edges of the two signals is the low-segment time interval, the START signals and the STOP signals output by the two multi-input N-type pseudo-OR gates are respectively connected to the T input end and STOP input end of the fine counting circuit, the PMOS tubes of the two multi-input N-type pseudo-OR gates are connected with an enable input end; the fine calculation circuit comprises a pulse generator 1, a pulse generator 2, a vernier delay ring 1, a vernier delay ring 2, a D trigger and a counter, wherein the vernier delay ring 1 comprises the pulse generator 1, an exclusive-OR gate 1, a single-ended voltage-controlled delay unit 1 and a digital logic gate, the single-ended voltage-controlled delay unit 1 comprises 1 single-ended voltage-controlled delay unit controlled by a controlled voltage 2, the vernier delay ring 2 comprises the pulse generator 2, the exclusive-OR gate 2, the single-ended voltage-controlled delay unit 2 and the digital logic gate, and the single-ended voltage-controlled delay unit 2 comprises 2 single-ended voltage-controlled delay units controlled by the controlled voltage 2; the inner structure connection and the working principle of the vernier delay ring 1 are the same as those of the vernier delay ring 2; the input ends of a pulse generator 1 and a pulse generator 2 are respectively connected with a START input end and a STOP input end, the input ends of a vernier delay ring 1 and a vernier delay ring 2 are respectively connected with the output ends of the pulse generator 1 and the pulse generator 2, the output end of the pulse generator 1 is connected with one port of an exclusive-OR gate 1, the output of the exclusive-OR gate 1 is input into a single-ended voltage-controlled delay unit 1, the output of the single-ended voltage-controlled delay unit 1 is connected into one port of an AND gate 1, the output of the AND gate 1 is connected into a counter and is connected into the other input of the exclusive-OR gate 1, meanwhile, the D input end of the D trigger is connected with the output of the exclusive-OR gate 1, the clock input end of the D trigger is connected with the output of the exclusive-OR gate 2, the output Q of the D trigger is connected to the other input end of the AND gate 1 and the AND gate 2, and the digital signal output by the counter is in a low-period time interval and is input to the multiplexing end 3 of the reading circuit (112); the register 1 is composed of a D trigger array device, a plurality of inputs of an encoder are connected with the output of an arbiter array in the interpolator 1, a plurality of outputs of the encoder are connected with D ends of all D trigger devices in the D trigger array, and CLK ends of all D trigger devices are connected with a storage input end, and the D trigger device is used for storing middle-stage time interval digital signals and inputting multi-bit digital signals to a multiplexing end 3 of a reading circuit; when an enable pulse signal is input into a start signal low-segment counter array (14), an enable control signal controls one start signal low-segment counter of the start signal low-segment counter array (14) to normally work, namely the enable input end of the start signal low-segment counter is at a high level, the other start signal low-segment counter is at a low level, the start signal low-segment counter receives a middle-segment time interval digital signal and an enable pulse signal and measures a low-segment time interval, the enable control signal is input into the enable signal input end of the synchronous circuit 1 and enables a PMOS (P-channel metal oxide semiconductor) gate in a multi-input N-type pseudo-OR gate to be at a high level, at the moment, the synchronous circuit 1 normally works and is also input into an encoder enable end and a D trigger reset end in the register 1, the input enable control signal is at a high level, the register 1 normally works, when the enable pulse signal is applied to the start signal low-segment counter which normally works, enabling the rising edge of the pulse signal to trigger the D flip-flops in the register 1, so that all the D flip-flops in the register 1 transmit the D input signal into the output Q, and the output Q of all the D flip-flops form a middle-period time interval digital signal and input the middle-period time interval digital signal into the reading circuit (11); then, the rising edge of the enable pulse signal triggers an arbiter of the synchronous circuit 1, so that the arbiter outputs a high level and inputs the high level to a multi-input N-type pseudo-OR gate connected with the arbiter, the multi-input N-type pseudo-OR gate outputs a START high level signal, at this time, a signal at an input end of the synchronous signal is input to another multi-input N-type pseudo-OR gate of the synchronous circuit 1, in an arbiter array of the interpolator 1, the output of the arbiter which outputs the high level at first is applied to an NMOS tube gate in the multi-input N-type pseudo-OR gate connected with the arbiter, and the multi-input N-type pseudo-OR gate outputs a STOP high level signal; when a START high-level signal and a STOP high-level signal are respectively input into a pulse generator 1 and a pulse generator 2 to generate a high level, the pulse generator 1 and the pulse generator 2 are respectively input into an input end of a vernier delay ring 1 and an input end of the vernier delay ring 2, the vernier delay ring 1 generates a pulse cycle, similarly, the vernier delay ring 2 also generates a pulse cycle, a pulse of the pulse generator 1 is input into one input port of an XOR gate 1 in the vernier delay ring 1, the output of the XOR gate generates the same high-level pulse signal, when the vernier delay ring is delayed by a single-ended voltage-controlled delay unit 1, the output of the single-ended voltage-controlled delay unit 1 generates a high-level pulse signal and is input into one input end of an AND gate, the output end of the AND gate also outputs a high-level pulse and is connected into the other input end of the XOR gate, the output end of the XOR gate generates a pulse again, and the pulse cycle is generated by the vernier delay ring 1 repeatedly, when the rising edge of the cyclic pulse of the vernier delay ring 2 lags behind the rising edge of the vernier delay ring 1, the output Q end of the D trigger is always in a high level, so that the two vernier delay rings keep cycling, when the rising edge of the cyclic pulse of the vernier delay ring 1 leads the rising edge of the cyclic pulse of the vernier delay ring 2, the cycle is stopped, and the counter outputs a multi-bit digital signal to the multiplex 3 of the reading circuit (12), namely, a low-section time interval is measured.

Compared with the prior art, the invention has the advantages that: the novel time-to-digital conversion integrated circuit can repeatedly measure the measurement time at different moments in a circulating manner, which means that a system can greatly reduce random errors, so that more accurate system errors can be obtained, and the chip still keeps the characteristic of high precision under high integration and large dynamic range.

Drawings

Fig. 1 is a system block diagram of a novel time-to-digital conversion integrated circuit, which is composed of an external input start signal (1), an external input stop signal (2), an external input reference clock signal (3), a start signal port (4), a stop signal port (5), a reference clock signal port (6), a delay phase-locked loop module (7), a global counter (9), a start signal counting module (10), a stop signal counting module (11), and a readout circuit (12).

Fig. 2 is a system block diagram of an embodiment of a novel time-to-digital conversion integrated circuit, which is composed of an external input start signal (101), an external input stop signal (102), an external input reference clock signal (103), a start signal port (104), a stop signal port (105), a reference clock signal port (106), a delay locked loop module (107), a global counter (109), a start signal counting module (110), a stop signal counting module (111), and a readout circuit (112).

Fig. 3 is a schematic diagram of an embodiment of a novel time-to-digital conversion integrated circuit, in which a first start signal low-level counter and a second start signal low-level counter are in an array of start signal low-level counters.

Fig. 4 shows a delay locked loop module of an embodiment of a novel time-to-digital conversion integrated circuit, wherein the delay locked loop module (7) is composed of a high-level delay locked loop (27) and a low-level delay locked loop (28).

Fig. 5 shows a start signal middle counter (113) of an embodiment of a novel time-to-digital conversion integrated circuit, which is composed of a cycle controller 1(117) and an interpolator 1 (118).

FIG. 6 shows that the start signal low counter array (114) of the embodiment of the novel time-to-digital conversion integrated circuit is composed of 4 start signal low counters, and each start signal low counter is composed of a synchronization circuit 1(125), a fine computation circuit 1(126) and a register 1(127)

Detailed Description

The invention is further illustrated below with reference to specific examples.

The working time sequence of the novel time-to-digital conversion integrated circuit is shown in fig. 3, the system block diagram is shown in fig. 2, and the novel time-to-digital conversion integrated circuit is composed of an external input start signal (101), an external input stop signal (102), an external input reference clock signal (103), a start signal port (104), a stop signal port (105), a reference clock signal port (106), a delay phase-locked loop module (107), a global counter (109), a start signal counting module (110), a stop signal counting module (111) and a reading circuit (112); the internal structure connection of the starting signal counting module (110) and the stopping signal counting module (111) is the same as the working principle; the delay phase-locked loop module (107) consists of a high-level delay phase-locked loop (127) and a low-level delay phase-locked loop (128), the starting signal counting module (110) consists of a starting signal middle counter (113) and a starting signal low counter array (114), and the stopping signal counting module (111) consists of a stopping signal middle counter (115) and a stopping signal low counter array (116); an external input reference clock signal (103) is transmitted to a reference clock input end 1 of a delay phase-locked loop module (107) and a reference clock input end 2 of a global counter (109) through a reference clock signal port (106), a plurality of clock output ends 1 of the delay phase-locked loop module (107) output 10 multiphase clock signals with equal phase difference, the delay phase-locked loop module (107) is connected to a clock input end 1 of the start signal counting module (110) and a clock input end 2 of the stop signal counting module (111), a control voltage 1 output end of the delay phase-locked loop module (107) outputs a control voltage 1 to a first input end of the start signal counting module (110) and a first input end of the stop counting module (111), and a control voltage 2 output end of the delay phase-locked loop module (107) outputs a control voltage 2 to a second input end of the start signal counting module (110) and a second input end of the stop signal counting module (111); when the external input start signal (101) generates a pulse signal from the start signal port (104) to the third input terminal of the start signal counting module (110) and the start counting input terminal of the global counter (109), the rising edge of the pulse signal triggers the global counter (109) to start counting the clock rising edge of the external input 100MHz reference clock signal (103), the rising edge of the pulse signal also triggers the start signal counting module (110) to enable the internal enable pulse signals with 11ns as the period, each enable pulse signal rising edge appears between the rising edges of 10 adjacent multiphase clock signals of the advanced time-delay phase-locked loop (107), the phase difference between each enable pulse signal rising edge and the reference clock signal rising edge is measured and converted into a digital signal, the obtained phase difference is the middle time interval (ST 11) of the start signal, .., ST110) and a low-level time interval (ST21, ST210), and the obtained digital signal is output to the multiplexing input terminal 1 of the readout circuit (112) through the 8-bit digital signal output terminal of the start signal counting module (10); an external input stop signal (102) is transmitted to a third input end of a stop signal counting module (111) and a stop counting input end of a global counter (109) through a stop signal port (105), when the external input stop signal (102) generates a pulse signal, the rising edge of the pulse signal triggers the global counter (109) to output a counting result of the global counter (109) at the moment, the obtained counting result is a high-period time interval Tg, and the counting result is output to a multiplexing input end 2 of a reading circuit (112) from the output end of the global counter (109) in the form of a 4-bit digital signal, the stop signal counting module (111) has the same internal principle and output form as the start signal counting module (110), the rising edge of the pulse signal also triggers the stop signal counting module (111) to output a digital signal representing the phase difference to a multiplexing input end 3 of the reading circuit (112), a mid-range time interval (SP 11.., SP110) and a low-range time interval (SP 21.., SP210) of the stop signal; finally, the measured digital signal is serially output through a readout circuit (112), so that a time interval T between a rising edge of a pulse signal of the external input start signal (101) and a rising edge of the pulse signal of the external input stop signal (2) is measured and output in the form of a digital signal.

A time interval T between a rising edge of the pulse signal of the external input start signal (1) and a rising edge of the pulse signal of the external input stop signal (102) is composed of a high-stage time interval Tg of the global counter (109), a plurality of middle-stage time intervals (ST11,..., ST110) generated by the start signal counting module (110) and a plurality of middle-stage time intervals (SP11,..., SP110) and low-stage time intervals (SP21,..., SP210) generated by the low-stage time intervals (ST21,..., ST210) and the stop signal counting module (111); averaging a plurality of middle-segment signal time intervals and low-segment time intervals generated by the start signal counting module (110) to obtain a more accurate start signal middle-segment signal time interval ST1 and low-segment time interval ST2, and similarly, the stop signal counting module (111) also obtains a more accurate stop signal middle-segment time interval SP2 and low-segment time interval SP 2; the total time interval T is the high segment time interval Tg plus the more accurate start signal mid signal time interval ST1 and low segment time interval ST2 minus the more accurate stop signal mid time interval SP1 and low segment time interval SP 2.

The time interval between the rising edge of the pulse signal of the external input starting signal (1) and the rising edge of the pulse signal of the external input stopping signal (2) consists of a high-stage time interval of a global counter (9), a plurality of middle-stage time intervals and low-stage time intervals generated by a 4-bit digital signal and starting signal counting module (10), a plurality of middle-stage time intervals and low-stage time intervals generated by an 8-bit digital signal and stopping signal counting module (11) and an 8-bit digital signal; averaging a plurality of middle-segment signal time intervals and low-segment time intervals generated by the start signal counting module (10) to obtain more accurate middle-segment signal time intervals and low-segment time intervals of the start signal, and similarly, obtaining more accurate middle-segment time intervals and low-segment time intervals of the stop signal by the stop signal counting module (11); the total time interval is the high interval plus the more accurate start signal mid-segment time interval and low interval minus the more accurate stop signal mid-segment time interval and low interval.

As shown in fig. 4, the reference clock signal input terminal 1 of the delay-locked loop module (107) is connected to the advanced delay-locked loop (127), 10 clock phase signals of the advanced delay-locked loop (127) are connected to the plurality of clock output terminals 1 of the delay-locked loop module (107), the advanced delay-locked loop (127) outputs the control voltage 1 to the control voltage 1 output terminal of the delay-locked loop module (107), the low-level delay-locked loop (128) outputs the control voltage 2 to the control voltage 2 output terminal of the delay-locked loop module (107), the clock phase input terminals 1 and 2 of the low-level delay-locked loop (128) are respectively connected to the last two clock phase signals of the 10 clock phase signals in the advanced delay-locked loop (127), inputting the 9 th and 10 th clock phase signals of the 10 clock phase signals into a low-level delay phase-locked loop (128); the advanced delay phase-locked loop (127) consists of a thick single-ended voltage-controlled delay chain, a phase frequency detector, a charge pump and a low-pass filter, and has the functions that the advanced delay phase-locked loop receives a reference clock signal at a reference clock input end 1 of the advanced delay phase-locked loop, and the advanced delay phase-locked loop (127) provides 1 and 10 clock phase signals which are stable and control voltage and do not change along with the process, the power supply voltage and the temperature under the action of a phase-locked loop of the advanced delay phase-locked loop; the low-level delay phase-locked loop (128) consists of a thin single-ended voltage-controlled delay chain, a phase frequency detector, a charge pump and a low-pass filter, and has the functions that the low-level delay phase-locked loop (128) receives clock phase signals of a clock phase input end 1 and a clock phase input end 2, and the low-level delay phase-locked loop (128) provides stable control voltage 2 which does not change along with the process, the power supply voltage and the temperature through the action of a phase-locked loop of the low-level delay phase-locked loop (128).

As shown in fig. 5, the start signal middle counter (113) is composed of the loop controller 1(117) and the interpolator 1(118), and the stop signal middle counter (115) is composed of the loop controller 2 and the interpolator 2; the cycle controller 1(117) of the start signal middle segment counter (13) consists of a pulse generator (119), a single-ended voltage-controlled delay chain (120), a nine-system counter (121), a decoder (122) and a digital logic gate; the function is to output enable pulse signals with the period of 11ns to the measurement start input ends of a plurality of start signal low-stage counters in a start signal low-stage counter array (114), and output enable control signals to control the start signal low-stage counter array (114), wherein a plurality of output signals in the enable control signals are respectively connected to the enable input ends of the plurality of start signal low-stage counters, so that the plurality of start signal low-stage counters receive the enable pulse signals in order; the input of the pulse generator (119) is connected with the third input end of the start signal counting module (110), the output of the pulse generator (119) is respectively connected with one port of the AND gate and the input of the delay unit, the output of the delay unit is connected with the other port of the AND gate after passing through the inverter, and the output port of the AND gate is the output port of the pulse generator (119); when an external input start signal (101) generates a pulse signal, the rising edge of the pulse signal triggers a pulse generator (119), the pulse generator (119) generates a pulse signal at the output, the pulse signal output by the pulse generator (119) is input to one input end of an exclusive-or gate, the output signal of the exclusive-or gate generates the same pulse signal and is input to the input end of a single-ended voltage-controlled delay chain (120), the single-ended voltage-controlled delay chain (120) is controlled by a control voltage 1, the output end of the single-ended voltage-controlled delay chain (120) generates a first enabling pulse signal after the delay time of the single-ended voltage-controlled delay chain (120), the enabling pulse signal is connected with an NMOS transistor and is input to the other port of the exclusive-or gate, at the moment, the output signal of the exclusive-or gate is in a low level, and the enabling pulse signal enables the output signal of the exclusive-or gate to generate the same pulse signal, the single-ended voltage-controlled delay chain (120) enables the output of the single-ended voltage-controlled delay chain to generate a second enable pulse signal, and the operation is repeated in such a way that the cyclic controller 1 outputs a plurality of enable pulse signals; a plurality of enable pulse signals are input to the measurement input ends of a multi-system counter and a start signal low-stage counter array (114), the count of a nine-system counter (121) is increased by one by the rising edge of each enable pulse signal, when the count of the nine-system counter (121) is full (1001), the nine-system counter (121) outputs a reset signal high level and inputs the reset signal high level to the grid of an NMOS tube to stop circulation, a single-end voltage-controlled delay chain (120) does not output the enable pulse signals any more, two low level outputs of the nine-system counter (121) are connected to a decoder, the decoder obtains a thermal unique code output through decoding, the thermal unique code output is an enable control signal, the enable control signal is respectively input to the enable input ends of all start signal low-stage counters in the start signal low-stage counter array (114), the enable input ends are in normal work when being in the high level, and do not work when being in the low level, when the counter counts and adds one, the output signal of the decoder will shift to high by one bit, the enable control signal controls the next start signal low-stage counter to receive the enable pulse signal, in this way, the start signal low-stage counter array (114) can output a plurality of middle-stage time intervals and low-stage time intervals respectively; the interpolator 1(118) is composed of an arbiter array (123) and an encoder (124), wherein the input end of IN1 of each arbiter IN the arbiter array (123) is connected with an enable pulse signal, the input end of IN2 is connected with the clock input end 1 of the start signal counting module (110), the output of each arbiter is input into the input end of the encoder (124), the encoder (124) outputs a four-bit digital signal through encoding, and the output of the encoder is connected with the storage input end of each start signal low-stage counter IN the start signal low-stage counter array (114) and the synchronous signal input end of each start signal low-stage counter IN the start signal low-stage counter array (114); the function is that at the rising edge of each enable pulse signal, the number of clock step signals between the rising edge of each enable pulse signal and the rising edge of the next reference clock signal, namely the middle-stage time interval, is output in a digital signal form, and simultaneously the detected clock phase signals are sent into the synchronous signal input end of a low-stage counter array (114), the function of the arbiter is that the rising edge of which input port of the two input ends of the arbiter can be identified to arrive faster, when the enable pulse signal arrives preferentially than the clock step signals, the arbiter outputs a high level, otherwise, the arbiter outputs a low level; when the rising edge of the enable pulse signal triggers the interpolator 1(118), the arbiter array of the interpolator 1 will output as the function of the arbiters, and the outputs of all arbiters in the arbiter array will be input to the synchronization signal input of each start signal low-level counter in the start signal low-level counter array (114), and the output of the encoder will be input to the storage input of each start signal low-level counter in the start signal low-level counter array (114).

As shown in fig. 6, the start signal low-stage counter array (114) is composed of 4 start signal low-stage counters, each of which is composed of a synchronization circuit 1(125), a fine computation circuit 1(126) and a register 1 (127); each start signal low-stage counter in the start signal low-stage counter array (14) consists of a synchronous circuit 1(125), a fine calculation circuit 1(126) and a register 1 (129); the function is to obtain the low-stage time interval and send it to the fine counting circuit for measurement, wherein the synchronous circuit 1(125) is composed of two multi-input N-type pseudo-OR gates and an arbitrator, the gates of all NMOS tubes of one multi-input N-type pseudo-OR gate are connected to the storage input end of the low-stage counter of the START signal, the multi-input N-type pseudo-OR gates output STOP signal, the gate of one NMOS tube of the other multi-input N-type pseudo-OR gate is connected with the output of the arbitrator, the other inputs are connected with the ground, the IN1 input of the arbitrator is connected with the output of the enable pulse signal, the IN2 input end is connected with the ground, the multi-input N-type pseudo-OR gates output START signal, the START signal represents the rising edge of the enable pulse signal, the STOP signal represents the rising edge of the adjacent multiphase clock signal, the time interval between the rising edges of the two signals is low-stage time interval, the START signal and the STOP signal of the two multi-input N-type pseudo-OR gates are respectively connected to the START input end and the START input end of the fine counting circuit (126) The input end of the STOP, the PMOS tube of two multi-input N-type false OR gates is connected with the enable input end; the fine computation circuit (126) consists of a pulse generator 1, a pulse generator 2, a vernier delay ring 1(130), a vernier delay ring 2(131), a D trigger and a counter, wherein the vernier delay ring 1(130) consists of the pulse generator 1, an exclusive-OR gate 1, a single-ended voltage-controlled delay unit 1 and a digital logic gate, the single-ended voltage-controlled delay unit 1 consists of 2 single-ended voltage-controlled delay units controlled by a controlled voltage 2, the vernier delay ring 2(131) consists of the pulse generator 2, the exclusive-OR gate 2, the single-ended voltage-controlled delay unit 2 and the digital logic gate, and the single-ended voltage-controlled delay unit 2 consists of 1 single-ended voltage-controlled delay unit controlled by the controlled voltage 2; the internal structural connection and the working principle of the vernier delay ring 1(130) are the same as those of the vernier delay ring 2 (131); the input ends of the pulse generator 1 and the pulse generator 2 are respectively connected with a START input end and a STOP input end, the input end of the vernier delay ring 1(130) is connected with the pulse generator 1, the input end of the vernier delay ring 2(131) is connected with the pulse generator 2, the output end of the pulse generator 1 is connected with one port of the XOR gate 1, the output of the XOR gate 1 is input into the single-ended voltage-controlled delay unit 1, the output of the single-ended voltage-controlled delay unit 1 is connected into one port of the AND gate 1, the output of the AND gate 1 is connected into the counter and is connected into the other input of the XOR gate 1, meanwhile, the D input end of the D trigger is connected with the output of the exclusive-OR gate 1, the clock input end of the D trigger is connected with the output of the exclusive-OR gate 2, the output Q of the D trigger is connected to the other input end of the AND gate 1 and the AND gate 2, and the digital signal output by the counter is in a low-period time interval and is input to the multiplexing end 3 of the reading circuit (112); the register 1(129) is composed of a D trigger array, a plurality of inputs of an encoder are connected with the output of an arbiter array (123) in an interpolator 1(118), a plurality of outputs of an encoder (124) are connected with D ends of all D triggers in the D trigger array, and CLK ends of all D triggers are connected with a storage input end, so that the D triggers are used for storing middle-interval digital signals and inputting 4-bit digital signals to a multiplexing end 3 of a reading circuit; when the enable pulse signal is input into the start signal low segment counter array (114), the enable control signal controls one of the start signal low segment counters of the start signal low segment counter array (114) to normally work, i.e. the enable signal input end of the start signal low segment counter is at high level, and the other is at low level, the start signal low segment counter receives the middle segment time interval digital signal and the enable pulse signal and measures the low segment time interval, the enable control signal is input into the enable signal input end of the synchronous circuit 1(125) and makes the PMOS gate in the multi-input N-type pseudo-OR gate appear at high level, at this moment, the synchronous circuit 1(125) normally works, the enable signal input by the other start signal low segment counters of the start signal low segment counter array (114) is at low level, therefore, it does not work, and simultaneously input into the encoder enable end and the D flip-flop reset end in the register 1(129), the input enable control signal is high level, the register 1(129) normally works, when the enable pulse signal acts on the start signal low-stage counter of the normal work, the rising edge of the enable pulse signal triggers the D flip-flops in the register 1(129), all the D flip-flops in the register 1(129) transmit the signals of the D input into the output Q, and the output Q of all the D flip-flops form middle-stage time interval digital signals and input into the reading circuit (111); then, the rising edge of the enable pulse signal triggers an arbiter of the synchronous circuit 1(125), so that the arbiter outputs a high level and inputs the high level to a multi-input N-type pseudo-or gate connected with the arbiter, the multi-input N-type pseudo-or gate outputs a START high level signal, at this time, a signal at an input end of the synchronous signal is input to another multi-input N-type pseudo-or gate of the synchronous circuit 1, in an arbiter array of the interpolator 1, the output of the arbiter which outputs the high level at first is applied to a gate of an NMOS pipe in the multi-input N-type pseudo-or gate connected with the arbiter, so that the multi-input N-type pseudo-or gate outputs a STOP high level signal; when a START high-level signal and a STOP high-level signal are respectively input into a pulse generator 1 and a pulse generator 2 to generate a high level, the pulse generator 1 and the pulse generator 2 are respectively input into an input end of a vernier delay ring 1(130) and an input end of a vernier delay ring 2(131), the vernier delay ring 1(130) generates a pulse cycle, and similarly, the vernier delay ring 2(131) also generates a pulse cycle, a pulse of the pulse generator 1 is input into one input port of an exclusive-or gate 1 in the vernier delay ring 1(130), the output of the pulse generator generates the same high-level pulse signal, the pulse signal is delayed by a single-ended voltage-controlled delay unit 1, the high-level pulse signal appears at the output of the voltage-controlled single-ended delay unit 1 and is input into one input port of an and gate, the high-level pulse is also output from the output port of the and is connected to the other input port of the exclusive-or gate, so that the output port of the exclusive-or gate appears a pulse again, repeating the steps, so that the vernier delay ring 1 generates pulse circulation, when the rising edge of the circulation pulse of the vernier delay ring 1 lags behind the rising edge of the vernier delay ring 2, the output Q end of the D trigger is always in a high level, so that the two vernier delay rings keep circulation, when the rising edge of the circulation pulse of the vernier delay ring 1 leads the rising edge of the circulation pulse of the vernier delay ring 2, the circulation is stopped at the moment, and the counter outputs a 4-bit digital signal to the multiplex 3 of the reading circuit (112), namely, a low-section time interval is measured.

Claims (5)

1. A novel time-to-digital conversion integrated circuit is characterized in that: the device consists of an external input starting signal (1), an external input stopping signal (2), an external input reference clock signal (3), a starting signal port (4), a stopping signal port (5), a reference clock signal port (6), a delay phase-locked loop module (7), a global counter (9), a starting signal counting module (10), a stopping signal counting module (11) and a reading circuit (12); the delay phase-locked loop module (7) consists of a high-level delay phase-locked loop (27) and a low-level delay phase-locked loop (28), the starting signal counting module (10) consists of a starting signal middle counter (13) and a starting signal low counter array (14), and the stopping signal counting module (11) consists of a stopping signal middle counter (15) and a stopping signal low counter array (16); the internal structure connection, the working principle and the output form of the stop signal counting module (11) are the same as those of the start signal counting module (10); an external input reference clock signal (3) is transmitted to a reference clock input end 1 of a delay phase-locked loop module (7) and a reference clock input end 2 of a global counter (9) through a reference clock signal port (6), a plurality of clock output ends 1 of the delay phase-locked loop module (7) output a plurality of multiphase clock signals with equal phase difference, the delay phase-locked loop module (7) is connected to a clock input end 1 of the start signal counting module (10) and a clock input end 2 of the stop signal counting module (11), a control voltage 1 output end outputs a control voltage 1 to a first input end of the start signal counting module (10) and a first input end of the stop counting module (11), and a control voltage 2 output end outputs a control voltage 2 to a second input end of the start signal counting module (10) and a second input end of the stop signal counting module (11); an external input start signal (1) passes through a start signal port (4) to a third input end of a start signal counting module (10) and a start counting input end of a global counter (9), when the external input start signal (1) generates a pulse signal, a rising edge of the pulse signal triggers the global counter (9) to start counting clock rising edges of an external input reference clock signal (3), the rising edge of the pulse signal also triggers the start signal counting module (10) to enable an enable pulse signal to appear in a period, each enable pulse signal rising edge appears between rising edges of all adjacent multiphase clock signals of a high-level delay phase-locked loop (7) in sequence, a phase difference between each enable pulse signal rising edge and a reference clock signal rising edge is measured and converted into a digital signal, and the obtained phase difference is a middle section time interval and a low section time interval of the start signal, the obtained digital signal is output to a multiplex input end 1 of a reading circuit (12) through a digital signal output end of a starting signal counting module (10); an external input stop signal (2) passes through a stop signal port (5) to a third input end of a stop signal counting module (11) and a stop counting input end of a global counter (9), when the external input stop signal (2) generates a pulse signal, a rising edge of the pulse signal triggers the global counter (9) to output a counting result of the global counter (9) at the moment, the obtained counting result is a high-stage time interval, the counting result is output from an output end of the global counter (9) to a multiplexing input end 2 of a reading circuit (12) in the form of a digital signal, and the rising edge of the pulse signal also triggers the stop signal counting module (11) to output the digital signal representing the phase difference to a multiplexing input end 3 of the reading circuit (12), namely the middle-stage time interval and the low-stage time interval of the stop signal; finally, the measured digital signal is serially output through a readout circuit (12), so that the time interval between the rising edge of the pulse signal of the external input start signal (1) and the rising edge of the pulse signal of the external input stop signal (2) is measured and output in the form of a digital signal.

2. The novel time-to-digital conversion integrated circuit of claim 1, wherein: a reference clock signal input end 1 of the delay phase-locked loop module (7) is connected with an advanced delay phase-locked loop (27), a plurality of clock output ends 1 of the delay phase-locked loop module (7) are connected with a plurality of clock output ends 2 of the advanced delay phase-locked loop (27), the advanced delay phase-locked loop (27) outputs a control voltage 1 to a control voltage 1 output end of the delay phase-locked loop module (7), a low-level delay phase-locked loop (28) outputs a control voltage 2 to a control voltage 2 output end of the delay phase-locked loop module (7), and a clock phase input end 1 and a clock phase input end 2 of the low-level delay phase-locked loop (28) are respectively connected with the last two clock phase signals output by a plurality of clock phase signals in the advanced delay phase-locked loop (27); the advanced delay phase-locked loop (27) consists of a thick single-ended voltage-controlled delay chain, a phase frequency detector, a charge pump and a low-pass filter, and has the functions that the advanced delay phase-locked loop (27) receives a reference clock signal of a reference clock input end 3 of the advanced delay phase-locked loop, and the advanced delay phase-locked loop (1) provides a stable control voltage 1 and a plurality of clock phase signals which do not change along with the process, the power supply voltage and the temperature under the action of a phase-locked loop of the advanced delay phase-locked loop; the low-level delay phase-locked loop (28) consists of a thin single-ended voltage-controlled delay chain, a phase frequency detector, a charge pump and a low-pass filter, and has the functions that the low-level delay phase-locked loop (28) receives clock phase signals of a clock phase input end 1 and a clock phase input end 2, and the low-level delay phase-locked loop (28) provides stable control voltage 2 which does not change along with the process, the power supply voltage and the temperature through the action of a phase-locked loop of the low-level delay phase-locked loop.

3. The novel time-to-digital conversion integrated circuit of claim 1, wherein: the starting signal middle counter (13) consists of a cycle controller 1 and an interpolator 1, the cycle controller 1 consists of a pulse generator, a single-ended voltage-controlled delay chain, a multilevel counter, a decoder and a digital logic gate, and has the functions of outputting periodic enable pulse signals and inputting the enable pulse signals to the measurement starting input ends of a plurality of starting signal low-stage counters in a starting signal low-stage counter array (14), outputting enable control signals to control the plurality of starting signal low-stage counters in the starting signal low-stage counter array (14), and respectively connecting a plurality of output signals in the enable control signals to the enabling input ends of the plurality of starting signal low-stage counters so that the plurality of starting signal low-stage counters receive the pulse signals in order; the input of the pulse generator is connected with the third input end of the start signal counting module (10), the output of the pulse generator is respectively connected with one port of the AND gate and the input of the delay unit, the output of the delay unit is connected with the other port of the AND gate after passing through the phase inverter, and the output port of the AND gate is the output port of the pulse generator; when an external input start signal (1) generates a pulse signal, the rising edge of the pulse signal triggers a pulse generator, the pulse generator can generate a pulse signal at the output, the pulse signal output by the pulse generator is input to one input end of an exclusive-OR gate, the output signal of the exclusive-OR gate generates the same pulse signal and is input to the input end of a single-ended voltage-controlled delay chain, the single-ended voltage-controlled delay chain is controlled by a control voltage 1, through the delay time of the single-ended voltage-controlled delay chain, the output of the single-ended voltage-controlled delay chain generates a first enable pulse signal, the enable pulse signal is connected with an NMOS tube and is input to the other port of the exclusive-OR gate, the output signal of the exclusive-OR gate is at a low level, the enable pulse signal enables the output signal of the exclusive-OR gate to generate the same pulse signal, the single-ended voltage-controlled delay chain enables the output of the single-ended voltage-controlled delay chain to generate a second enable pulse signal, repeating the steps to enable the circulation controller 1 to output a plurality of enable pulse signals; a plurality of enable pulse signals are input to the measurement input ends of a multi-system counter and a start signal low-stage counter array (14), the rising edge of each enable pulse signal enables the multi-system counter to count by one, when the multi-system counter counts and is full, the multi-system counter outputs a reset signal, the high level of the reset signal is input to the grid of an NMOS (N-channel metal oxide semiconductor) tube to stop circulation, a single-ended voltage-controlled delay chain does not output the enable pulse signals any more, a plurality of low level outputs of the multi-system counter are connected to a decoder, the decoder obtains a thermal unique code output through decoding, the thermal unique code output is an enable control signal, the enable control signal is respectively input to the enable input ends of all start signal low-stage counters in the start signal low-stage counter array (14), the enable input end is in a high level and works normally, when the low level does not work, when the counter counts by one, the output signal of the decoder is shifted to a high level, the enable control signal controls the next start signal low-stage counter to receive the enable pulse signal, and in this way, the start signal low-stage counter array (14) can respectively output a plurality of middle-stage time intervals and low-stage time intervals; the interpolator 1 consists of an arbiter array, the input end of IN1 of each arbiter IN the arbiter array is connected with an enable pulse signal, the input end of IN2 is connected with the clock input end 1 of a start signal counting module (10), the output of each arbiter is input to the input end of an encoder and the synchronous signal input end of each start signal low-stage counter IN a start signal low-stage counter array (14), the encoder outputs a four-bit digital signal through encoding, and the output of the encoder is connected to the storage input end of each start signal low-stage counter IN the start signal low-stage counter array; the function of the arbiter is to identify which input port rising edge of the two input ends of the arbiter arrives faster, when the enable pulse signal arrives preferentially than the clock step signal, the arbiter outputs high level, otherwise outputs low level; when the rising edge of the enable pulse signal triggers the interpolator 1, the arbiter array of the interpolator 1 will output according to the function of the arbiter, and the output of all the arbiters in the arbiter array will be input to the synchronization signal input of each start signal low segment counter in the start signal low segment counter array (14), and the output of the encoder will be input to the storage input of each start signal low segment counter in the start signal low segment counter array (14).

4. The novel time-to-digital conversion integrated circuit of claim 1, wherein: the start signal low segment counter array (14) is composed of a plurality of start signal low segment counters; each starting signal low-stage counter consists of a synchronous circuit 1, a fine computing circuit 1 and a register 1; each starting signal low-stage counter in the starting signal low-stage counter array (14) consists of a synchronous circuit 1, a fine computing circuit 1 and a register 1; the function is to obtain the low-segment time interval and send it to the fine counting circuit for measurement, wherein the synchronous circuit 1 is composed of two multi-input N-type pseudo-OR gates and an arbitrator, the gates of all NMOS tubes of one multi-input N-type pseudo-OR gate are connected to the synchronous signal input end of the START signal low-segment counter, the multi-input N-type pseudo-OR gates output STOP signals, the gate of one NMOS tube of the other multi-input N-type pseudo-OR gate is connected with the output of the arbitrator, the other inputs are connected with the ground, the IN1 input of the arbitrator is connected with the output of the enable pulse signal, the IN2 is connected with the ground, the multi-input N-type pseudo-OR gates output START signals, the START signals represent the rising edge of the enable pulse signal, the STOP signals represent the rising edge of the adjacent multiphase clock signal, the time interval between the rising edges of the two signals is the low-segment time interval, the START signals and the STOP signals output by the two multi-input N-type pseudo-OR gates are respectively connected to the T input end and STOP input end of the fine counting circuit, the PMOS tubes of the two multi-input N-type pseudo-OR gates are connected with an enable input end; the fine calculation circuit comprises a pulse generator 1, a pulse generator 2, a vernier delay ring 1, a vernier delay ring 2, a D trigger and a counter, wherein the vernier delay ring 1 comprises the pulse generator 1, an exclusive-OR gate 1, a single-ended voltage-controlled delay unit 1 and a digital logic gate, the single-ended voltage-controlled delay unit 1 comprises 1 single-ended voltage-controlled delay unit controlled by a controlled voltage 2, the vernier delay ring 2 comprises the pulse generator 2, the exclusive-OR gate 2, the single-ended voltage-controlled delay unit 2 and the digital logic gate, and the single-ended voltage-controlled delay unit 2 comprises 2 single-ended voltage-controlled delay units controlled by the controlled voltage 2; the inner structure connection and the working principle of the vernier delay ring 1 are the same as those of the vernier delay ring 2; the input ends of a pulse generator 1 and a pulse generator 2 are respectively connected with a START input end and a STOP input end, the input ends of a vernier delay ring 1 and a vernier delay ring 2 are respectively connected with the output ends of the pulse generator 1 and the pulse generator 2, the output end of the pulse generator 1 is connected with one port of an exclusive-OR gate 1, the output of the exclusive-OR gate 1 is input into a single-ended voltage-controlled delay unit 1, the output of the single-ended voltage-controlled delay unit 1 is connected into one port of an AND gate 1, the output of the AND gate 1 is connected into a counter and is connected into the other input of the exclusive-OR gate 1, meanwhile, the D input end of the D trigger is connected with the output of the exclusive-OR gate 1, the clock input end of the D trigger is connected with the output of the exclusive-OR gate 2, the output Q of the D trigger is connected to the other input end of the AND gate 1 and the AND gate 2, and the digital signal output by the counter is in a low-period time interval and is input to the multiplexing end 3 of the reading circuit (112); the register 1 is composed of a D trigger array device, a plurality of inputs of an encoder are connected with the output of an arbiter array in the interpolator 1, a plurality of outputs of the encoder are connected with D ends of all D trigger devices in the D trigger array, and CLK ends of all D trigger devices are connected with a storage input end, and the D trigger device is used for storing middle-stage time interval digital signals and inputting multi-bit digital signals to a multiplexing end 3 of a reading circuit; when an enable pulse signal is input to a start signal low-segment counter array (14), an enable control signal controls one start signal low-segment counter of the start signal low-segment counter array (14) to normally work, namely the enable input end of the start signal low-segment counter is at a high level, the other start signal low-segment counter is at a low level, the start signal low-segment counter receives a middle time interval digital signal and an enable pulse signal and measures a low-segment time interval, the enable control signal is input to the enable signal input end of the synchronous circuit 1 and enables a PMOS (P-channel metal oxide semiconductor) grid in the multi-input N-type pseudo-OR gate to be at a high level, at the moment, the synchronous circuit 1 normally works and is also input to an encoder enable end and a D trigger reset end in the register 1, the input enable control signal is at a high level, the register 1 normally works, when the enable pulse signal is applied to the start signal low-segment counter which normally works, enabling the rising edge of the pulse signal to trigger the D flip-flops in the register 1, so that all the D flip-flops in the register 1 transmit the D input signal into the output Q, and the output Q of all the D flip-flops form a middle-period time interval digital signal and input the middle-period time interval digital signal into the reading circuit (11); then, the rising edge of the enable pulse signal triggers an arbiter of the synchronous circuit 1, so that the arbiter outputs a high level and inputs the high level to a multi-input N-type pseudo-OR gate connected with the arbiter, the multi-input N-type pseudo-OR gate outputs a START high level signal, at this time, a signal at the synchronous signal input end is input to another multi-input N-type pseudo-OR gate of the synchronous circuit 1, and in an arbiter array of the interpolator 1, the output of the arbiter which firstly outputs the high level is applied to an NMOS transistor gate in the multi-input N-type pseudo-OR gate connected with the arbiter, so that the multi-input N-type pseudo-OR gate outputs a STOP high level signal; when a START high-level signal and a STOP high-level signal are respectively input into a pulse generator 1 and a pulse generator 2 to generate a high level, the pulse generator 1 and the pulse generator 2 are respectively input into an input end of a vernier delay ring 1 and an input end of the vernier delay ring 2, the vernier delay ring 1 generates a pulse cycle, similarly, the vernier delay ring 2 also generates a pulse cycle, a pulse of the pulse generator 1 is input into one input port of an XOR gate 1 in the vernier delay ring 1, the output of the XOR gate generates the same high-level pulse signal, when the vernier delay ring is delayed by a single-ended voltage-controlled delay unit 1, the output of the single-ended voltage-controlled delay unit 1 generates a high-level pulse signal and is input into one input end of an AND gate, the output end of the AND gate also outputs a high-level pulse and is connected into the other input end of the XOR gate, the output end of the XOR gate generates a pulse again, and the pulse cycle is generated by the vernier delay ring 1 repeatedly, when the rising edge of the cyclic pulse of the vernier delay ring 2 lags behind the rising edge of the vernier delay ring 1, the output Q end of the D trigger is always in a high level, so that the two vernier delay rings keep cycling, when the rising edge of the cyclic pulse of the vernier delay ring 1 leads the rising edge of the cyclic pulse of the vernier delay ring 2, the cycle is stopped, and the counter outputs a multi-bit digital signal to the multiplex 3 of the reading circuit (12), namely, a low-section time interval is measured.

5. The novel time-to-digital conversion integrated circuit of claim 1, wherein: the global counter (3) is an addition counter and has the function of calculating the number of rising edges of a reference clock between the rising edges of the start signal pulse and the stop signal pulse, namely a high-section time interval; the global counter can be implemented by various counters, such as a synchronous addition counter and an asynchronous addition counter, wherein the adder can be composed of a T flip-flop, a D flip-flop and a JK flip-flop and a digital logic gate.

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