CN106463542A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN106463542A
CN106463542A CN201580027849.0A CN201580027849A CN106463542A CN 106463542 A CN106463542 A CN 106463542A CN 201580027849 A CN201580027849 A CN 201580027849A CN 106463542 A CN106463542 A CN 106463542A
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groove
insulating film
gate insulating
semiconductor substrate
semiconductor
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CN106463542B (zh
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西胁克彦
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Denso Corp
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Toyota Motor Corp
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Abstract

半导体装置(1)具备：第一沟槽(611)，其被形成在半导体基板(10)表面上；第二沟槽(612)，其被形成在半导体基板(10)的表面上，并且在对半导体基板(10)的表面进行俯视观察时，在与第一沟槽(611)不同的方向上延伸且与第一沟槽(611)相交。此外，半导体装置(1)具备：栅极绝缘膜(62)，其覆盖第一沟槽(611)与第二沟槽(612)的内表面以及交叉部(30)的内表面(301)；栅电极(63)，其被形成在第一沟槽(611)与所述第二沟槽(612)内，并且隔着栅极绝缘膜(62)而与半导体基板(10)对置。此外，半导体装置(1)具备n型发射区(24)，其被形成在半导体基板(10)内，且在半导体基板(10)的表面上露出，并与第一沟槽(611)内的栅极绝缘膜(62)相接，并且与形成在第一沟槽(611)和第二沟槽(612)的交叉部(30)的内表面(301)上的栅极绝缘膜(62)不相接。

Description

半导体装置
技术领域
本说明书中所公开的技术涉及一种半导体装置。
背景技术
在专利文献1(日本特开2013-232533号公报)中，公开了一种具备半导体基板和形成在半导体基板上的多个沟槽的半导体装置。在专利文献1的半导体装置中，沟槽被形成为格子状。
发明内容
发明所要解决的课题
在专利文献1的半导体装置中，有时为了形成沟道而所需的阈值电压会由于栅电极的位置而产生差异。因此本说明书的目的在于，提供一种能够实现阈值电压的稳定的半导体装置。
用于解决课题的方法
本说明书中所公开的半导体装置具备：第一沟槽，其被形成在半导体基板的表面上；第二沟槽，其被形成在所述表面上，并且在对所述表面进行俯视观察时在与所述第一沟槽不同的方向上延伸且与第一沟槽相交。此外，半导体装置具备：栅极绝缘膜，其覆盖所述第一沟槽与所述第二沟槽的内表面、以及所述第一沟槽与所述第二沟槽的交叉部的内表面；栅电极，其被形成在所述第一沟槽与所述第二沟槽内，并且隔着栅极绝缘膜而与所述半导体基板对置。此外，半导体装置具备：第一导电型的第一半导体区域，其被形成在所述半导体基板内，且在所述表面上露出，并与所述第一沟槽内的所述栅极绝缘膜相接，并且与形成在所述第一沟槽和所述第二沟槽的交叉部的内表面上的所述栅极绝缘膜不相接。此外，半导体装置具备第二导电型的第二半导体区域，其被形成在所述半导体基板内，并与和所述第一半导体区域相比靠较深侧的所述第一沟槽内的所述栅极绝缘膜相接。此外，半导体装置具备第一导电型的第三半导体区域，其被形成在所述半导体基板内，并与和所述第二半导体区域相比靠较深侧的所述第一沟槽内的所述栅极绝缘膜相接，并且通过所述第二半导体区域而与所述第一半导体区域分离。
在第一沟槽与第二沟槽相交的交叉部处，沟槽与周围的部分相比而较深。然而，根据上述的结构，由于第一半导体区域与形成于交叉部处的栅极绝缘膜不相接，因此能够避免由于交叉部的较深的沟槽所造成的影响。其结果为，能够实现半导体装置的阈值电压的稳定。
附图说明
图1为半导体装置的俯视图。
图2为图1的Ⅱ-Ⅱ剖视图。
图3为图1的Ⅲ-Ⅲ剖视图。
图4为图1的主要部分Ⅳ的放大图。
图5为其他实施方式所涉及的半导体装置的俯视图。
图6为另外的其他实施方式所涉及的半导体装置的主要部分的放大图。
图7为另外的其他实施方式所涉及的半导体装置的俯视图。
具体实施方式
在以下列举欲进行说明的实施方式的主要特征。另外，在以下所记载的技术要素为各自独立的技术要素，且为以单独或各种组合的方式来发挥技术上的有用性的技术要素。
(特征1)
半导体装置可以具有多个第一沟槽和多个第二沟槽。在对半导体基板的表面进行俯视观察时，可以将多个第一沟槽和多个第二沟槽配置为格子状。第一半导体区域可以不与第二沟槽内的栅极绝缘膜相接。
(特征2)
在对半导体基板的表面进行俯视观察时，由第一沟槽和第二沟槽形成的格子可以被配置成交错状。
下面，参照附图来对实施方式进行说明。图1至3所示的半导体装置1为IGBT(Insulated Gate Bipolar Transistor：绝缘栅双极性晶体管)。半导体装置1由半导体基板10、电极以及绝缘层等构成。
半导体基板10由硅(Si)形成。在其他示例中，半导体基板10也可以由碳化硅(SiC)或氮化镓(GaN)等形成。如图2所示，在半导体基板10的内部形成有发射区24(相当于第一半导体区域的一个示例)、接触区25、体区23(相当于第二半导体区域的一个示例)、漂移区22(相当于第三导电型的一个示例)、以及集电区21。更加详细而言，半导体基板10从背面侧起而依次具备p型集电区21、形成在集电区21之上的n型漂移区22、形成在漂移区22之上的p型体区23、形成在体区23之上的n型发射区24、形成在体区23之上的p型接触区25。集电区21在半导体基板10的背面上露出。集电区21通过漂移区22而与体区23分离。漂移区22通过体区23而与发射区24分离。发射区24在半导体10的表面上露出。接触区25在半导体基板10的表面上露出。接触区25的p型杂质浓度与体区23的p型杂质浓度相比而较高。另外，n型相当于第一导电型的一个示例，p型相当于第二导电型的一个示例。
在半导体基板10的表面上形成有表面电极70。表面电极70与发射区24以及接触区25连接。在半导体基板10的背面上形成有背面电极72。背面电极72与集电区21连接。
如图1所示，在半导体基板10的表面上形成有多个沟槽61(即，多个第一沟槽611和多个第二沟槽612)。在对半导体基板10的表面进行俯视观察时，第一沟槽611沿着x方向(第一方向)而延伸。在对半导体基板10的表面进行俯视观察时，多个第一沟槽611以在y方向隔开间隔的方式而并排形成。另外，y方向为与x方向不同的方向，更加详细而言，y方向为相对于x方向而正交的方向。多个第一沟槽611平行地延伸。第二沟槽612在y方向(第二方向)上延伸。多个第二沟槽612以在x方向隔开间隔的方式而并排形成。多个第二沟槽612平行地延伸。在y方向上相邻的两个第二沟槽612彼此在x方向上相互错开。在两个第一沟槽611之间形成有第二沟槽612。各第二沟槽612在其两端部(图1的交叉部30)处与第一沟槽611相交。沟槽61从交叉部30起向三个方向延伸。通过第一沟槽611和第二沟槽612而将半导体基板10的表面划分为格子状。由第一沟槽611和第二沟槽612所形成的格子被配置成交错状。在以下，将被划分为格子状的区域称为元件区20。
如图1所示，发射区24被形成在元件区20中。发射区24与第二沟槽612邻接。发射区24沿着第二沟槽612而形成。发射区24沿着y方向(第二方向)而延伸。在第二沟槽612的x方向的两侧处形成有发射区24。第二沟槽612的两侧的发射区24夹着第二沟槽612而被对称地形成。发射区24不与第一沟槽611邻接。此外，发射区24不与交叉部30邻接。即，发射区24以与第一沟槽611以及交叉部30分离的方式而形成。接触区25以与第一沟槽611、第二沟槽612以及交叉部30相接的方式而形成。即，在发射区24与第一沟槽611之间形成有接触区25。
如图2以及图3所示，在进行剖面观察时，沟槽61(第一沟槽611以及第二沟槽612)从半导体基板10的表面起向z方向(深度方向)延伸。第一沟槽611贯穿发射区24以及体区23而延伸至漂移区22。第二沟槽612贯穿接触区25以及体区23而延伸至漂移区22。如图3所示，在交叉部30处，与交叉部30的外侧相比，沟槽61的深度较深。这是由于，当在半导体装置10的制造工序中通过干式蚀刻而形成沟槽61时，被供给至交叉部30的蚀刻气体的量与交叉部30的外侧的沟槽61相比而较多。在沟槽61的内表面上形成有栅极绝缘膜62。栅极绝缘膜62覆盖沟槽61的内表面整体。在各沟槽61的内部(栅极绝缘膜62的内侧)形成有栅电极63。栅电极63被配置于第一沟槽611的内部以及第二沟槽612的内部。栅电极63隔着栅极绝缘膜62而与半导体基板10对置。栅电极63通过层间绝缘膜74而与表面电极70绝缘。此外，如图4所示，栅极绝缘膜62覆盖第一沟槽611和第二沟槽612的内表面、以及第一沟槽611与第二沟槽612的交叉部30的内表面。在本实施方式中，交叉部30的内表面301相当于第一沟槽611的端部与第二沟槽612的端部相接的部分(角部)的内表面。此外，交叉部30的内表面301相当于第一沟槽611中的、与朝向第一沟槽611延伸的第二沟槽612对置的部分的内表面。该内表面301面对交叉部30。
在栅极绝缘膜62上，相接有接触区25、发射区24、体区23以及漂移区22。如图2所示，发射区24在半导体基板10的表面附近处与栅极绝缘膜62相接。如图3所示，接触区25在半导体基板10的表面附近处与栅极绝缘膜62相接。如图1所示，接触区25与第一沟槽611、第二沟槽612及交叉部30内的栅极绝缘膜62相接。此外，发射区24与第二沟槽612内的栅极绝缘膜62相接。发射区24与第一沟槽611以及交叉部30内的栅极绝缘膜62不相接。如图2所示，体区23在发射区24的下部处，与和发射区24相比靠深侧的栅极绝缘膜62相接。此外，如图3所示，体区23在接触区25的下部处，与和接触区25相比靠深侧的栅极绝缘膜62相接。漂移区22在体区23的下部处，与和体区23相比靠深侧的栅极绝缘膜62相接。
根据具备上述结构的半导体装置1，当将沟槽61的内部的栅电极63设为导通电位(阈值以上的电位)时，在栅极绝缘膜62的附近处的体区23中，会沿着沟槽61的深度方向而形成沟道。此外，当向表面电极70和背面电极72之间施加电压时，将从发射区24经由沟道和漂移区22而向集电区21流动有电子。此外，从集电区21经由漂移区22和体区23而向接触区25流动有空穴。通过这种方式，从而从集电区21向发射区24流动有电流。即，IGBT导通。
如上所述，在交叉部30中，沟槽61与周围的部分相比而较深。当IGBT导通时，电子易于在沟槽61的附近处流动。因此，当沟槽61较深的交叉部30的附近处成为了电子流动的主要路径时，在沟槽61较深的位置(即，交叉部30附近)和沟槽61较浅的位置(从交叉部离开的位置)处，阈值(即，形成沟道所需的栅极电位)会产生差异，从而IGBT的阈值偏差将会变大。对此，在上述的半导体装置1中，发射区24与形成于交叉部30处的栅极绝缘膜62不邻接。因此，在半导体装置1中，发射区24的下部成为电子的主要路径，从而在交叉部30的附近处几乎不会流动有电子。由此，能够避免交叉部30的较深的沟槽61的影响。其结果为，能够抑制半导体装置1的阈值的偏差，从而能够实现阈值的稳定。此外，能够实现开关特性的稳定。
此外，当交叉部30的附近处成为电子流动的主要路径时，在交叉部30的附近处电子的流动易于集中。然而，在上述的半导体装置1中，由于发射区24与交叉部30不邻接，因此能够抑制交叉部30的附近处的电流的集中。此外，由于发射区24隔着第二沟槽612而被对称地配置，因此电流会均匀地流动。由此，能够抑制交叉部30处的局部性的发热。此外，能够在发射区24与交叉部30分离的部分处确保接触区25。由此，能够确保空穴流动的区域，并且能够实现高速开关。
此外，在上述的半导体装置1中，以将多个格子(元件区30)配置成交错状的方式而具备多个第一沟槽611以及多个第二沟槽612。在这种结构中，第一沟槽611和第二沟槽612的深度有时会产生偏差。在沿着第一沟槽611和第二沟槽612双方而形成有电子的流动的主要路径的结构中，由于第一沟槽611和第二沟槽612的深度的差异，有时在沿着第一沟槽611的电子的路径和沿着第二沟槽的电子的路径上，阈值会产生偏差。然而，在上述的半导体装置1中，发射区24与第一沟槽611内的栅极绝缘膜62不相接。由此，能够避免第一沟槽611和第二沟槽612的深度的差所造成的影响，从而能够实现阈值电压的稳定。
虽然在上文中对一个实施方式进行了说明，但具体的方式并不限定于上述实施方式。在以下的说明中，对与上述的说明中的结构相同的结构，标注同样的符号并省略说明。
虽然在上述的实施方式中，多个第二沟槽612被配置成交错状，但并不限定于该结构。在其他实施方式中，如图5所示，也可以使多个第二沟槽612在y方向上(第二方向)对齐而形成。多个第二沟槽612排列为直线状。沟槽61从交叉部30向四个方向延伸。
此外，虽然在上述实施方式中，发射区24与第二沟槽612邻接，并且未与第一沟槽611邻接，但是不限定于该结构。在其他实施方式中，如图5所示，也可以使发射区24与第一沟槽611以及第二沟槽612分别邻接。与第一沟槽611邻接的发射区24以与第二沟槽612分离的方式而形成。与第二沟槽612邻接的发射区24以与第一沟槽611分离的方式而形成。
此外，虽然在上述实施方式中，发射区24夹着第二沟槽612而对称地形成，但不限定于该结构，也可以以非对称的方式而形成。在其他实施方式中，如图6所示，在第二沟槽612的x方向上的一侧形成有发射区24，而在另一侧未形成有发射区24。在这种结构中，流动有电流的部分会分散，从而能够抑制电流的集中。
此外，虽然在上述实施方式中，多个沟槽61被配置为格子状，但是并不限定于该结构。在其他的实施方式中，如图7所示，也可以将多个沟槽61配置为多边形形状。在图7所示的示例中，多个沟槽61被配置为六边形形状。多个沟槽61被形成为蜂巢状。在被配置为六边形的沟槽61彼此相交的部分处形成有交叉部30。
此外，虽然在上述实施方式中，在半导体基本10上形成有IGBT，但也可以代替IGBT而形成MOSFET(Metal Oxide Semiconductor Field Effect Transistor：金属氧化物场效应晶体管)。在该情况下，例如，在图1至3的结构中，能够采用代替集电区21而形成n型高浓度区域并且使该高浓度区域与背面电极72导通的结构。
以上，虽然对本发明的具体示例进行了详细说明，但这些仅是示例，并不对权利要求书进行限定。在权利要求书所记载的技术中，包括对上文所示的具体示例进行了各种变形、变更的技术。本说明书或附图中所说明的技术要素为以单独或各种组合的方式来发挥技术上的有用性的技术，其并不限定于申请时权利要求中所记载的组合。此外，本说明书或附图中所例示的技术为同时实现多个目的的技术，而实现其中一个目的本身也具有技术上的有用性。
符号说明
1：半导体装置
10：半导体基板
20：元件区
21：集电区
22：漂移区
23：体区
24：发射区
25：接触区
30：交叉部
61：沟槽
62：栅极绝缘膜
63：栅电极
70：表面电极
72：背面电极
74：层间绝缘膜

Claims (3)

1.一种半导体装置，具备：
第一沟槽，其被形成在半导体基板的表面上；
第二沟槽，其被形成在所述表面上，并且在对所述表面进行俯视观察时在与所述第一沟槽不同的方向上延伸且与第一沟槽相交；
栅极绝缘膜，其覆盖所述第一沟槽与所述第二沟槽的内表面、以及所述第一沟槽与所述第二沟槽的交叉部的内表面；
栅电极，其被形成在所述第一沟槽与所述第二沟槽内，并且隔着栅极绝缘膜而与所述半导体基板对置；
第一导电型的第一半导体区域，其被形成在所述半导体基板内，且在所述表面上露出，并与所述第一沟槽内的所述栅极绝缘膜相接，并且与覆盖所述第一沟槽和所述第二沟槽的交叉部的内表面的所述栅极绝缘膜不相接；
第二导电型的第二半导体区域，其被形成在所述半导体基板内，并与和所述第一半导体区域相比靠较深侧的所述第一沟槽内的所述栅极绝缘膜相接；
第一导电型的第三半导体区域，其被形成在所述半导体基板内，并与和所述第二半导体区域相比靠较深侧的所述第一沟槽内的所述栅极绝缘膜相接，并且通过所述第二半导体区域而与所述第一半导体区域分离。
2.如权利要求1所述的半导体装置，其中，
具有多个所述第一沟槽和多个所述第二沟槽；
在对半导体基板的表面进行俯视观察时，多个所述第一沟槽和多个所述第二沟槽被配置为格子状；
所述第一半导体区域与所述第二沟槽内的栅极绝缘膜不相接。
3.如权利要求2所述的半导体装置，其中，
在对半导体基板的表面进行俯视观察时，由所述第一沟槽和所述第二沟槽形成的格子被配置成交错状。
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