CN106298725A - 串联二极管的封装结构 - Google Patents
串联二极管的封装结构 Download PDFInfo
- Publication number
- CN106298725A CN106298725A CN201610848725.5A CN201610848725A CN106298725A CN 106298725 A CN106298725 A CN 106298725A CN 201610848725 A CN201610848725 A CN 201610848725A CN 106298725 A CN106298725 A CN 106298725A
- Authority
- CN
- China
- Prior art keywords
- pin
- backlight unit
- diode chip
- encapsulating structure
- pole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000003822 epoxy resin Substances 0.000 claims description 9
- 229920000647 polyepoxide Polymers 0.000 claims description 9
- 238000009413 insulation Methods 0.000 claims description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910000831 Steel Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical group [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000010959 steel Substances 0.000 claims description 3
- 238000010923 batch production Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 4
- 238000010276 construction Methods 0.000 abstract description 3
- 230000005855 radiation Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Device Packages (AREA)
Abstract
Description
Claims (10)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610848725.5A CN106298725A (zh) | 2016-09-23 | 2016-09-23 | 串联二极管的封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201610848725.5A CN106298725A (zh) | 2016-09-23 | 2016-09-23 | 串联二极管的封装结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN106298725A true CN106298725A (zh) | 2017-01-04 |
Family
ID=57714998
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201610848725.5A Pending CN106298725A (zh) | 2016-09-23 | 2016-09-23 | 串联二极管的封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN106298725A (zh) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107452704A (zh) * | 2017-09-06 | 2017-12-08 | 深圳市矽莱克半导体有限公司 | 串联封装的半导体装置及其引线框架 |
CN107464799A (zh) * | 2017-09-21 | 2017-12-12 | 深圳市矽莱克半导体有限公司 | 单相桥式整流电路和三相桥式整流电路 |
CN107546209A (zh) * | 2017-09-28 | 2018-01-05 | 深圳市矽莱克半导体有限公司 | 串联封装的碳化硅衬底及氮化镓衬底半导体装置 |
CN107768365A (zh) * | 2017-09-30 | 2018-03-06 | 深圳市矽莱克半导体有限公司 | 两个不同元器件串联封装的半导体装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002261230A (ja) * | 2001-02-28 | 2002-09-13 | Nippon Inter Electronics Corp | フルモールド型半導体装置及びそれに使用するリードフレーム |
US20020168899A1 (en) * | 2001-05-11 | 2002-11-14 | Yoshifumi Matsumoto | Functional connector |
CN201523329U (zh) * | 2009-11-02 | 2010-07-07 | 绍兴科盛电子有限公司 | 直插式双二极管小电流整流模块 |
CN206179859U (zh) * | 2016-09-23 | 2017-05-17 | 陈文彬 | 串联二极管的封装结构 |
-
2016
- 2016-09-23 CN CN201610848725.5A patent/CN106298725A/zh active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002261230A (ja) * | 2001-02-28 | 2002-09-13 | Nippon Inter Electronics Corp | フルモールド型半導体装置及びそれに使用するリードフレーム |
US20020168899A1 (en) * | 2001-05-11 | 2002-11-14 | Yoshifumi Matsumoto | Functional connector |
CN201523329U (zh) * | 2009-11-02 | 2010-07-07 | 绍兴科盛电子有限公司 | 直插式双二极管小电流整流模块 |
CN206179859U (zh) * | 2016-09-23 | 2017-05-17 | 陈文彬 | 串联二极管的封装结构 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107452704A (zh) * | 2017-09-06 | 2017-12-08 | 深圳市矽莱克半导体有限公司 | 串联封装的半导体装置及其引线框架 |
CN107464799A (zh) * | 2017-09-21 | 2017-12-12 | 深圳市矽莱克半导体有限公司 | 单相桥式整流电路和三相桥式整流电路 |
CN107546209A (zh) * | 2017-09-28 | 2018-01-05 | 深圳市矽莱克半导体有限公司 | 串联封装的碳化硅衬底及氮化镓衬底半导体装置 |
CN107768365A (zh) * | 2017-09-30 | 2018-03-06 | 深圳市矽莱克半导体有限公司 | 两个不同元器件串联封装的半导体装置 |
CN107768365B (zh) * | 2017-09-30 | 2019-06-11 | 深圳市矽莱克半导体有限公司 | 两个不同元器件串联封装的半导体装置 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20170816 Address after: 518000, A, building 611, south-east square International Plaza, Shek ha ha North Street, Futian District, Guangdong, Shenzhen Applicant after: Shenzhen silicon Lake Semiconductor Co., Ltd. Address before: 518000 Guangdong, Shenzhen, Futian District, No. 3013 Yitian Road, South Plaza, building A room, Room 302 Applicant before: Chen Wenbin Applicant before: Luo Xiaochun |
|
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170104 |