CN108321151A - 芯片封装组件及其制造方法 - Google Patents
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Abstract
本发明提供了一种芯片封装组件及其制造方法,通过在位于芯片承载盘周围的引脚上安装芯片,以使诸如二极管这样的器件在封装组件的内部与其它芯片电连接,提高的芯片的集成度,减小了***电路的体积。
Description
技术领域
本发明涉及半导体技术领域,尤其涉及一种芯片封装组件及其制造方法。
背景技术
目前的QFN封装中所采用的引线框架如图1所示,其包括位于中间的承载盘11和位于承载盘11周围的引脚12。为了提高封装组件的集成度,在QFN封装中,通常会封装装多块芯片(裸芯片),但所封装的芯片只叠层或平铺在引线框架中间的承载盘上,如图2所示,芯片21与芯片22叠层安装在承载盘11上,芯片22上电极通过导线221电连接到芯片21上,芯片21上的电极在通过导线211电连接到引脚12上,或者如图3所示,芯片21与芯片22平铺在承载盘11上,芯片21与芯片22上的电极分别通过导线211与221电连接到引脚12上。
然而,在某些应用上,希望芯片上的I/O能串联二极管等芯片,以用于给***电路做驱动或保护IC的端口,这时,如图2与图3所述QFN无法将控制芯片或MOS管芯片与二极管芯片集成在同一封装体内,而是只能在封装好的芯片***电路和独立的二极管器件串联。
发明内容
有鉴于此,本发明提供了一种芯片封装组件及其制造方法,以实现将二极管与其它芯片一起集成在封装体的内部,以实现二极管与其它芯片在封装体内部的串联连接。
一种芯片封装组件,其特在于,包括:
引线框架,具有承载盘和位于所述承载盘周围的多个引脚,
第一芯片,所述第一芯片位于所述承载盘之上,
至少一个第二芯片,所述第二芯片位于所述引脚之上。
优选地,每一个所述第二芯片位于一个所述引脚上。
优选地,所述第二芯片的第一表面上具有第一电极,所述第二芯片的第二表面上具有第二电极,
所述第二芯片第二表面朝向所述引脚的第一表面,所述第二电极与所述引脚的第一表面电连接,
所述第一电极通过第一导线与所述第一芯片电连接,以将所述第二芯片与第一芯片串联连接。
优选地,所述第一芯片的第一表面为有源面,所述第一芯片的第二表面贴在所述承载盘的第一表面上,
所述第一电极通过第一导线与所述有源面上的一个电极电连接,所述有源面上的剩余电极通过第二导线与除用于承载所述第二芯片外的所述引脚的第一表面电连接。
优选地,所述第二芯片为二极管,
所述第一电极为二极管的阳极和阴极中的一个,所述第二电极为二极管的阳极和阴极中的另一个。
优选地,所述二极管为瞬态抑制二极管或肖特基二极管。
优选地,所述的芯片封装组件还包括用于包封所述第一芯片与第二芯片的塑封体,
所述引脚的第二表面和所述承载盘的第二表面裸露在所述塑封体的表面。
优选地,所述芯片封装组件为DFN或QFN封装。
一种芯片封装组件的制造方法,其特在于,包括:
在引线框架的承载盘上安装第一芯片,
在引线框架的引脚上安装第二芯片,所述引脚位于所述承载盘的周围。
优选地,所述的制造方法还包括在安装所述第一芯片与第二芯片之前,根据所述第二芯片的尺寸设计所述引脚的结构与尺寸。
优选地,将所述第二芯片采用导电层贴装在一个所述引脚上。
优选地,对所述第一芯片和第二芯片进行DFN或QFN封装。
由上可见,在本发明提供的芯片封装组件及其制造方法中,利用在位于芯片承载盘周围的引脚上安装芯片,从而可以使诸如二极管这样的器件在封装组件的内部与其它芯片电连接,提高的芯片的集成度,减小了***电路的体积。
附图说明
通过以下参照附图对本发明实施例的描述,本发明的上述以及其他目的、特征和优点将更为清楚,在附图中:
图1为QFN封装组件中的引线框架的结构示意图;
图2为现有技术实现的一种多芯片集成的QFN封装组件结构示意图;
图3为现有技术实现的另一种多芯片集成的QFN封装组件结构示意图;
图4为依据本发明实施例提供的芯片封装组件的剖面结构示意图;
图5为依据本发明实施例提供的芯片封装组件的俯视图。
具体实施方式
以下将参照附图更详细地描述本发明。在各个附图中,相同的组成部分采用类似的附图标记来表示。为了清楚起见,附图中的各个部分没有按比例绘制。此外,可能未示出某些公知的部分。为了简明起见,可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本发明的许多特定的细节,例如每个组成部分的结构、材料、尺寸、处理工艺和技术,以便更清楚地理解本发明。但正如本领域的技术人员能够理解的那样,可以不按照这些特定的细节来实现本发明。此外,在本申请中,芯片是指半导体裸芯片。
图4为依据本发明实施例提供的芯片封装组件的剖面结构示意图,图5为依据本发明实施例提供的芯片封装组件的俯视图,下面将结合图4与图5来具体阐述本发明。
本发明提供的芯片封装组件主要包括引线框架、至少一个第一芯片、至少一个第二芯片。其中,所述的引线框架由承载盘11和位于承载盘12周围的多个引脚12构成,多个引脚12可以对称的排列在承载盘11的四边的,也可以仅对称的排列早承载盘11相对的两边。
第一芯片21位于第一承载盘的之上,其包括相对的第一表面与第二表面,第一芯片21的第一表面为有源面,第二表面粘贴在承载盘11上。第二芯片31位于引脚12之上,具体的,每一个第一芯片31均位于一个引脚12上,引脚12用于引出第二芯片31的一个电极,以使该电极与外部其它器件或电路电连接,引脚12还用于承载第二芯片31,即引脚12为第二芯片31提供机械支撑。
第二芯片31具有相对的第一表面与第二表面,其第一表面上具有第一电极,第二表面上具有第二电极,第二芯片31以第二表面朝向引脚12的第一表面的方式贴装在引脚12上,使得第二电极与引脚12的第一表面电连接,而第二芯片21的第一电极则通过导线311与第一芯片21的有源面上的电极电连接,第一芯片的有源面上的剩余电极通过导线211与除用于承载第二芯片21外的引脚12的第一表面电连接。在芯片封装结构中,第二芯片31与第二芯片21串联连接。
在本发明实施例提供的芯片封装组件中,第二芯片31为二极管,则所述的第一电极为二极管的阳极和阴极中的一个,所述第二电极为二极管的阳极和阴极中的另一个。第二芯片31可以具体为瞬态抑制二极管或肖特基二极管。第一芯片21可以为MOS管,如功率MOS管,也可以为控制芯片。
此外,所述的芯片封装组件还进一步包括塑封体41,塑封体41用于包封第一芯片21和第二芯片31,且引脚12第二表面和承载盘的第二表面均裸露在塑封体41的表面,以作为所述芯片封装组件与外部电连接的外引脚。
根据引脚12在承载盘11周围的排列情况,所述芯片封装组件可以为DFN或QFN封装。且在所述芯片封装组件中,还可以包括第三芯片(图4和图5中未画出),所述第三芯片堆叠在第一芯片21之上或者与第一芯片21一起平铺在承载盘11上。若第三芯片堆叠在第一芯片21之上,则所述第三芯片上的电极通过导线先电连接到第一芯片21的第一表面上,然后再通过导线由第一表面引出到引脚12上,若第三芯片平铺在承载盘11上,则第三芯片上的电极直接通过导线与引脚12电连接。在所述芯片封装组件中,还可包括多个第二芯片,每一个第二芯片安装在一个引脚上。
此外,本发明还提供了一种芯片封装组件的制造方法,该方法主要包括在引线框架的承载盘上安装第一芯片,而在引线框架的引脚上安装第二芯片,所述引脚位于承载盘的周围。所述制造方法还进一步包括形成所述引线框架,在形成所述引线框架时,根据所述第二芯片的尺寸设计所述引脚的结构与尺寸,以使得所述引脚与所述第二芯片相匹配。可以采用DFN或QFN封装来对第一芯片和第二芯片进行封装。具体的,在安装第二芯片的过程中,可以使第二芯片通过导电层贴装在所述引脚上,使得所述引脚既用作所述第二芯片与外部电路或器件电连接的触点,又作为所述第二芯片的机械支撑体,以承载所述第二芯片。
由上可见,在本发明提供的芯片封装组件及其制造方法中,利用在位于芯片承载盘周围的引脚上安装芯片,从而可以使诸如二极管这样的器件在封装组件的内部与其它芯片电连接,提高的芯片的集成度,减小了***电路的体积。
依照本发明的实施例如上文所述,这些实施例并没有详尽叙述所有的细节,也不限制该发明仅为所述的具体实施例。显然,根据以上描述,可作很多的修改和变化。本说明书选取并具体描述这些实施例,是为了更好地解释本发明的原理和实际应用,从而使所属技术领域技术人员能很好地利用本发明以及在本发明基础上的修改使用。本发明仅受权利要求书及其全部范围和等效物的限制。
Claims (12)
1.一种芯片封装组件,其特在于,包括:
引线框架,具有承载盘和位于所述承载盘周围的多个引脚,
第一芯片,所述第一芯片位于所述承载盘之上,
至少一个第二芯片,所述第二芯片位于所述引脚之上。
2.根据权利要求1所述的芯片封装组件,其特征在于,每一个所述第二芯片位于一个所述引脚上。
3.根据权利要求2所述的芯片封装组件,其特征在于,所述第二芯片的第一表面上具有第一电极,所述第二芯片的第二表面上具有第二电极,
所述第二芯片第二表面朝向所述引脚的第一表面,所述第二电极与所述引脚的第一表面电连接,
所述第一电极通过第一导线与所述第一芯片电连接,以将所述第二芯片与第一芯片串联连接。
4.根据权利要求3所述的芯片封装组件,其特征在于,所述第一芯片的第一表面为有源面,所述第一芯片的第二表面贴在所述承载盘的第一表面上,
所述第一电极通过第一导线与所述有源面上的一个电极电连接,所述有源面上的剩余电极通过第二导线与除用于承载所述第二芯片外的所述引脚的第一表面电连接。
5.根据权利要求3所述的芯片封装组件,其特征在于,所述第二芯片为二极管,
所述第一电极为二极管的阳极和阴极中的一个,所述第二电极为二极管的阳极和阴极中的另一个。
6.根据权利要求5所述的芯片封装组件,其特征在于,所述二极管为瞬态抑制二极管或肖特基二极管。
7.根据权利要求4所述的芯片封装组件,其特征在于,还包括用于包封所述第一芯片与第二芯片的塑封体,
所述引脚的第二表面和所述承载盘的第二表面裸露在所述塑封体的表面。
8.根据权利要求1所述的芯片封装组件,其特征在于,所述芯片封装组件为DFN或QFN封装。
9.一种芯片封装组件的制造方法,其特在于,包括:
在引线框架的承载盘上安装第一芯片,
在引线框架的引脚上安装第二芯片,所述引脚位于所述承载盘的周围。
10.根据权利要求9所述的制造方法,其特征在于,还包括在安装所述第一芯片与第二芯片之前,根据所述第二芯片的尺寸设计所述引脚的结构与尺寸。
11.根据权利要求9所述的制造方法,其特征在于,将所述第二芯片采用导电层贴装在一个所述引脚上。
12.根据权利要求9所述的制造方法,其特征在于,对所述第一芯片和第二芯片进行DFN或QFN封装。
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