CN106233452A - 由局部硅外延籽晶形成的体晶片中的隔离半导体层 - Google Patents

由局部硅外延籽晶形成的体晶片中的隔离半导体层 Download PDF

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CN106233452A
CN106233452A CN201580018939.3A CN201580018939A CN106233452A CN 106233452 A CN106233452 A CN 106233452A CN 201580018939 A CN201580018939 A CN 201580018939A CN 106233452 A CN106233452 A CN 106233452A
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layer
isolation
substrate
top surface
crystal
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CN106233452B (zh
CN106233452B8 (zh
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D·N·卡罗瑟斯
J·R·德博尔
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在所描述的示例中，一种集成电路(100)可以通过在基于单晶硅的衬底(102)中的隔离槽(118)内形成埋入式隔离层(124)来形成。在埋入式隔离层(124)处的衬底(102)的裸露侧表面(132)被电介质侧壁(136)覆盖。籽晶沟槽(140)穿过埋入式隔离层(124)形成以曝露出衬底(102)。基于单晶硅的籽晶层(144)穿过籽晶沟槽(140)形成并且延伸高于埋入式隔离层(124)的顶表面(126)。硅基非晶层(150)被形成为与籽晶层(144)接触。保护层(152)被形成在非晶层(146)上方。辐射感应的再结晶工艺将非晶层(150)转换为与籽晶层(144)对齐的单晶层。保护层(152)被移除并且单晶层被平坦化，留下在埋入式隔离层(124)上方的隔离半导体层。

Description

由局部硅外延籽晶形成的体晶片中的隔离半导体层
技术领域
本公开总体涉及集成电路，并且更特别地涉及集成电路中的隔离半导体层。
背景技术
在介电隔离的硅中具有一些电路或组件的集成电路可以在绝缘体上硅(SOI)晶片上形成。SOI晶片比体晶片和外延晶片更加昂贵，不合乎期望地增加了集成电路的成本。可替代地，这些电路或组件可以在二氧化硅的埋入式层上方形成。形成埋入式二氧化硅层的方法(诸如注入氧)在提供埋入式氧化物层的期望侧面和竖直维度控制方面存在问题，并且不合乎期望地增加晶片上的应力，因此导致光刻操作期间的问题。在埋入式氧化物层上方形成器件质量硅(device quality silicon)的薄层也存在问题。
发明内容
在所描述的示例中，一种集成电路可以通过在基于单晶硅的衬底中形成隔离槽并且用隔离电介质材料填充隔离槽以形成埋入式隔离层而形成，该埋入式隔离层的顶表面比相邻衬底的顶表面低。在埋入式隔离层处的衬底的裸露的侧表面被电介质侧壁覆盖。籽晶沟槽穿过埋入式隔离层而形成以使衬底裸露。基于单晶硅的籽晶层穿过籽晶沟槽而形成，并且延伸高于埋入式隔离层的顶表面。硅基非晶层被形成在衬底和埋入式隔离层上方并与籽晶层接触。保护层被形成在非晶层的上方。辐射感应再结晶工艺加热埋入式隔离层上方的非晶层并将其转换成与籽晶层对齐的单晶层。保护层被去除，并且非晶层被从衬底上方去除，留下埋入式隔离层上方的隔离半导体层。
附图说明
图1A至图1S是以连续的制造阶段描绘的示例集成电路的截面。
图2A至图2G是图1A至图1S中的集成电路的截面，描绘了用于形成单晶区和非晶区并且用于随后的辐射感应再结晶工艺的可替代方法。
具体实施方式
以下文献描述了相关的主题并且通过引用整体合并于此：申请号US 14/301,765；申请号US 14/301,827；以及申请号US 14/301,848。
集成电路可以通过在基于单晶硅的衬底中形成隔离槽并且用隔离电介质材料填充隔离槽以形成埋入式隔离层而形成，该埋入式隔离层具有比相邻衬底的顶表面低的顶表面。在埋入式隔离层处裸露的衬底的侧表面被电介质侧壁覆盖。籽晶沟槽穿过埋入式隔离层而形成以使衬底裸露。基于单晶硅的籽晶层穿过籽晶沟槽而形成并且延伸高于埋入式隔离层的顶表面。硅基非晶层被形成在衬底和埋入式隔离层上方并且与籽晶层接触。保护层在非晶层的上方形成。辐射感应再结晶工艺加热埋入式隔离层上方的非晶层并将其转换为与籽晶层对齐的单晶层。保护层被去除，并且非晶层被从衬底上方去除，留下埋入式隔离层上方的隔离半导体层。
图1A至图1S是以连续的制造阶段描绘的示例集成电路的截面。参考图1，集成电路100被形成在硅基单晶半导体材料的衬底102上。衬底102可以是体硅晶片或具有外延层的硅晶片，或适用于形成集成电路100的其他衬底102。阻挡层104被形成在衬底102的顶表面106上方以便为随后的沟槽蚀刻提供蚀刻掩模并在随后的外延工艺中阻挡外延生长。阻挡层104可以包括具有在顶表面106处通过热氧化形成的5纳米至20纳米厚的二氧化硅层108，以及在该二氧化硅层108上通过低压化学气相沉积(LPCVD)工艺形成的50纳米至150纳米厚的氮化硅层110。阻挡层104的其他结构或组分在该示例的范围内。隔离掩模112被形成在阻挡层104上方以曝露出用于隔离半导体层114的区域并覆盖相邻的阻挡层104。例如，用于隔离半导体层114的区域可以具有2微米至200微米的宽度。隔离掩模112可以包括由光刻工艺形成的光刻胶，并且可以包括抗反射层和/或诸如碳化硅或无定形碳的硬掩模材料。作为浅沟槽隔离工艺的一部分，隔离掩模112可以曝露出集成电路100的其他区域以用于场氧化物。
参考图1B，隔离蚀刻工艺116从用于隔离半导体层114的区域中去除阻挡层104并且然后从衬底102中去除半导体材料以形成隔离槽118。例如，在衬底102中，隔离槽118可以具有250纳米至1000纳米的深度。如图1B示意性地描绘，隔离蚀刻工艺116可以是反应离子蚀刻(RIE)工艺。隔离蚀刻工艺116可以是定时的蚀刻以提供隔离槽118的期望深度。隔离掩模112被去除。例如，在至少一个实施例中，隔离掩模112的一部分可以在隔离蚀刻工艺116期间被去除，并且隔离掩模112的剩余部分可以在隔离蚀刻工艺116完成之后(例如通过灰化工艺及之后的湿法清洗工艺)被去除。
参考图1C，隔离电介质材料120被形成在集成电路100的现有顶表面上方，延伸到隔离槽118中并填充隔离槽118。隔离电介质材料120可以主要是二氧化硅，可以主要是氧化铝，或者可以包括不同电介质材料的多个子层。隔离电介质材料120中的二氧化硅可以通过使用硅烷和氧气的常压化学气相沉积(APCVD)工艺、使用原硅酸四乙酯(也被称为四乙氧基硅烷(TEOS))的等离子增强化学气相沉积(PECVD)工艺、高密度等离子体(HDP)工艺和/或基于臭氧的热化学气相沉积(CVD)工艺(也被称为高深宽比工艺(HAPP))而形成。隔离电介质材料120中的氧化铝可以通过在氧气环境中的物理气相沉积(PVD)工艺或CVD工艺而形成。隔离电介质材料120可以通过沉积之后部分回刻的几次重复形成，以改善隔离电介质材料120的顶表面的平坦度。
参考图1D，隔离电介质材料120通过化学机械抛光(CMP)工艺被向下平坦化至阻挡层104，其在图1D中由CMP垫描绘。CMP工艺122可以使用氧化铈浆液，该氧化铈浆液对隔离电介质材料120具有比阻挡层104更高的去除速率。CMP工艺122留下阻挡层104的期望厚度以便在随后的外延工艺期间阻挡外延材料形成。
参考图1E，隔离槽118中的隔离电介质材料120被凹入相邻衬底102的顶表面106之下以形成埋入式隔离层124。例如，该埋入式隔离层的顶表面126可以比衬底102的顶表面106低50纳米至150纳米。隔离电介质材料120可以通过使用如图1E中示意性描绘的定时等离子体蚀刻工艺128或通过另一种方法被凹入。
参考图1F，侧壁材料层130被共形地形成在阻挡层104上方并延伸到埋入式隔离层124上以覆盖在隔离槽118中的高于埋入式隔离层124的顶表面126的衬底102的裸露侧表面132。例如，侧壁材料层130可以包括通过使用双(叔丁基氨基)硅烷(BTBAS)的PECVD工艺形成的氮化硅。可替代地，侧壁材料层130可以包括通过使用TEOS的PECVD工艺形成的二氧化硅。例如，隔离槽118中的衬底102的裸露侧表面132上的侧壁材料层130可以具有10纳米至25纳米的厚度。
参考图1G，可选的各向异性蚀刻工艺134将图1F的侧壁材料层130从阻挡层104的上方去除并从埋入式隔离层124的顶表面126去除，以便在隔离槽118中的衬底102的裸露侧表面132上留下侧壁136。各向异性蚀刻工艺134可以是RIE工艺，类似于用于在金属氧化物半导体(MOS)晶体管制造中形成栅极侧壁间隔物的RIE工艺。可替代地，侧壁136可以通过在隔离槽118中的衬底102的裸露侧表面132处热氧化衬底102中的硅来形成。可替代地，图1F的侧壁材料层130可以完整保留，诸如在该示例的一个版本中，其中侧壁材料层130主要是二氧化硅。
参考图1H，沟槽掩模138被形成在阻挡层104和埋入式隔离层124上方以便曝露出用于穿过埋入式隔离层124的籽晶沟槽140的区域。沟槽掩模138可以包括光刻胶和/或硬掩模材料。沟槽蚀刻工艺142将介电材料从由沟槽掩模138曝露的区域中的埋入式隔离层124去除以形成籽晶沟槽140。沟槽蚀刻工艺142可以是如图1H中示意性描绘的RIE工艺。籽晶沟槽140使衬底102裸露。
参考图1I，图1H中的沟槽掩模138被去除。例如，在至少一个实施例中，沟槽掩模138的一部分可以在沟槽蚀刻工艺142期间被去除，并且沟槽掩模138的剩余部分可以在完成沟槽蚀刻工艺142之后被去除。沟槽掩模138中的光刻胶可以通过灰化工艺以及之后的使用硫酸和过氧化氢的水混合物和/或氢氧化铵和过氧化氢的水混合物的湿法清洗工艺而被去除。沟槽掩模138中的硬掩模材料可以由对阻挡层104和埋入式隔离层124具有选择性的RIE工艺去除。
参考图1J，基于单晶硅的籽晶层144被形成在籽晶沟槽140中的衬底102上，延伸高于埋入式隔离层124的顶表面126。选择性外延工艺可以开始于现场清洁工艺，例如AppliedMaterials SiconiTM(应用材料硅靶视象)清洁工艺，以便从籽晶沟槽140中的衬底102的表面去除任何自然氧化物。选择性外延工艺可以在10托到100托的压强下在衬底102处于700℃到900℃温度的情况下以每分钟100标准立方厘米(100sccm)到300sccm的速度提供二氯硅烷(SiH2Cl2)气体并且以100sccm到300sccm的速度提供氯化氢(HCl)气体，该选择性外延工艺可以提供每分钟5纳米到每分钟50纳米的生长速率。侧壁136防止外延材料形成在隔离槽118中的衬底102的侧表面132上。阻挡层104防止外延材料形成在与隔离槽118相邻的衬底102的顶表面106上。
参考图1K，非选择性外延工艺在阻挡层104和埋入式隔离层124上方形成硅基半导体材料的外延层146，该外延层146与籽晶层144接触。外延层146包括在籽晶层144上的单晶区148和在埋入式隔离层124上与单晶区148侧面接触的非晶区150。非晶区150可以是多晶的或无定形的。非晶区150的厚度可以比埋入式隔离层124上方的单晶层的期望最终厚度厚50纳米到200纳米。例如，对于埋入式隔离层124上方的单晶层具有75纳米的最终期望厚度的情况，非晶区150的厚度可以是125纳米。单晶区148的厚度可以基本等于或大于非晶区150的厚度。非选择性外延工艺可以在10托至100托的压强下和500℃至700℃的温度下以每分钟20标准立方厘米(20sccm)到200sccm的速度提供甲硅烷(SiH4)和/或乙硅烷(Si2H6)，这可以提供每分钟5纳米至每分钟50纳米的生长速度。可替代地，非选择性外延工艺可以在10托至100托的压强下和400℃至650℃的温度下以每分钟20毫克至每分钟250毫克的速率提供丙硅烷(Si3H8)。外延层146可以在相同温度下使用丙硅烷比使用甲硅烷或乙硅烷以更高的速率生长，或者外延层146可以在更低的温度下以与甲硅烷/乙硅烷相当的速率生长。在该示例的一些版本中，在形成外延层146期间通过非选择性外延工艺提供给籽晶层144的顶表面的气体可以基本不含有含氯气体，这可以形成基本相同厚度的单晶区148和非晶区150。在其他版本中，在形成外延层146期间提供给衬底102的气体可以包括一些含氯气体，这可以形成比非晶区150更厚(例如厚20％)的单晶区148。例如，非选择性外延工艺可以在20托至100托的压强下以及1080℃至1120℃的温度下提供具有氢气(H2)的二氯甲硅烷，这可以提供每分钟500纳米至每分钟2微米的生长速率。可替代地，非选择性外延工艺可以在500托至760托的压强下以及1115℃至1200℃的温度下提供具有氢气的三氯甲硅烷(SiHCl3)，这可以提供每分钟3.5微米至每分钟4微米的生长速率。
参考图1L，保护层152被形成在外延层146上方。保护层152可以包括二氧化硅、氮化硅和/或氧氮化硅的一个或多个层。保护层152可以具有50纳米至200纳米的厚度，并且可以通过使用用于二氧化硅的TEOS和用于氮化硅的BTBAS的PECVD工艺来形成。保护层152可以具有光学厚度，该光学厚度是厚度乘以有效折射率，这为相对于用于随后的辐射感应再结晶工艺的非晶区150提供了有效的抗反射层。例如，保护层152的光学厚度可以是随后的辐射感应再结晶工艺的辐射能量的主要波长的20％到30％，以提供有效的抗反射层。对于使用具有10.6微米波长的二氧化碳激光器的辐射感应再结晶工艺，保护层152的光学厚度可以是2.12微米至3.18微米以提供有效的抗反射层。
参考图1M，辐射感应再结晶工艺154将非晶区150加热到比外延层146的单晶区148更高的温度，使得非晶区150再结晶以便将单晶区148延伸到埋入式隔离层124上方。图1M描绘完成状态的辐射感应再结晶工艺154。辐射感应再结晶工艺154可以将非晶区150的温度提升到它的熔点之上。通过形成保护层152以提供关于非晶区150的抗反射层，相比于被耦合到单晶区148，来自辐射感应再结晶工艺154的更多辐射能量可以被有利地耦合到非晶区150，由此促进延伸的单晶区148中的低缺陷。辐射感应再结晶工艺154可以在保护层152与埋入式隔离层124上方的单晶区148的新再结晶部分之间产生粗糙界面156。例如，如图1M中示意性描绘的，辐射感应再结晶工艺154可以包括扫描激光退火工艺154。可替代地，辐射感应再结晶工艺154可以是闪光灯退火工艺，或将来自电磁频谱的任何一部分中的辐射源的能量提供给非晶区150的其他辐射工艺。通过形成外延层以具有在埋入式隔离层124的顶表面126之上并且与非晶区150侧面相邻的单晶区148，可以使得埋入式隔离层124上方的单晶区148的新再结晶部分能够形成为比没有与非晶区侧面相邻的单晶区的外延层具有更少的缺陷。
参考图1N，在不去除单晶区148的重要部分的情况下，去除图1M的保护层152。可以通过对外延层146具有选择性的等离子体蚀刻，或通过使用氢氟酸的稀释缓冲水溶液的湿法蚀刻来去除保护层152。
参考图1O，单晶区148被平坦化以提供在埋入式隔离层124上方延伸的单晶区148的平滑的顶表面158。单晶区148可以通过CMP工艺160(在图1O中由CMP垫描绘)被平坦化。可替代地，单晶区148可以通过其他方法(诸如光刻胶回刻工艺)被平坦化。
参考图1P，热氧化工艺可以被用于消耗顶表面158处的单晶区148的期望厚度，从而在单晶区148上形成热氧化物层162。通过使用热氧化工艺消耗单晶区148的期望厚度，可以横跨埋入式隔离层124有利地消耗统一数量的单晶区148。消耗单晶区148的期望厚度的其他方法(诸如定时全面蚀刻工艺)在该示例的范围内。
参考图1Q，在单晶区148上的图1P中的热氧化物层162被去除，留下在埋入式隔离层124上方具有最终厚度164的单晶区148。可以通过等离子体蚀刻工艺去除热氧化物层162，该等离子体蚀刻工艺对单晶区148具有选择性并且终止于单晶区148的顶表面158处。可替代地，可以通过使用氢氟酸的缓冲稀释水溶液的定时湿法蚀刻工艺去除热氧化物层162。在埋入式隔离层124上方的单晶区148提供隔离半导体层114。最终厚度164可以小于120纳米，例如75纳米至100纳米。
参考图1R，防护层166被形成在隔离半导体层114上方。例如，防护层166可以包括5纳米至15纳米的热氧化物。防护层166与侧壁136和阻挡层104的顶层(诸如氮化硅层110)具有不同的蚀刻特性。
参考图1S，图1R的侧壁136和阻挡层104的氮化硅层110被去除。侧壁136中的氮化硅和氮化硅层110可以通过150℃的磷酸水溶液来去除。例如，隔离半导体层114的宽度168可以是2微米至200微米。又例如，埋入式隔离层124的最终厚度170可以是200纳米至900纳米厚。组件(诸如晶体管)可以随后被形成在埋入式隔离层124上方的隔离半导体层114中，以有利地具有对衬底102的低电容。
图2A至图2G是图1A至图1S中的集成电路的截面，描绘了用于形成单晶区和非晶区并且用于随后的辐射感应再结晶工艺的可替代方法。参考图2A，埋入式隔离层124被形成在集成电路100的衬底102中的隔离槽118中。埋入式隔离层124的顶表面126被凹入到与隔离槽118相邻的阻挡层104下方的衬底102的顶表面106之下。侧壁136被形成在隔离槽118中的衬底102的侧表面132上。在该示例中，籽晶层144被形成在籽晶沟槽140中的衬底102上以延伸高于由与隔离槽118相邻的衬底102的顶表面106限定的平面。
参考图2B，非晶区150被形成在阻挡层和埋入式隔离层124上方并与籽晶层144接触。在该示例中，非晶区150被形成为一层多晶的硅150(被称为多晶硅)。多晶硅非晶区150可以诸如在550℃至600℃的温度下和0.2托至1托的压强下通过热分解硅烷来形成。通过与籽晶层144分离地形成非晶区150，与同时形成相比，可以有利地实现对非晶区150的更多厚度控制。侧壁136将非晶区150与衬底102分离。
参考图2C，保护层152如参考图1L所描述那样被形成在非晶区150上方。考虑到非晶区150的顶表面的形状，保护层152可以被形成以便在靠近籽晶层144的区域中为随后的辐射感应再结晶工艺提供最大抗反射特性。
参考图2D，辐射感应再结晶工艺154将非晶区150加热到比籽晶层144更高的温度，使得非晶区150中的多晶硅在籽晶层144周围形成单晶区148并向外生长越过埋入式隔离层124。辐射感应再结晶工艺154可以在保护层152和单晶区148的新再结晶部分之间产生粗糙界面156。通过形成籽晶层144以延伸高于衬底102的顶表面106，埋入式隔离层124上方的单晶区148的新再结晶部分可以被使能以形成具有比与埋入式隔离层124的顶表面共面的籽晶层144更少的缺陷。
参考图2E，在不去除单晶区148的重要部分的情况下，图2D的保护层152被去除。保护层152可以如参考图1N所描述地被去除。
参考图2F，单晶区148以及可能籽晶层144被平坦化以提供光滑平面的顶表面158。单晶区148以及可能籽晶层144可以通过CMP工艺或通过其他方法被平坦化。如图2F中所描述，顶表面158可以高于阻挡层104。在该示例的另一版本中，顶表面158可以与阻挡层104的顶表面基本共面，这可以是CMP平坦化工艺所导致。在又一个版本中，顶表面158可以低于阻挡层104的顶表面，但是高于与隔离槽118相邻的衬底102的顶表面106。
参考图2G，单晶区148被凹入隔离槽118中以提供期望厚度164。单晶区148可以通过如图2G所描绘的定时等离子体蚀刻工艺172被凹入，或者通过使用氢氟酸的水性缓冲溶液的定时湿法蚀刻工艺被凹入。在获得期望的厚度164之后，集成电路100的工艺如参考图1R等等所描述继续进行。
在权利要求的范围内，在所描述的实施例中有可能进行修改，并且其他实施例是有可能的。

Claims (20)

1.一种集成电路，其包含：
衬底，其包括硅基单晶半导体材料；
埋入式隔离层，其包括所述衬底中的电介质材料，所述埋入式隔离层的顶表面比与所述埋入式隔离层相邻的所述衬底的顶表面低；
基于单晶硅的材料的籽晶层，其通过所述埋入式隔离层被设置在籽晶沟槽中，所述籽晶层穿过所述籽晶沟槽与所述衬底接触；以及
隔离半导体层，其被设置在所述埋入式隔离层上方并在所述埋入式隔离层之上的所述衬底的侧表面处与所述衬底分离。
2.根据权利要求1所述的集成电路，其中所述埋入式隔离层的所述电介质材料是二氧化硅。
3.根据权利要求1所述的集成电路，其中所述埋入式隔离层具有200纳米至900纳米的厚度。
4.根据权利要求1所述的集成电路，其中所述隔离半导体层具有75纳米至100纳米的厚度。
5.根据权利要求1所述的集成电路，其中所述隔离半导体层具有2微米至200微米的宽度。
6.一种形成集成电路的方法，所述方法包含：
提供衬底，所述衬底包括硅基单晶半导体材料；
形成阻挡层，所述阻挡层包括在所述衬底的顶表面上方的电介质材料；
穿过所述阻挡层并在所述衬底中形成隔离槽；
形成埋入式隔离层，所述埋入式隔离层包括在所述隔离槽中的电介质材料，所述埋入式隔离层的顶表面比与所述隔离槽相邻的所述衬底的所述顶表面低；
在所述隔离槽中所述埋入式隔离层的所述顶表面之上的所述衬底的侧表面上形成电介质材料；
穿过所述埋入式电介质层形成籽晶沟槽，所述籽晶沟槽使所述衬底裸露；
在所述籽晶沟槽中的所述衬底上形成基于单晶硅的籽晶层，所述籽晶层延伸高于所述籽晶沟槽的所述顶表面；
在所述埋入式隔离层的所述顶表面上方和所述阻挡层上方形成硅基半导体材料的非晶区，所述非晶区与所述籽晶层接触；
通过辐射感应再结晶工艺加热所述非晶区，以在所述埋入式隔离层上方形成与所述籽晶层对齐的单晶区；以及
将所述单晶区的顶表面凹入。
7.根据权利要求6所述的方法，其中所述阻挡层包括在所述衬底的所述顶表面处的二氧化硅层以及在所述二氧化硅层上的氮化硅层。
8.根据权利要求6所述的方法，其中形成所述埋入式隔离层包括：
在所述阻挡层上方形成包括二氧化硅的隔离电介质材料，并且填充所述隔离槽；
通过化学机械抛光工艺即CMP工艺向下平坦化所述隔离电介质材料直到所述阻挡层；以及
将在与所述隔离槽相邻的所述衬底的所述顶表面下方的所述隔离电介质材料凹入。
9.根据权利要求6所述的方法，其中在所述衬底的所述侧表面上形成所述电介质材料包括：
形成侧壁材料层，所述侧壁材料层包括在所述阻挡层上方共形的氮化硅并在所述埋入式隔离层上方延伸，在所述埋入式隔离层的所述顶表面之上覆盖所述隔离槽中的所述衬底的所述侧表面；以及
利用各向异性反应离子蚀刻工艺即RIE工艺从所述阻挡层上方去除所述侧壁材料层并从所述埋入式隔离层的所述顶表面去除所述侧壁材料层以便在所述隔离槽内的所述衬底的所述侧表面上留下侧壁。
10.根据权利要求6所述的方法，其中形成所述非晶区包括在所述阻挡层和所述埋入式隔离层上方形成硅基半导体材料的外延层的非选择性外延工艺，所述外延层与所述籽晶层接触，所述外延层包括在所述籽晶层上的单晶区和在所述埋入式隔离层上与所述单晶区侧面接触的非晶区。
11.根据权利要求6所述的方法，其中形成所述非晶区包括形成多晶硅层以提供所述非晶区。
12.根据权利要求6所述的方法，其中所述辐射感应再结晶工艺包括扫描激光退火工艺。
13.根据权利要求6所述的方法，其中所述保护层具有光学厚度，所述光学厚度是所述保护层的厚度乘以所述保护层的有效折射率，所述光学厚度是所述辐射感应再结晶工艺的辐射能量的主波长的20％到30％。
14.根据权利要求6所述的方法，其中平坦化所述单晶区的所述顶表面包括CMP工艺。
15.根据权利要求6所述的方法，其中将所述单晶区的所述顶表面凹入包括：
通过热氧化工艺在所述单晶区的所述顶表面形成热氧化物层；以及
去除所述热氧化物层。
16.根据权利要求6所述的方法，进一步包含：
在通过所述辐射感应再结晶工艺加热所述非晶区之前，在所述非晶区上方形成包括电介质材料的保护层；以及
在通过所述辐射感应再结晶工艺加热所述非晶区之后，去除所述保护层。
17.根据权利要求6所述的方法，进一步包含在通过所述辐射感应再结晶工艺加热所述非晶区之后，平坦化在所述埋入式隔离层上方的所述单晶区的顶表面。
18.根据权利要求6所述的方法，其中所述埋入式隔离层具有200纳米至900纳米的厚度。
19.根据权利要求6所述的方法，其中所述隔离半导体层具有75纳米至100纳米的厚度。
20.根据权利要求6所述的方法，其中所述隔离半导体层具有2微米至200微米的宽度。
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CI03 Correction of invention patent

Correction item: Priority

Correct: 61/978,935 2014.04.13 US|14/301,788 2014.06.11 US

False: 61/978,935 2014.04.13 US

Number: 26-02

Page: The title page

Volume: 39

Correction item: Priority

Correct: 61/978,935 2014.04.13 US|14/301,788 2014.06.11 US

False: 61/978,935 2014.04.13 US

Number: 26-02

Volume: 39

CI03 Correction of invention patent