CN106209102A - Mixed type two-layer configuration for full parellel successive approximation analog-digital converter - Google Patents
Mixed type two-layer configuration for full parellel successive approximation analog-digital converter Download PDFInfo
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- CN106209102A CN106209102A CN201610496084.1A CN201610496084A CN106209102A CN 106209102 A CN106209102 A CN 106209102A CN 201610496084 A CN201610496084 A CN 201610496084A CN 106209102 A CN106209102 A CN 106209102A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
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- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
The invention discloses a kind of mixed type two-layer configuration for full parellel successive approximation analog-digital converter, switch is shared including first order full parellel analog-digital converter Flash ADC and second level successive approximation analog-digital converter SAR ADC, digital calibration circuit, sample circuit, first order full parellel analog-digital converter includes 3.5 bit Flash single-chip microcomputers, digital encoding circuit, and second level successive approximation analog-digital converter includes high-low position electric capacity sole plate level switch controller, the second comparator, high-low position DAC capacitor array.SAR ADC and Flash ADC is combined by the present invention, before signal cycle is resolved by SAR ADC, the Gao Sanwei of signal is quantified by the feature utilizing Flash ADC Parallel transformation simultaneously, and remaining figure place is quantified by SAR ADC, thus improves the switching rate of SAR ADC.
Description
Technical field
The present invention relates to field of analog integrated circuit, specifically a kind of for full parellel Approach by inchmeal Analog-digital Converter
The mixed type two-layer configuration of device.
Background technology
Taking with smart mobile phone, panel computer, Intelligent bracelet as representative is held consumer electronics and is changed the life of people.
The acp chip of hardware support is provided for this type of consumer electronics, by increasingly advanced semiconductor technology, constantly will originally divide
It is integrated that vertical components and parts design carries out one chip, constitutes function and becomes stronger day by day and SOC(system on a chip) (SoC) that power consumption constantly reduces, low
Power consumption becomes the key factor designing this type of portable set.Make to connect " the bridge between simulated world and digital signal processor
Beam " the indispensable important module of the most above-mentioned SOC(system on a chip) of analog-digital converter.Therefore, people's analog to digital to low consumption
The demand of transducer (ADC) is more and more stronger.
In existing general ADC framework, compare pipeline ADC, over-sampling ADC and fold the several types such as ADC
Analog-digital converter, SAR ADC (Successive Approximation Register Analog to Digital
Converter, SAR ADC) there is the advantages such as middle high accuracy, high speed degree, low in energy consumption and area occupied be little, the most key
Being under using advanced digital CMOS process, the ADC's of same design index employing capacitor type SAR framework is least in power-consuming.But,
The SAR ADC of traditional structure still cannot replace pipeline ADC in the status in high-speed applications field because its system structure determine
Each change-over period is required for carrying out at least N-1 (N is the resolution of analog-digital converter) secondary lookup, and this is the aobvious of this kind of structure
Write defect, hinder the development of SAR ADC phase more High Speed Field.
Tradition SAR ADC is made up of DAC capacitor array, comparator, control clock generation circuit, logic control circuit.One
In the individual change-over period, the workflow of SAR ADC is as follows:
1, input signal is sampled by DAC capacitor array, and the required time is Tsample;
2, the electric charge of storage and variable reference voltage on DAC capacitor array being carried out gradually multilevel iudge, this process is divided into N (N
Resolution for analog-digital converter) circulation, each circulation will experience comparator locking (TCMP), the transmission of logic control circuit
Postpone (TDgital), DAC sets up three steps of precision prescribed (TDAC), and wherein last circulation only needs comparator to complete
Relatively work.By analyzing the shortest time that can calculate traditional SAR ADC each clock cycle above it is: TADC=
Tsample+ TCMPxN+ (TDgital + TDAC)xN-1
Flash type ADC, is also called full parellel ADC or flashing ADC, be realize analog digital conversion the fastest be also the most directly to tie
Configuration formula.It is generated network (being typically made up of), a string comparator and codimg logic block group resistance string dividing potential drop by reference voltage
Become.Input signal synchronizes to compare with each reference voltage to produce thermometer-code through comparator, and the encoded device of thermometer-code produces
Binary system output numeral.Owing to need not gradually compare, it is not conversion N time to N bit data, but only changes once, and
Its conversion speed is only dependent upon the speed of comparator, thus the ADC of this structure be in various configurations conversion speed
Fast.But, this ultrahigh speed is to sacrifice the conditions such as ADC power consumption, area as cost.Due to a n position Flash
ADC at least needs 2n equivalent divider resistance, 2n-1 comparator and relevant digital encoder and depositor etc..Institute
With, generally consider that the precision of merit power consumption and chip area Flash ADC is not over 8.
In sum, SAR ADC have low-power consumption, in high precision, the advantage such as medium speed, Flash ADC has letter relatively
Single structure and the highest be the advantages such as conversion speed, Flash and SAR can be combined, make up SAR ADC in speed
Not enough, it is achieved a kind of well compromise between speed, precision and power consumption.
Summary of the invention it is an object of the invention to provide a kind of mixing for full parellel successive approximation analog-digital converter
Mould assembly two-layer configuration, to solve the problem that prior art exists.
In order to achieve the above object, the technical solution adopted in the present invention is:
Mixed type two-layer configuration for full parellel successive approximation analog-digital converter, it is characterised in that: include the first order
Full parellel analog-digital converter Flash ADC, second level successive approximation analog-digital converter SAR ADC, digital calibration electricity
Road, shared switch S1 and S2；
Described first order full parellel analog-digital converter is by the 3.5-bit Flash single-chip microcomputer of built-in comparator, digital coding
Circuit is constituted, and the comparator in 3.5-bit Flash single-chip microcomputer turns as the first comparator, second level Approach by inchmeal simulation numeral
Parallel operation is by the second comparator, high-order DAC capacitor array, low level DAC capacitor array, high-order electric capacity sole plate level switching control
Device, bit capacitor sole plate level switch controller are constituted, and wherein high-order DAC capacitor array, low level DAC capacitor array are as adopting
Sample capacitor array, the end plate end of high-order DAC capacitor array is connected with high-order electric capacity sole plate level switch controller, low level
The end plate end of DAC capacitor array is connected with bit capacitor sole plate level switch controller, the climax of high-order DAC capacitor array
After the top plate end of plate end and low level DAC capacitor array connects altogether, connect end altogether by shared switch S1 Yu 3.5-bit Flash monolithic
Machine input connects, and connects altogether and holds the input also by shared switch S2 and the second comparator to connect, by shared switch S1 and S2
Realize first order full parellel analog-digital converter Flash ADC and second level successive approximation analog-digital converter SAR ADC
Time-sharing multiplex sampling capacitance array；
In first order full parellel analog-digital converter Flash ADC, 3.5-bit Flash single-chip microcomputer is believed with the first sampling clock
Number CLKD1 is as control signal, and the output signal of 3.5-bit Flash single-chip microcomputer is as high-order electric capacity sole plate level switching control
The control signal of device processed, the output signal of 3.5-bit Flash single-chip microcomputer also sends into the input of digital encoding circuit simultaneously, number
Word coding circuit outfan is connected with one of them input of digital calibration circuit；
In the successive approximation analog-digital converter SAR ADC of the second level, the second comparator is made with the second sampled clock signal CLKD2
For control signal, the output signal of the second comparator as the control signal of bit capacitor sole plate level switch controller,
The output signal of two comparators also send digital calibration circuit another input；
Sampling capacitance array is using sampled clock signal CLKS as control signal, when sampled clock signal CLKS is high level pair
Input information is sampled, and is stored in the form of a charge by the signal of sampling on the top plate end of sampling capacitance array, this
Time share switch S1, S2 be in off-state；
Sampling is closed after terminating and is shared switch S1, in first order full parellel analog-digital converter Flash ADC, 3.5-bit
Flash single-chip microcomputer starts the quantizing process that the first order is high-order under the first sampled clock signal CLKD1 controls, to high-order DAC electricity
The signal that appearance array is sampled quantifies, and the output then quantization obtained is as high-order electric capacity sole plate level switching control
The control signal of device, controls the level switching of high-order DAC capacitor array sole plate；
The quantization of a first order high position disconnects after terminating and shares switch S1, closes shared switch S2, second level Approach by inchmeal simulation number
In word transducer SAR ADC, the second comparator starts the amount of second level low level under the control of the second sampled clock signal CLKD2
Change process, the signal being sampled low level DAC capacitor array quantifies, and the output then quantization obtained is as bit capacitor
The control signal of sole plate level switch controller, bit capacitor sole plate level switch controller is according to the amount of the second comparator
Changing the level switching of output control low level DAC capacitor array sole plate, the second level disconnects S2 after quantifying to terminate.
The described mixed type two-layer configuration for full parellel successive approximation analog-digital converter, it is characterised in that:
Described first order full parellel analog-digital converter Flash ADC utilizes the 3.5-bit Flash single-chip microcomputer letter to being sampled
Number quantify and obtain 14 thermometer-codes, after digital encoding circuit encodes, obtain 4 binary codes, wherein binary code
Lowest order is redundancy function, for digital calibration；Second comparator pair in the successive approximation analog-digital converter SAR ADC of the second level
Binary code is obtained after the signal quantization sampled.
The described mixed type two-layer configuration for full parellel successive approximation analog-digital converter, it is characterised in that:
Described digital calibration circuit first order full parellel analog-digital converter Flash ADC is obtained after digital encoding circuit two
The lowest order of binary digits output code, the binary digit obtained with second level successive approximation analog-digital converter SAR ADC
The highest order dislocation of output code is added, and obtains final binary digit output code, first order full parellel analog-digital converter
In Flash ADC, the use of redundancy function reduces because comparator imbalance voltage is the error of transfer zone.
The described mixed type two-layer configuration for full parellel successive approximation analog-digital converter, it is characterised in that:
Described digital encoding circuit includes thermometer-code-Gray code conversion circuit, Gray code-binary code change-over circuit, in order to effectively
The digital output error that brings because of metastable state due to comparator of elimination, generally use Gray code as intermediate code, be placed in
Between thermometer-code and binary code, thermometer-code is first converted to Gray code, then is binary code by Gray code conversion.
The described mixed type two-layer configuration for full parellel successive approximation analog-digital converter, it is characterised in that:
Described high-order DAC capacitor array is divided into two arrays, and its total capacitance value is 448C, and every an array is all 16C by 14 capacitances
Electric capacity composition, from highest order to lowest order, be divided into 128C, 64C, 32C tri-groups, two row respectively by share switch S1 with
3.5-bit Flash single-chip microcomputer input connects；
Described low level DAC capacitor array is divided into two arrays, and its total capacitance value is 64C, and every an array is from highest order to lowest order
Electric capacity be respectively 16C, 8C, 4C, 2C, 1C, 1C, wherein string by share switch S2 and the second comparator anode be connected,
Another row are connected by the negative terminal of shared switch S2 and the second comparator.
The described mixed type two-layer configuration for full parellel successive approximation analog-digital converter, it is characterised in that:
High-order electric capacity sole plate level switch controller, bit capacitor sole plate level switch controller are based respectively on HCSR algorithm real
The now level switching to plates capacitance at the bottom of corresponding capacitor array, wherein:
The level switching principle of plates capacitance at the bottom of high-order DAC capacitor array is by described HCSR algorithm:
When the highest order quantized result of described first order full parellel analog-digital converter Flash ADC is 000, high-order DAC
The 128C/64C/32C electric capacity sole plate being connected with the second comparator anode in capacitor array is switched to VREF by VCM, with second
The 128C/64C/32C electric capacity sole plate that comparator anode is connected is switched to 0 by VCM；When described first order Flash ADC
When high-order quantized result is 001, the 128C/32C electric capacity sole plate being connected with the second comparator anode in high-order DAC capacitor array
Being switched to VREF, 68C electric capacity sole plate by VCM keeps connection VCM constant, the 128C/32C electricity being connected with the second comparator negative terminal
Holding sole plate and be switched to 0 by VCM, it is constant that 68C electric capacity sole plate keeps connecting VCM；The highest as described first order Flash ADC
Position quantized result is when being 010, the 68C/32C electric capacity sole plate being connected with the second comparator anode in high-order DAC capacitor array by
VCM is switched to VREF, 128C electric capacity sole plate and keeps connection VCM constant, the 68C/32C electric capacity being connected with the second comparator negative terminal
Sole plate is switched to 0 by VCM, and it is constant that 128C electric capacity sole plate keeps connecting VCM；
When the highest order quantized result of described first order full parellel analog-digital converter Flash ADC is 011, high-order DAC
The 32C electric capacity sole plate being connected with the second comparator anode in capacitor array is switched to VREF, 128C/68C electric capacity sole by VCM
It is constant that plate keeps connecting VCM, and the 32C electric capacity sole plate being connected with the second comparator negative terminal is switched to 0 by VCM, 128C/68C electricity
Holding sole plate keeps connection VCM constant；In like manner, the highest as described first order full parellel analog-digital converter Flash ADC
When position quantized result is 100,101,110,111, with above-mentioned four kinds of switching mode contrast.
The level switching principle of plates capacitance at the bottom of low level DAC capacitor array is by described HCSR algorithm:
When in described second level successive approximation analog-digital converter SAR ADC, the highest order of low level DAC capacitor array quantifies knot
When fruit is 0, the 16C electric capacity sole plate being connected with the second comparator anode is switched to VREF by VCM, with the second comparator negative terminal phase
16C electric capacity sole plate even is switched to 0 by VCM；When low level in described second level successive approximation analog-digital converter SAR ADC
When the highest order quantized result of DAC capacitor array is 1, the 16C electric capacity sole plate that the second positive and negative end of comparator is connected keeps connecting
VCM is constant, and by 0, the 32C electric capacity sole plate being connected with the second comparator negative terminal is switched to VCM；8C in low level DAC capacitor array
The switching mode of electric capacity sole plate to be determined jointly according to last time and this quantized result, when last time and this quantization knot
When fruit is 00, the 8C electric capacity sole plate being connected with the second comparator anode is switched to VREF by VCM, with the second comparator negative terminal phase
8C electric capacity sole plate even is switched to 0 by VCM；When last time and this quantized result are 01, the second comparator positive and negative end phase
It is constant that 8C electric capacity sole plate even keeps connecting VCM, is switched by 0 by the 16C electric capacity sole plate being connected with the second comparator negative terminal
To VCM；When last time and this quantized result are 10, the 8C electric capacity sole plate being connected with the second comparator anode is cut by VCM
Changing to VREF, the 8C electric capacity sole plate being connected with the second comparator negative terminal is switched to 0 by VCM；When last time and this quantization knot
When fruit is 11, the 8C electric capacity sole plate being connected with the second comparator anode is switched to 0 by VCM, is connected with the second comparator negative terminal
8C electric capacity sole plate be switched to VREF by VCM；In like manner, the switching of 4C/2C/C/C electric capacity sole plate in low level DAC capacitor array
Mode is identical with the switching mode of 8C, is all jointly to be determined with the quantized result of last time according to this.
The method have the advantages that
The mixed type two-layer configuration of the full parellel successive approximation analog-digital converter that the present invention proposes combines Flash ADC
The feature of rapid translating, has higher sampling rate relative to existing SAR ADC structure；Due to the Flash ADC added
Figure place is relatively low, and have employed dynamic comparer structure, under higher sampling clock controls, and the power consumption that dynamic comparer consumes
The least；Utilize sample circuit technology of sharing to allow Flash Yu SAR share a sample circuit, mix relative to existing Flash-SAR
Mould assembly structure decreases the number of sample circuit, thus reduces power consumption and chip area；SAR ADC have employed the new of proposition
Type switching strategy HCSR algorithm, greatly reduces capacitance switch power consumption in frequent handoff procedure.The present invention is with existing
MCS switching strategy compares, and the total capacitance number needed for capacitor array reduces one times, and the level switching of whole electric capacity sole plate is average
Lower power consumption 81.22%.Certainly, the arbitrary product implementing the present invention it is not absolutely required to reach all the above excellent simultaneously
Point.
Accompanying drawing explanation
The mixed type two-layer configuration being applied to full parellel successive approximation analog-digital converter that Fig. 1 provides for the present invention
Schematic diagram.
Fig. 2 is applied to the sampling of full parellel successive approximation analog-digital converter and quantizing process for what the present invention provided
Sequential chart.
Fig. 3 is that the capacitive switch switches energy of the quantized result of the present invention and two kinds of technology of existing MCS and Monotonic disappears
Consumption comparison diagram.
The simulation result signal of the full parellel successive approximation analog-digital converter that Fig. 4 provides for the embodiment of the present invention
Figure.
Detailed description of the invention
Embodiments provide a kind of mixed type two-stage for full parellel successive approximation analog-digital converter
Structure, as it is shown in figure 1, it includes first order full parellel analog-digital converter Flash ADC and the simulation of second level Approach by inchmeal
Switch shared by digital converter SAR ADC, digital calibration circuit, sample circuit.First order full parellel analog-digital converter bag
Include the first sample circuit, 3.5-bit Flash single-chip microcomputer, digital encoding circuit.Second level successive approximation analog-digital converter
Including the second sample circuit, high-order electric capacity sole plate level switch controller and bit capacitor sole plate level switch controller,
Second comparator, high-order DAC capacitor array and low level DAC capacitor array;Wherein DAC capacitor array is digital analog converter
Capacitor array, wherein DAC full name is Digital analog converter, and wherein SAR ADC full name is Successive
Approximation Register Analog to Digital Converter。
Share switch S1, S2 to be used for realizing first order full parellel analog-digital converter Flash ADC and the second level gradually
Approximation analog-digital converter one sampling capacitance array of SAR ADC time-sharing multiplex, sampling capacitance is second level Approach by inchmeal mould
Intend the capacitor array of digital converter SAR ADC.When sampling clock CLKS is high level, input information is sampled, and will
Signal is stored on the top plate of sampling capacitance in the form of a charge.Share switch S1, S2 to be off simultaneously.Sampling knot
Closing after bundle and share switch S1, first order full parellel analog-digital converter Flash ADC is at the first sampled clock signal CLKD1
The signal under control sampled high-order DAC capacitor array quantifies.Meanwhile, output quantization obtained is as high-order electric capacity
The control signal of sole plate level switch controller, controls the level switching of high-order DAC capacitor array sole plate.The first order quantifies
Disconnecting after end and share switch S1, close and share switch S2, the second comparator is under the control of the second sampled clock signal CLKD2
Starting the quantizing process of second level successive approximation analog-digital converter SAR ADC low level, bit capacitor sole plate level switches
Controller, according to the quantized result of the second comparator, controls the level switching of low level DAC capacitor array sole plate.The second level quantifies
Disconnect after end and share switch S2.
As in figure 2 it is shown, Fig. 2 is first order full parellel analog-digital converter Flash ADC and second level Approach by inchmeal mould
Intend digital converter sampling SAR ADC and the sequential chart of quantization.Sample phase, i.e. sampled clock signal CLKS be high level time
Waiting, input signal is connected to the top plate of sampling capacitance, shares switch S1, S2 simultaneously and is off.Wherein, sampling capacitance
Capacitor array for second level successive approximation analog-digital converter sampling SAR ADC.When the trailing edge of CLKS comes interim, to defeated
The analog signal sampling entered.In the holding stage, input signal is stored on the top plate of sampling capacitance in the form of a charge.The
One-level full parellel analog-digital converter Flash ADC quantization stage, sampling triggers while terminating shares switch S1 Guan Bi, for
The first order quantifies to prepare.Interim first order full parellel analog-digital converter Flash is carried out when the first order quantifies clock CLKD1
ADC starts to quantify a high position for sampled signal.Also the quantized result obtained is utilized traditional HCSR algorithm controls simultaneously
Cutting of the electric capacity bottom crown of the high-order DAC capacitor array of control second level successive approximation analog-digital converter sampling SAR ADC
Change mode.While the first order quantifies to terminate, switch S2 Guan Bi is shared in triggering, S1 disconnects so that sampling capacitance completes second
Redistributing of the electric charge of level.When the control letter of comparator in second level successive approximation analog-digital converter sampling SAR ADC
During number CLKD2, successive approximation analog-digital converter sampling SAR ADC in the second level starts the low level amount of carrying out to sampled signal
Change.Quantized result switches via HCSR algorithm controls low level DAC capacitor array sole plate level, lasts till lowest order quantizing process
Complete.Trigger while the second level quantifies to terminate and share switch S2 disconnection
The HCSR algorithm that high-order electric capacity sole plate level switch controller described above passes through to propose is to high-order and low level DAC electric capacity
Array sole plate level is controlled, and HCSR algorithm full name is higher capacitor skipped-or-reused, the highest
Position electric capacity is skipped and multiplexing algorithm；
The level handoff procedure of plates capacitance at the bottom of high-order DAC capacitor array is by HCSR algorithm:
When the highest order quantized result of first order full parellel analog-digital converter Flash ADC is 000, high-order DAC electric capacity
The 128C/64C/32C electric capacity sole plate being connected with the second comparator anode in array is switched to VREF by VCM, compares with second
The 128C/64C/32C electric capacity sole plate that device anode is connected is switched to 0 by VCM；When first order full parellel analog-digital converter
When the highest order quantized result of Flash ADC is 001, the 128C/ being connected with the second comparator anode in high-order DAC capacitor array
32C electric capacity sole plate is switched to VREF, 68C electric capacity sole plate by VCM and keeps connection VCM constant, with the second comparator negative terminal phase
128C/32C electric capacity sole plate even is switched to 0 by VCM, and it is constant that 68C electric capacity sole plate keeps connecting VCM；When the described first order
When the highest order quantized result of Flash ADC is 010, the 68C/ being connected with the second comparator anode in high-order DAC capacitor array
32C electric capacity sole plate is switched to VREF, 128C electric capacity sole plate by VCM and keeps connection VCM constant, with the second comparator negative terminal phase
68C/32C electric capacity sole plate even is switched to 0 by VCM, and it is constant that 128C electric capacity sole plate keeps connecting VCM；
When the highest order quantized result of first order full parellel analog-digital converter Flash ADC is 011, high-order DAC electric capacity
The 32C electric capacity sole plate being connected with the second comparator anode in array is switched to VREF, 128C/68C electric capacity sole plate by VCM and protects
Holding connection VCM constant, the 32C electric capacity sole plate being connected with the second comparator negative terminal is switched to 0 by VCM, at the bottom of 128C/68C electric capacity
It is constant that pole plate keeps connecting VCM；In like manner, knot is quantified when the highest order of first order full parellel analog-digital converter Flash ADC
When fruit is 100,101,110,111, with above-mentioned four kinds of switching mode contrast.
The level handoff procedure of plates capacitance at the bottom of low level DAC capacitor array is by HCSR algorithm:
When in second level successive approximation analog-digital converter sampling SAR ADC, the highest order of low level DAC capacitor array quantifies knot
When fruit is 0, the 16C electric capacity sole plate being connected with the second comparator anode is switched to VREF by VCM, with the second comparator negative terminal phase
16C electric capacity sole plate even is switched to 0 by VCM；When low level in second level successive approximation analog-digital converter sampling SAR ADC
When the highest order quantized result of DAC capacitor array is 1, the 16C electric capacity sole plate that the second positive and negative end of comparator is connected keeps connecting
VCM is constant, and by 0, the 32C electric capacity sole plate being connected with the second comparator negative terminal is switched to VCM；8C in low level DAC capacitor array
The switching mode of electric capacity sole plate to be determined jointly according to last time and this quantized result, when last time and this quantization knot
When fruit is 00, the 8C electric capacity sole plate being connected with the second comparator anode is switched to VREF by VCM, with the second comparator negative terminal phase
8C electric capacity sole plate even is switched to 0 by VCM；When last time and this quantized result are 01, the second comparator positive and negative end phase
It is constant that 8C electric capacity sole plate even keeps connecting VCM, is switched by 0 by the 16C electric capacity sole plate being connected with the second comparator negative terminal
To VCM；When last time and this quantized result are 10, the 8C electric capacity sole plate being connected with the second comparator anode is cut by VCM
Changing to VREF, the 8C electric capacity sole plate being connected with the second comparator negative terminal is switched to 0 by VCM；When last time and this quantization knot
When fruit is 11, the 8C electric capacity sole plate being connected with the second comparator anode is switched to 0 by VCM, is connected with the second comparator negative terminal
8C electric capacity sole plate be switched to VREF by VCM；In like manner, the switching of 4C/2C/C/C electric capacity sole plate in low level DAC capacitor array
Mode is identical with the switching mode of 8C, is all jointly to be determined with the quantized result of last time according to this.
The successive approximation analog-digital converter based on HCSR algorithm that the present invention proposes, its switch switching average power consumption is
31.98 CV2REF.The switch switching average power consumption of the MCS technology existed is 170.29 CV2REF.In this patent gradually
The switch switching power consumption of approximation analog-digital converter reduces by 81.22% compared to the MCS technology existed, and Fig. 3 shows is
It is corresponding that Monotonic, MCS and this paper quantifies each quantized result in 1024 kinds of results of 10 results respectively
Capacitive switch switches power consumption.
Under smic180nm technique, the circuit of this invention put up, use circuit simulation tools Cadence
Circuit is emulated by Spectre, and Fig. 4 is to be the FFT simulation result of the present invention.
In sum, SAR ADC and Flash ADC is combined, before signal cycle is resolved by SAR ADC, utilize
The Gao Sanwei of signal is quantified by the feature of Flash ADC Parallel transformation simultaneously, and remaining figure place is quantified by SAR ADC.Thus
Decrease SAR conversion times within a cycle, thus improve the switching rate of SAR ADC.Due to the Flash added
ADC figure place is relatively low, and have employed dynamic comparer structure, and under higher sampling clock controls, dynamic comparer consumes
Power consumption is the least.Meanwhile, this structure utilize sample circuit technology of sharing to allow Flash ADC Yu SAR share a sample circuit, phase
For existing Flash-SAR hybrid architecture, The present invention reduces the number of sample circuit, thus reduce power consumption and chip
Area.It addition, SAR ADC have employed the New Switching Strategy SHBR algorithm of proposition, compared with existing MCS switching strategy
Relatively, the total capacitance number needed for capacitor array reduces one times, and the level switching average power consumption of whole electric capacity sole plate reduces by 81.22%.
Present invention disclosed above preferred embodiment is only intended to help to illustrate the present invention.Preferred embodiment is the most detailed
Describe all of details, be also not intended to the detailed description of the invention that this invention is only described.Obviously, according to the content of this specification,
Can make many modifications and variations.These embodiments are chosen and specifically described to this specification, is to preferably explain the present invention
Principle and actual application so that skilled artisan can be best understood by and utilize the present invention.The present invention is only
Limited by claims and four corner thereof and equivalent.
Claims (6)
1. for the mixed type two-layer configuration of full parellel successive approximation analog-digital converter, it is characterised in that: include first
Level full parellel analog-digital converter Flash ADC, second level successive approximation analog-digital converter SAR ADC, digital calibration
Circuit, shared switch S1 and S2；
Described first order full parellel analog-digital converter is by the 3.5-bit Flash single-chip microcomputer of built-in comparator, digital coding
Circuit is constituted, and the comparator in 3.5-bit Flash single-chip microcomputer turns as the first comparator, second level Approach by inchmeal simulation numeral
Parallel operation is by the second comparator, high-order DAC capacitor array, low level DAC capacitor array, high-order electric capacity sole plate level switching control
Device, bit capacitor sole plate level switch controller are constituted, and wherein high-order DAC capacitor array, low level DAC capacitor array are as adopting
Sample capacitor array, the end plate end of high-order DAC capacitor array is connected with high-order electric capacity sole plate level switch controller, low level
The end plate end of DAC capacitor array is connected with bit capacitor sole plate level switch controller, the climax of high-order DAC capacitor array
After the top plate end of plate end and low level DAC capacitor array connects altogether, connect end altogether by shared switch S1 Yu 3.5-bit Flash monolithic
Machine input connects, and connects altogether and holds the input also by shared switch S2 and the second comparator to connect, by shared switch S1 and S2
Realize first order full parellel analog-digital converter Flash ADC and second level successive approximation analog-digital converter SAR ADC
Time-sharing multiplex sampling capacitance array；
In first order full parellel analog-digital converter Flash ADC, 3.5-bit Flash single-chip microcomputer is believed with the first sampling clock
Number CLKD1 is as control signal, and the output signal of 3.5-bit Flash single-chip microcomputer is as high-order electric capacity sole plate level switching control
The control signal of device processed, the output signal of 3.5-bit Flash single-chip microcomputer also sends into the input of digital encoding circuit simultaneously, number
Word coding circuit outfan is connected with one of them input of digital calibration circuit；
In the successive approximation analog-digital converter SAR ADC of the second level, the second comparator is made with the second sampled clock signal CLKD2
For control signal, the output signal of the second comparator as the control signal of bit capacitor sole plate level switch controller,
The output signal of two comparators also send digital calibration circuit another input；
Sampling capacitance array is using sampled clock signal CLKS as control signal, when sampled clock signal CLKS is high level pair
Input information is sampled, and is stored in the form of a charge by the signal of sampling on the top plate end of sampling capacitance array, this
Time share switch S1, S2 be in off-state；
Sampling is closed after terminating and is shared switch S1, in first order full parellel analog-digital converter Flash ADC, 3.5-bit
Flash single-chip microcomputer starts the quantizing process that the first order is high-order under the first sampled clock signal CLKD1 controls, to high-order DAC electricity
The signal that appearance array is sampled quantifies, and the output then quantization obtained is as high-order electric capacity sole plate level switching control
The control signal of device, controls the level switching of high-order DAC capacitor array sole plate；
The quantization of a first order high position disconnects after terminating and shares switch S1, closes shared switch S2, second level Approach by inchmeal simulation number
In word transducer SAR ADC, the second comparator starts the amount of second level low level under the control of the second sampled clock signal CLKD2
Change process, the signal being sampled low level DAC capacitor array quantifies, and the output then quantization obtained is as bit capacitor
The control signal of sole plate level switch controller, bit capacitor sole plate level switch controller is according to the amount of the second comparator
Changing the level switching of output control low level DAC capacitor array sole plate, the second level disconnects S2 after quantifying to terminate.
Mixed type two-layer configuration for full parellel successive approximation analog-digital converter the most according to claim 1,
It is characterized in that: described first order full parellel analog-digital converter Flash ADC utilizes 3.5-bit Flash single-chip microcomputer pair
The signal quantization sampled also obtains 14 thermometer-codes, obtains 4 binary codes, wherein after digital encoding circuit encodes
The lowest order of binary code is redundancy function, for digital calibration；In the successive approximation analog-digital converter SAR ADC of the second level
Two comparators obtain binary code after the signal quantization to being sampled.
Mixed type two-layer configuration for full parellel successive approximation analog-digital converter the most according to claim 2,
It is characterized in that: described digital calibration circuit is electric through digital coding by first order full parellel analog-digital converter Flash ADC
The lowest order of the binary digit output code obtained behind road, obtains with second level successive approximation analog-digital converter SAR ADC
Binary digit output code highest order dislocation be added, obtain final binary digit output code, first order full parellel mould
Intend the use of redundancy function in digital converter Flash ADC to reduce because comparator imbalance voltage is the error of transfer zone.
Mixed type two-layer configuration for full parellel successive approximation analog-digital converter the most according to claim 2,
It is characterized in that: described digital encoding circuit includes thermometer-code-Gray code conversion circuit, Gray code-binary code conversion electricity
Road, in order to effectively eliminate the digital output error brought due to comparator because of metastable state, generally uses Gray code conduct
Intermediate code, is placed between thermometer-code and binary code, thermometer-code is first converted to Gray code, then is two by Gray code conversion
Ary codes.
Mixed type two-layer configuration for full parellel successive approximation analog-digital converter the most according to claim 1,
It is characterized in that: described high-order DAC capacitor array is divided into two arrays, and its total capacitance value is 448C, and every an array is all by 14
Capacitance is the electric capacity composition of 16C, is divided into 128C, 64C, 32C tri-groups from highest order to lowest order, and two row are respectively by altogether
Enjoy switch S1 with 3.5-bit Flash single-chip microcomputer input to be connected；
Described low level DAC capacitor array is divided into two arrays, and its total capacitance value is 64C, and every an array is from highest order to lowest order
Electric capacity be respectively 16C, 8C, 4C, 2C, 1C, 1C, wherein string by share switch S2 and the second comparator anode be connected,
Another row are connected by the negative terminal of shared switch S2 and the second comparator.
Mixed type two-layer configuration for full parellel successive approximation analog-digital converter the most according to claim 1,
It is characterized in that: difference base in high-order electric capacity sole plate level switch controller, bit capacitor sole plate level switch controller
The level switching to plates capacitance at the bottom of corresponding capacitor array is realized, wherein in HCSR algorithm:
The level switching principle of plates capacitance at the bottom of high-order DAC capacitor array is by described HCSR algorithm:
When the highest order quantized result of described first order full parellel analog-digital converter Flash ADC is 000, high-order DAC
The 128C/64C/32C electric capacity sole plate being connected with the second comparator anode in capacitor array is switched to VREF by VCM, with second
The 128C/64C/32C electric capacity sole plate that comparator anode is connected is switched to 0 by VCM；When described first order Flash ADC
When high-order quantized result is 001, the 128C/32C electric capacity sole plate being connected with the second comparator anode in high-order DAC capacitor array
Being switched to VREF, 68C electric capacity sole plate by VCM keeps connection VCM constant, the 128C/32C electricity being connected with the second comparator negative terminal
Holding sole plate and be switched to 0 by VCM, it is constant that 68C electric capacity sole plate keeps connecting VCM；The highest as described first order Flash ADC
Position quantized result is when being 010, the 68C/32C electric capacity sole plate being connected with the second comparator anode in high-order DAC capacitor array by
VCM is switched to VREF, 128C electric capacity sole plate and keeps connection VCM constant, the 68C/32C electric capacity being connected with the second comparator negative terminal
Sole plate is switched to 0 by VCM, and it is constant that 128C electric capacity sole plate keeps connecting VCM；
When the highest order quantized result of described first order full parellel analog-digital converter Flash ADC is 011, high-order DAC
The 32C electric capacity sole plate being connected with the second comparator anode in capacitor array is switched to VREF, 128C/68C electric capacity sole by VCM
It is constant that plate keeps connecting VCM, and the 32C electric capacity sole plate being connected with the second comparator negative terminal is switched to 0 by VCM, 128C/68C electricity
Holding sole plate keeps connection VCM constant；In like manner, the highest as described first order full parellel analog-digital converter Flash ADC
When position quantized result is 100,101,110,111, with above-mentioned four kinds of switching mode contrast；
The level switching principle of plates capacitance at the bottom of low level DAC capacitor array is by described HCSR algorithm:
When in described second level successive approximation analog-digital converter SAR ADC, the highest order of low level DAC capacitor array quantifies knot
When fruit is 0, the 16C electric capacity sole plate being connected with the second comparator anode is switched to VREF by VCM, with the second comparator negative terminal phase
16C electric capacity sole plate even is switched to 0 by VCM；When low level in described second level successive approximation analog-digital converter SAR ADC
When the highest order quantized result of DAC capacitor array is 1, the 16C electric capacity sole plate that the second positive and negative end of comparator is connected keeps connecting
VCM is constant, and by 0, the 32C electric capacity sole plate being connected with the second comparator negative terminal is switched to VCM；8C in low level DAC capacitor array
The switching mode of electric capacity sole plate to be determined jointly according to last time and this quantized result, when last time and this quantization knot
When fruit is 00, the 8C electric capacity sole plate being connected with the second comparator anode is switched to VREF by VCM, with the second comparator negative terminal phase
8C electric capacity sole plate even is switched to 0 by VCM；When last time and this quantized result are 01, the second comparator positive and negative end phase
It is constant that 8C electric capacity sole plate even keeps connecting VCM, is switched by 0 by the 16C electric capacity sole plate being connected with the second comparator negative terminal
To VCM；When last time and this quantized result are 10, the 8C electric capacity sole plate being connected with the second comparator anode is cut by VCM
Changing to VREF, the 8C electric capacity sole plate being connected with the second comparator negative terminal is switched to 0 by VCM；When last time and this quantization knot
When fruit is 11, the 8C electric capacity sole plate being connected with the second comparator anode is switched to 0 by VCM, is connected with the second comparator negative terminal
8C electric capacity sole plate be switched to VREF by VCM；In like manner, the switching of 4C/2C/C/C electric capacity sole plate in low level DAC capacitor array
Mode is identical with the switching mode of 8C, is all jointly to be determined with the quantized result of last time according to this.
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