CN111431534B - Analog-digital converter for quantizing multipath input - Google Patents
Analog-digital converter for quantizing multipath input Download PDFInfo
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- CN111431534B CN111431534B CN202010399223.5A CN202010399223A CN111431534B CN 111431534 B CN111431534 B CN 111431534B CN 202010399223 A CN202010399223 A CN 202010399223A CN 111431534 B CN111431534 B CN 111431534B
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- H03M1/12—Analogue/digital converters
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- H03M1/123—Simultaneous, i.e. using one converter per channel but with common control or reference circuits for multiple converters
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Abstract
The invention belongs to the technical field of data quantization processing in an integrated circuit, and discloses an analog-digital converter for quantizing multipath input, which comprises: the digital-to-analog converter is provided with N groups in total and is used for sampling N paths of input signals simultaneously in quantization processing; the number of each group of digital-to-analog converters is two, the input end of each digital-to-analog converter is connected with a sampling switch, each group of digital-to-analog converters is connected with the positive end and the negative end of the comparator through a selection switch array, and each digital-to-analog converter comprises a capacitor array; the comparator is used for sequentially comparing the quantization difference values of the N groups of input signals; the digital control circuit is connected to the output end of the comparator and executes capacitance setting according to each comparison result of the comparator; in conclusion, the invention can simultaneously complete the quantization processing of the multi-path input signals and has the advantages of low power consumption, less additional circuits, low hardware cost and high quantization efficiency.
Description
Technical Field
The invention belongs to the technical field of data quantization processing in an integrated circuit, and particularly relates to an analog-digital converter for quantizing multipath input.
Background
In recent years, with the rapid development of emerging information technologies such as data, artificial intelligence, internet of things and the like, the method brings deep influence on the economic society. In the internet of things technology, quantization and processing of analog signals collected by end equipment such as a sensor are a crucial link.
Data quantization is a circuit that converts an analog signal into a digital signal and converts the analog signal into the digital signal, and is called an analog-to-digital converter. The existing analog-digital converters are of various types, and mainly include pipeline-structured a/D converters, successive approximation analog-digital converters (SAR ADCs), oversampling analog-digital converters, and the like.
When quantizing a plurality of signals, the conventional analog-to-digital converter generally adopts the following two methods:
(1) As shown in the structure of fig. 1, a plurality of analog-to-digital converters are used to quantize all input signals simultaneously, so as to obtain a plurality of quantization results. However, this method has problems of many additional circuits, complicated implementation, and large power consumption.
(2) As shown in the structure of fig. 2, an analog converter is used to quantize the input signal in a time interleaving manner, and each quantization result is obtained. However, in the method, multiple signals need to be quantized in sequence, that is, a previous input signal is quantized before a next input signal cannot be quantized, so that the problem of poor quantization flexibility exists; in addition, in order to ensure the accuracy of time interleaving, a multi-phase sampling clock needs to be added, the requirement on the accuracy of the multi-phase sampling clock is high, and the hardware cost is increased.
In summary, it can be known that how to realize quantization of multi-path input signals with low cost, high efficiency and flexibility is one of the problems to be solved for the existing analog-digital converter.
Disclosure of Invention
Accordingly, the present invention is directed to an analog-to-digital converter for quantizing multiple inputs, so as to effectively solve the problems in the background art, thereby reducing power consumption, additional circuit and hardware costs during quantization of multiple inputs, and effectively improving quantization efficiency.
In order to achieve the purpose, the invention provides the following technical scheme:
an analog-digital converter for quantizing multiple inputs, mainly comprising a digital-analog converter, a selection switch array, a comparator and a digital control circuit, wherein:
the digital-to-analog converter is provided with N groups in total and is used for sampling N paths of input signals simultaneously in quantization processing; the number of each group of digital-to-analog converters is two, the input end of each digital-to-analog converter is connected with a sampling switch, each group of digital-to-analog converters is connected with the positive end and the negative end of the comparator through a selection switch array, and each digital-to-analog converter comprises a capacitor array to form a capacitance type digital-to-analog converter; during sampling, the sampling switches are closed, common-mode voltage is adopted by an upper plate of a capacitor array in each group of digital-to-analog converters, and positive and negative terminal input signals are respectively adopted by a lower plate;
the comparator is used for sequentially comparing the quantization difference values of the N groups of quantized input signals, sequentially performing multiple comparisons based on the capacitance digits in the capacitance array when performing comparison of one group of input signals, and outputting the last comparison result as a quantization result;
the digital control circuit is connected to the output end of the comparator and executes capacitance setting according to each comparison result of the comparator; and when the comparison of a group of input signals is executed, the set capacitors are used as a group of capacitors to be compared based on the capacitor comparison sequence, and after the group of capacitors to be compared are set, the comparator compares the capacitors according to the set capacitor state.
Preferably, the selection switch array is formed by combining N selection switches, and one selection switch corresponds to one digital-to-analog converter; when a comparison of a set of input signals is performed, the selection switch corresponding to the set of input signals is closed.
Preferably, when the digital-to-analog converter performs sampling, at least one group of selection switches is closed, and the selection switches are used for adjusting the initial voltage of the positive terminal and the negative terminal of the comparator.
Preferably, the initial voltages of the positive and negative terminals of the comparator are both common-mode voltages.
Preferably, the comparator is configured to weight the comparison results of the plurality of times when performing the comparison of the set of input signals, wherein the weight of the comparison result of the first time is the largest.
Preferably, when the comparator sequentially compares the quantized difference values of the quantized N groups of input signals, after each group of input signals is quantized, the selection switch corresponding to the group of input signals is turned off, and the selection switch corresponding to another group of unquantized input signals is turned on.
Preferably, when the comparator sequentially compares the quantization difference values of the quantized N groups of input signals, after each group of input signals is quantized and before the selection switch corresponding to the group of input signals is turned off, the upper board of the capacitor array in the group of digital-to-analog converters is reset, so as to reset the voltages of the positive and negative terminals of the comparator to the initial common mode voltage.
Preferably, each comparison result of the comparator is a high level or a low level, and when the comparison result is the high level, a capacitor connected with the negative end of the comparator in the group of capacitors to be compared is set; and when the comparison result is low level, the capacitor connected with the positive end of the comparator in the group of capacitors to be compared is set.
Preferably, the setting mode of the capacitor is as follows: the lower electrode plate of the capacitor is in a state of being connected with common mode voltage.
Compared with the prior art, the invention has the following beneficial effects:
based on the analog-digital converter provided by the invention, a plurality of paths of input signals can be quantized simultaneously, and in the quantization process:
compared with the traditional method using a plurality of analog-digital converters, the method only uses one analog-digital converter, reduces circuit devices, circuit complexity and cost, and reduces circuit power consumption;
compared with the traditional method of using one digital-to-analog converter and adopting a time interleaving mode for quantization, the method provided by the invention can simultaneously sample and quantize multiple paths of input signals without time interleaving or setting a precise multiphase sampling clock, thereby effectively reducing the design difficulty of the digital-to-analog converter and reducing the hardware cost.
In addition, in the whole quantization process, the quantization selection order of the input signals is not sequential based on the reset operation, so that the flexibility of circuit quantization is effectively increased.
Drawings
FIG. 1 is a schematic diagram of a conventional multi-channel quantization method using a plurality of analog-to-digital converters;
FIG. 2 is a schematic diagram of a conventional architecture for time-interleaved multi-channel quantization using an analog-to-digital converter;
FIG. 3 is a schematic diagram of an analog-to-digital converter according to the present invention;
FIG. 4 is a flow chart of the multi-channel quantization using the ADC according to the present invention;
FIG. 5 is a schematic diagram of a capacitive DAC circuit of the ADC according to the present invention;
fig. 6 is a timing chart of quantization cycles when performing multi-channel quantization using the adc according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the present invention, a quantized multi-input adc is provided, and the specific structure thereof is shown in fig. 3, and mainly includes a digital-to-analog converter, a selection switch array, a comparator and a digital control circuit, wherein:
the digital-analog converters are provided with N groups, and the number of each group of digital-analog converters is two, and the two groups of digital-analog converters are used for simultaneously sampling 2N paths of input signals in quantization processing; the input end of each digital-to-analog converter is connected with a sampling switch, each group of digital-to-analog converters is connected with the positive end and the negative end of the comparator through a selection switch array, and each digital-to-analog converter comprises a capacitor array to form a capacitance type digital-to-analog converter;
the comparator is used for sequentially comparing the quantized difference values of the quantized N groups of input signals;
the digital control circuit is connected to the output end of the comparator and executes capacitance setting according to each comparison result of the comparator.
Based on the above disclosure, a specific process for quantizing a plurality of input signals is provided, and the process is shown in fig. 4, and specifically includes the following steps:
s1, a sampling stage: closing the sampling switches to enable an upper-level board of a capacitor array in each group of digital-to-analog converters to acquire common-mode voltage, and enabling a lower-level board to acquire positive and negative terminal input signals respectively, so that 1-N groups of differential input signals are sampled simultaneously through N groups of digital-to-analog converters, and each group of input signals comprises a positive terminal input signal and a negative terminal input signal; at the same time, at least one set of selection switches is closed, so that the voltages at the two ends of the comparator reach the common-mode voltage, thereby defining the initial voltage of the comparator (the set of selection switches corresponding to the closed signal 1 are shown in fig. 3 and 5).
And S2, after sampling is finished, disconnecting all sampling switches and all selection switches.
S3, quantization stage: arbitrarily selecting a path of input signals to start quantization, specifically taking a quantized signal 1 as an example: selecting a selection switch corresponding to the signal 1 to be closed, respectively obtaining a positive input signal 1 and a negative input signal 1 at two ends of a comparator, comparing the positive input signal 1 and the negative input signal 1 to obtain a first comparison result, and setting the capacitor array in the digital-analog converter group by the digital control circuit according to the first comparison result;
specifically, referring to fig. 5, in the process of performing quantization comparison, a plurality of capacitors in the capacitor array are sequentially compared according to a comparison sequence from left to right in fig. 5, so that after a first comparison result is obtained, a leftmost group of capacitors (capacitors at positive and negative ends) in the capacitor array is controlled by the digital control circuit to be set, where the leftmost group of capacitors is a group of capacitors to be compared in the quantization state.
Further, the capacitor setting mode is as follows: the lower electrode plate of the capacitor is in a state of being connected with common mode voltage.
Furthermore, the comparison result obtained after the comparison by the comparator is high level or low level; wherein: when the first comparison result is high level, setting the capacitor connected with the negative end of the comparator in the group of capacitors at the leftmost side, wherein the positive end of the comparator is connected with 1, and the negative end of the comparator is connected with 0, so that the second comparison is carried out, and the second comparison result is obtained; when the first comparison result is low level, setting the capacitor connected with the positive end of the comparator in the leftmost group of capacitors, connecting the positive end of the comparator to 0, and connecting the negative end of the comparator to 1, thereby performing second comparison and obtaining a second comparison result;
in conclusion, setting the second group of capacitors from left to right according to the second comparison result, and repeating the comparison; therefore, the comparison of a plurality of groups of capacitors in the capacitor array is sequentially completed, the last comparison result is obtained after the comparison of the last group of capacitors is completed, the last comparison result is taken as the quantization result of the group of input signals (signals 1), and the quantization result is the quantization difference value of the positive input signal 1 and the negative input signal 1.
In addition, in the process of the multiple comparisons, a certain weight is set every time a comparison result is obtained, and the weight is formed through self-defined presetting, wherein the weight of the first comparison result is the largest.
S4, resetting: after the quantization of the group of signals (signal 1) disclosed in the step S3 is completed, resetting the upper plate of the capacitor array in the group of digital-to-analog converters, thereby ensuring that the voltages of the positive and negative terminals of the comparator are both reset to the initial common mode voltage; the closed selection switches (i.e., the set of selection switches corresponding to signal 1) are opened after the comparator voltage reset is completed.
Therefore, the effect that quantization of each path of input signals is not in sequence can be effectively achieved, and therefore a certain path of input signals needing quantization can be selected randomly according to needs, and flexibility of circuit quantization is improved.
And S5, randomly selecting a selection switch corresponding to the other input signal (specifically, signals except the signal 1), and repeating the steps S3-S5 until the quantization of the n input signals is completed.
To sum up, the whole analog-to-digital converter samples signals at the same time and quantizes the signals in sequence, thereby achieving the purpose of quantizing multiple input signals at the same time.
In addition, for the above quantization process, the quantization of one input signal is changed into one small period, then n small periods form a large period for the simultaneous quantization of n input signals, and a specific timing chart for the simultaneous quantization of n input signals is shown in fig. 6; as can be seen from the figure, in the overall quantization process:
and quantizing the first group of signals in the first small quantizing period, wherein other groups of signals are in an idle state. And after the first group of signals are quantized, a second small quantization period is entered, the second group of signals are quantized, and at the moment, other groups of signals are in an idle state. And by analogy, when the quantization of the last group of signals is carried out in the last small quantization period, other groups of signals are in an idle state. And after the quantization of the last group of signals is finished, all the signals are quantized, and the quantization period is finished.
It should be noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (2)
1. An analog-to-digital converter for quantizing multiple inputs, mainly comprising a digital-to-analog converter, a selection switch array, a comparator and a digital control circuit, wherein:
the digital-analog converters are provided with N groups, and the number of each group of digital-analog converters is two, and the two groups of digital-analog converters are used for simultaneously sampling 2N paths of input signals in quantization processing; the input end of each digital-analog converter is connected with a sampling switch, each digital-analog converter is connected with the positive end and the negative end of the comparator through a selection switch array, and each digital-analog converter comprises a capacitor array to form a capacitance type digital-analog converter; during sampling, the sampling switches are closed, common-mode voltage is adopted by upper plates of capacitor arrays in each group of digital-to-analog converters, and positive and negative end input signals are respectively adopted by lower plates;
the comparator is used for sequentially comparing the quantization difference values of the N groups of quantized input signals, sequentially performing multiple comparisons based on the capacitance digits in the capacitance array when performing comparison of one group of input signals, and outputting the last comparison result as a quantization result;
the digital control circuit is connected to the output end of the comparator and executes capacitance setting according to each comparison result of the comparator; when the comparison of a group of input signals is executed, the set capacitors are used as a group of capacitors to be compared based on the capacitor comparison sequence, and after the group of capacitors to be compared are set, the comparator compares the capacitors according to the set capacitor state;
specifically, the method comprises the following steps:
when the digital-to-analog converter performs sampling, at least one group of selection switches are closed and used for adjusting the initial voltages of the positive terminal and the negative terminal of the comparator, and the initial voltages of the positive terminal and the negative terminal of the comparator are common-mode voltages;
the selection switch array is formed by combining N selection switches, and one selection switch corresponds to one digital-to-analog converter; while performing the comparison of the set of input signals, closing a selection switch corresponding to the set of input signals;
the comparator respectively adds weights to comparison results of multiple times when performing comparison of a group of input signals, wherein the weight of the comparison result of the first time is the largest;
when the comparator compares the quantization difference values of N groups of quantized input signals in sequence, after each group of input signals is quantized, the selection switch corresponding to the group of input signals is switched off, and the selection switch corresponding to the other group of unquantized input signals is switched on;
when the comparator compares the quantization difference values of N groups of quantized input signals in sequence, resetting an upper-level plate of a capacitor array in the group of digital-to-analog converters after the quantization of one group of input signals is finished and before a selection switch corresponding to the group of input signals is switched off, and resetting the voltages of the positive terminal and the negative terminal of the comparator to an initial common-mode voltage;
each comparison result of the comparator is high level or low level, and when the comparison result is high level, the capacitor connected with the negative end of the comparator in the group of capacitors to be compared is set; and when the comparison result is low level, the capacitor connected with the positive end of the comparator in the group of capacitors to be compared is set.
2. The adc of claim 1, wherein said capacitor is set by: the lower electrode plate of the capacitor is in a state of being connected with common mode voltage.
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| CN112130482A (en) * | 2020-08-24 | 2020-12-25 | 南开大学深圳研究院 | Quantization system and method for separately quantizing low-frequency component and high-frequency component of signal |
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