CN107517059B - Circuit and method for improving conversion speed of analog-to-digital converter - Google Patents
Circuit and method for improving conversion speed of analog-to-digital converter Download PDFInfo
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- CN107517059B CN107517059B CN201710898603.1A CN201710898603A CN107517059B CN 107517059 B CN107517059 B CN 107517059B CN 201710898603 A CN201710898603 A CN 201710898603A CN 107517059 B CN107517059 B CN 107517059B
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 239000003990 capacitor Substances 0.000 claims abstract description 96
- 238000013139 quantization Methods 0.000 claims abstract description 23
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/44—Sequential comparisons in series-connected stages with change in value of analogue signal
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention relates to the field of data converters, in particular to a circuit for improving the conversion speed of an analog-to-digital converter by utilizing a pre-quantization circuit, wherein the circuit comprises a digital-to-analog converter and the pre-quantization circuit, and the digital-to-analog converter consists of a switch circuit, a decoding circuit, a resistor array and a capacitor array; the invention also discloses a method for improving the conversion speed of the analog-to-digital converter, which reduces K conversion periods of the ADC because the high-K capacitor does not participate in the conversion of the ADC, and greatly improves the application frequency of the ADC because the capacitor array is of a binary weighted structure, the capacitance value of the low bit is smaller than that of the high bit, the required charge and discharge time is short, and the time required by each conversion period of the ADC is shortened.
Description
Technical Field
The present invention relates to the field of data converters, and in particular, to a circuit and method for increasing the conversion speed of an analog-to-digital converter using a pre-quantization circuit.
Background
Analog-to-digital converters (ADCs), hereinafter referred to as ADCs, are devices that convert continuous variable analog signals into discrete digital signals, and are key components of analog and digital system interfaces, and according to the resolution and speed, analog-to-digital converters can be classified into various types of converters, in which successive approximation ADCs have comprehensive advantages in terms of accuracy and speed, and are widely used in the market.
As shown in fig. 1, the successive approximation ADC mainly includes a sampling circuit, a comparator, a successive approximation logic circuit, and a digital-to-analog conversion circuit (DAC), hereinafter referred to as DAC, that generates a digital code bit by sequentially comparing a sampling value of an input signal with a reference voltage value generated by the DAC.
Depending on the DAC structure, the successive approximation ADC may be classified into a charge redistribution type, a resistor scaling type, a capacitor-resistor hybrid type, and the like, wherein the capacitor-resistor hybrid type combines the advantages of the resistor type and the charge distribution type, and thus is commonly used in the successive approximation ADC, and fig. 1 is a schematic circuit diagram of a general capacitor-resistor hybrid DAC.
As shown in fig. 2, the operation process of the successive approximation ADC includes two processes of sampling and conversion, the sampling stage samples an externally input analog signal to the capacitor array, the conversion stage generates a digital code bit by the sampled signal through the successive approximation algorithm, if the resolution of the ADC is N bits, N conversion clock cycles are required, the operation speed of the ADC is mainly affected by the charge and discharge speed of the capacitor array, and in the sampling stage and N conversion cycles, the capacitors are continuously charged and discharged, the number of capacitors is increased in a geometric progression manner every time the resolution of the ADC is increased, and the required charge and discharge time constant is also increased, so that for a high-precision ADC, the sampling frequency is greatly limited by a large capacitor.
In order to solve the above problems, it is necessary to invent an analog-to-digital converter circuit and method for increasing the sampling frequency and reducing the ADC conversion time.
Disclosure of Invention
The invention aims to overcome the defects in the prior art and provide a circuit and a method capable of improving the sampling frequency, the conversion speed and the accuracy of an analog-to-digital converter through a pre-quantization circuit.
In order to achieve the above purpose, the present invention provides the following technical solutions.
A circuit for increasing the conversion speed of an analog-to-digital converter, comprising:
the digital-to-analog converter consists of a switch circuit, a decoding circuit, a resistor array and a capacitor array;
and the pre-quantization circuit is respectively connected with the capacitor array and the resistor array.
As a preferred scheme of the invention, the switch circuit is respectively connected with reference voltage, standard input, high level of digital signal and ground;
the decoding circuit is respectively connected with the resistor array and the low bits of the digital signals;
the resistor array is composed of 2 K The resistors are connected in series and respectively comprise a first resistor, a second resistor and a 2 nd resistor K A resistor, wherein each resistor has a resistance equal to or greater than 1, K is a positive integer, one end of the first resistor is connected to a reference voltage, the other end of the first resistor is connected to one end of the second resistor, and so on, the (2 K -1) the other end of the resistor is connected toThe 2 nd K One end of the resistor is connected with the 2 nd K The other end of the resistor is grounded;
the capacitor array consists of M-bit capacitors, wherein the M-bit capacitors are of a binary weighted capacitor structure, M is larger than K, the M-bit capacitors consist of high-K-bit capacitors, middle-bit capacitors and low-bit capacitors, the positive ends of the M-bit capacitors are connected with the output, the negative ends of the high-K-bit capacitors are connected with the pre-quantization circuit, the negative ends of the lowest-bit capacitors are connected with the decoding circuit, and the negative ends of the middle-bit capacitors are connected with the switch circuit;
the high-K bit capacitor consists of a capacitor 2 M-K C to 2 M-1 C, the neutral capacitance is composed of the capacitances C to 2 M-K-1 And C, wherein the low-order capacitor is a capacitor C.
As a preferred embodiment of the present invention, the pre-quantization circuit is composed of a comparator array and a binary decoding circuit, the comparator array is composed of (2 K -1) comparator group, (2 K -1) the positive poles of said comparators are connected to the input, (2) K -1) the cathodes of the comparators are respectively connected between two of the resistors, i.e. one of the comparators is connected between each two of the resistors, (2) K -1) the other ends of the comparators are connected to the binary decoding circuit.
As a preferred embodiment of the present invention, the comparator is a high-speed comparator.
As a preferable scheme of the invention, the capacitor array is a high-order capacitor array, and the resistor array is a low-order resistor array.
The working principle of the pre-quantization circuit is as follows: after the ADC sampling is finished, comparing the voltage value divided by the resistor array with the sampling voltage value, wherein the positive end of the comparator array is connected with the sampling voltage, and the negative end of each comparator of the comparator array is respectively connected with each output voltage divided by the resistor array, (2) K -1) the comparators can be derived (2 K -1) comparing values, the comparator outputting a high level when the sampled voltage is greater than the voltage value divided by the resistor array, the sampled voltage being greater than the voltage value divided by the resistor arrayFor an hour, the comparator outputs a low level, (2) K -1) the comparison values are arranged from high to low to form a thermometer code, i.e. "11. 100. 0", the decoding circuit compares the values (2) K The thermometer code of the bit is converted into a binary code of K bit, which is used as a conversion result of the high K bit of the ADC, and the conversion result is assigned to the high K bit capacitor in the capacitor array, because the high K bit result is generated before the ADC starts conversion, after the ADC starts conversion, the conversion is started from the capacitor of M-K bit, the common successive approximation logic is used, the capacitor of M-K bit, the capacitor of M-K-1 bit, the capacitor of 1 bit, the resistor of K-1 bit, the resistor of … of 1 bit, and the resistor of 1 bit are sequentially compared, so that the digital value of the rest N-K bit of the ADC is generated, K conversion periods are reduced in the conversion process of the ADC, and because the capacitor array adopts a binary weighted capacitor structure, the capacitance value of the low bit capacitor is much smaller than that of the high K bit capacitor does not participate in conversion, the time constant of charge and discharge of the low bit capacitor is reduced, and therefore the time of each conversion period of the ADC can be greatly shortened, and the conversion speed of the ADC is improved.
The invention uses the resistance array to make the pre-quantization tool of the high-K capacitor, because the resistance array has monotonicity characteristic, can guarantee ADC high-order linearity, the resistance array not only participates in ADC low-K quantization, but also is the tool of the pre-quantization of the high-K capacitor, in order that the resistance array divides the voltage and adopts the comparison of the voltage can produce the result fast, use the high-speed comparator, the circuit structure of the high-speed comparator adopts the form of the preamplifier + latch amplifier, the preamplifier increases the change amplitude of the input signal, then add this signal to the latch amplifier and amplify again, in order to meet the output level requirement of the digital circuit, finally the RS flip-flop latches the output result of the amplifier, the preamplifier has characteristic of the negative index response, and the latch adopts the positive feedback structure, have positive index response characteristic, combine the two, has accelerated the comparison speed of the comparator, it has characteristic of the response speed is fast, the precision is high.
Consider that 2 is used K -1 high-speed comparatorThe overall power consumption is relatively high, the comparator can be turned off after each pre-quantization is finished, and in addition, the inherent input offset error of the comparator can influence the voltage comparison result, and an input offset eliminating circuit can be added in the pre-amplifier.
The ADC conversion process of the invention is added with a pre-quantization period, and simultaneously K conversion periods are reduced, the time of each conversion period is greatly shortened, and the time of the pre-quantization period is less than the time of one conversion period.
A method of increasing the conversion speed of an analog-to-digital converter, comprising the steps of:
step one, sampling: sampling by an analog-to-digital converter;
step two, pre-quantifying: comparing the resistor array voltage division with the sampling voltage to obtain a high-K bit comparison result of the analog-to-digital converter;
assigning a value to a high-K-bit capacitor in the capacitor array;
step four, conversion: and starting conversion from the capacitance of the M-K bit, sequentially quantizing the rest capacitance bits and resistance bits, and obtaining the result of the ADC low N-K bit.
Compared with the prior art, the invention has the beneficial effects that: the high-K capacitor does not participate in the conversion of the ADC, so that the ADC reduces K conversion periods, in addition, the capacitor array is of a binary weighted structure, the capacitance value of the low bit is smaller than that of the high bit, the required charge and discharge time is short, the time required by each conversion period of the ADC is shortened, and the adoption frequency of the ADC is greatly improved.
Drawings
FIG. 1 is a prior art circuit diagram;
FIG. 2 is a diagram of a prior art analog-to-digital conversion process;
FIG. 3 is a circuit diagram of the present invention;
FIG. 4 is a diagram of an analog-to-digital conversion process according to the present invention;
FIG. 5 is a circuit diagram of a high-speed comparator according to the present invention;
FIG. 6 is a flow chart of the present invention;
fig. 7 is a circuit diagram of an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the following examples and embodiments, but it should not be construed that the scope of the present invention is limited to the following examples, and all techniques realized based on the present invention are within the scope of the present invention.
As shown in fig. 7, a circuit for increasing the conversion speed of an analog-to-digital converter includes a digital-to-analog converter and a pre-quantization circuit, wherein the digital-to-analog converter in the embodiment is a 6-bit digital-to-analog converter, the digital-to-analog converter is composed of a switch circuit, a decoding circuit, a resistor array and a capacitor array, and the pre-quantization circuit is respectively connected with the capacitor array and the resistor array; the switching circuit is respectively connected with the reference voltage VREF, the standard input VIN, the digital signal high-order M-MSBs and the ground GND, and the decoding circuit is respectively connected with the resistor array and the digital signal low-order K-LSBs; the resistor array consists of 4 resistors which are connected in series and are respectively a first resistor, a second resistor, a third resistor and a fourth resistor, the resistance values of the four resistors are equal, one end of the first resistor is connected with a reference voltage, the other end of the first resistor is connected with one end of the second resistor, the other end of the second resistor is connected with one section of the third resistor, the other end of the third resistor is connected with the fourth resistor, the other end of the fourth resistor is grounded, and the resistor array consisting of the 4 resistors is a low-order resistor array; the capacitor array is composed of 5 capacitors which are connected in parallel and are respectively a first capacitor C, a second capacitor C, a third capacitor 2C, a fourth capacitor 4C and a fifth capacitor 8C, the capacitance values of all the capacitors are different, each capacitor adopts a binary weighted capacitor structure, the capacitance value of the low-order capacitor is much smaller than that of the high-order capacitor, the positive ends of the 5 capacitors are connected with an output Vout, the other end of the first capacitor is connected with a decoding circuit, the other ends of the second capacitor and the third capacitor are connected with a switch circuit, the other ends of the fourth capacitor and the fifth capacitor are connected with a binary decoding circuit, and the capacitor array composed of the 5 capacitors is a high-order capacitor array.
The pre-quantization circuit consists of a comparator array and a binary decoding circuit, wherein the comparator array consists of 3 comparators, the anodes of the 3 comparators are connected with the input end VIN, the cathodes of the 3 comparators are respectively connected between two resistors, namely, the cathodes of one comparator are connected between every two resistors, and the other ends of the 3 comparators are connected with the binary decoding circuit.
The pre-quantization process of the pre-quantization circuit is added with a pre-quantization process, 2 conversion periods are reduced, and the time of each conversion period of the ADC is also greatly shortened because the high-order capacitor does not participate in conversion
As shown in FIG. 5, the 3 comparators are all high-speed comparators, the high-speed comparators are in the form of a pre-amplifier and a latch amplifier, the pre-amplifier increases the variation amplitude of an input signal, then the signal is added to the latch amplifier for re-amplification so as to meet the output level requirement of a digital circuit, finally, the output result of the RS Flip-Flop latch amplifier is output by the RS Flip-Flop, the pre-amplifier has the characteristic of negative exponential response, and the latch adopts a positive feedback structure and has the characteristic of positive exponential response, and the pre-amplifier and the latch are combined, so that the comparison speed of the comparator is accelerated, and the high-speed comparator has the characteristics of high response speed and high precision.
As shown in fig. 6, a method for increasing the conversion speed of an analog-to-digital converter includes the following steps:
step one, sampling: sampling by an analog-to-digital converter;
step two, pre-quantifying: comparing the resistor array voltage division with the sampling voltage to obtain a high-K bit comparison result of the analog-to-digital converter;
assigning a value to a high-K-bit capacitor in the capacitor array;
step four, conversion: starting the conversion from the capacitance of the M-K bit, quantizing the remaining capacitance bits and resistance bits successively, and obtaining the result of the ADC low N-K bits, in this embodiment k=2, m=4, then n=6.
Claims (4)
1. A circuit for increasing the conversion speed of an analog-to-digital converter, comprising:
the digital-to-analog converter consists of a switch circuit, a decoding circuit, a resistor array and a capacitor array;
the switch circuit is respectively connected with reference voltage, standard input, high level of digital signal and ground;
the decoding circuit is respectively connected with the resistor array and the low bits of the digital signals;
the resistor array is composed of 2 K The resistors are connected in series and respectively comprise a first resistor, a second resistor and a 2 nd resistor K A resistor, wherein each resistor has a resistance equal to or greater than 1, K is a positive integer, one end of the first resistor is connected to a reference voltage, the other end of the first resistor is connected to one end of the second resistor, and so on, the (2 K -1) the other end of the resistor is connected to said 2 nd K One end of the resistor is connected with the 2 nd K The other end of the resistor is grounded;
the capacitor array consists of M-bit capacitors, wherein the M-bit capacitors are of a binary weighted capacitor structure, M is larger than K, the M-bit capacitors consist of high-K-bit capacitors, middle-bit capacitors and low-bit capacitors, the positive ends of the M-bit capacitors are connected with the output, the negative ends of the high-K-bit capacitors are connected with a pre-quantization circuit, the negative ends of the lowest-bit capacitors are connected with the decoding circuit, the negative ends of the middle-bit capacitors are connected with the switch circuit, and the high-K-bit capacitors consist of capacitors 2 M-K C to 2 M-1 C, the neutral capacitance is composed of the capacitances C to 2 M -K-1 C, the low-order capacitor is a capacitor C;
the pre-quantization circuit is respectively connected with the capacitor array and the resistor array;
the pre-quantization circuit is composed of a comparator array and a binary coding circuit, the comparator array is composed of (2) K -1) comparator group, (2 K -1) the positive poles of said comparators are connected to the input, (2) K -1) the cathodes of the comparators are respectively connected between two of the resistors, i.e. one of the comparators is connected between each two of the resistors, (2) K -1) the other ends of the comparators are connected with the binary decoding circuit, the binary decoding circuit is connected with the negative end of the high-K bit capacitor, the positive end of the comparator is connected with the input end, the negative electrode of the comparator array is connected with the resistor array, and the other end of the comparator array is connected with the binary decoding circuit;
the comparator is provided with an offset cancellation circuit to cancel the input offset error inherent to the comparator.
2. A circuit for increasing the conversion speed of an analog-to-digital converter as recited in claim 1, wherein: the comparator is a high-speed comparator, and the capacitor adopts a binary weighted capacitor structure.
3. A circuit for increasing the conversion speed of an analog-to-digital converter as recited in claim 1, wherein: the capacitor array is a high-order capacitor array, and the resistor array is a low-order resistor array.
4. A method of increasing the conversion speed of an analog to digital converter using the circuit of claim 1, comprising the steps of:
step one, sampling: sampling by an analog-to-digital converter;
step two, pre-quantifying: the voltage division of the resistor array is compared with the sampling voltage to obtain a high-K bit comparison result of the analog-to-digital converter, and the high-K bit comparison result is assigned to a high-K bit capacitor in the capacitor array;
step three, conversion: and starting conversion from the capacitance of the M-K bit, sequentially quantizing the rest capacitance bits and resistance bits, and obtaining the result of the ADC low N-K bit.
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| CN207427126U (en) * | 2017-09-28 | 2018-05-29 | 成都启英泰伦科技有限公司 | A kind of circuit for improving analog-digital converter conversion speed |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US8228221B2 (en) * | 2010-09-28 | 2012-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for calibrating sigma-delta modulator |
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- 2017-09-28 CN CN201710898603.1A patent/CN107517059B/en active Active
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| JPH07321656A (en) * | 1994-05-27 | 1995-12-08 | Hitachi Ltd | A/d converter and microcomputer mounted a/d converter |
| CA2475974A1 (en) * | 2002-02-12 | 2003-08-21 | Qualcomm Incorporated | Frequency-timing control loop for wireless communication systems |
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