CN106201759A - A kind of detecting system preventing FPGA depositor adhesion and method - Google Patents
A kind of detecting system preventing FPGA depositor adhesion and method Download PDFInfo
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- CN106201759A CN106201759A CN201610564573.6A CN201610564573A CN106201759A CN 106201759 A CN106201759 A CN 106201759A CN 201610564573 A CN201610564573 A CN 201610564573A CN 106201759 A CN106201759 A CN 106201759A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a kind of detecting system preventing FPGA depositor adhesion, including data acquisition module, data register module, data detection module, described data acquisition module carries out multi collect to the detection signal after Filtering Processing and the data every time collected is stored in data register module, the data collected are judged by described data detection module, when the data of interpretation collection are improper data, it is judged that FPGA depositor sticks together mistake.The present invention also provides for a kind of detection method preventing FPGA depositor adhesion.The technical solution used in the present invention, it is not necessary to judge to gather the correctness of data by fpga chip, reduce the error in data that FPGA depositor adhesion causes, the safety of raising system, and the data gathered can export in real time, it is not necessary to one cycle of time delay, it is ensured that the real-time of data.
Description
Technical field
The present invention relates to field of computer technology, particularly relate to prevent the detection technique of FPGA depositor adhesion.
Background technology
Owing to FPGA can realize the collection to different pieces of information, and picking rate block flexibly, therefore in signaling system
Either computer interlock (computer-based interlocking, CBI) or vehicle-mounted automatic train protection system
Core row control subsystems such as (AUTO train protection, ATP), is required for using FPGA to gather the external data of coming.
The correctness that FPGA gathers data is extremely important to system, and the detection to the data that FPGA gathers at present relies primarily on
Two aspects: one, rely on fpga chip oneself that data carry out detection and judge；Two, it is sent to after the data encoding that will collect
Third party's processor (such as ARM, POWER PC) judges.
At present conventional both modes all cannot be correct the depositor judging fpga chip itself whether stick together
Afterwards the data of mistake are carried out situation about processing.
1.FPGA chip self judgment mode
When this detection mode relates to system safe, it is necessary to assure the correctness of data, especially can not be by error number
It is judged that one-tenth just data, this is to can not put up with in track traffic, Aero-Space etc. for the occasion that security requirement is the highest
Mistake.This mode is very easy to, owing to the depositor of fpga chip own sticks together, the data of mistake are treated as just data
Upload, the most still use single pass board.After this kind of Data Detection mode directly gathers external data, basis is true
Data directly judged by fpga chip.It is that 8 ' h06, FPGA directly enter according to these data that such as FPGA collects external data
Row judges.This detection mode i.e. can determine whether data correctness without encoding, but the misjudgment that this detection method cannot be correct
The source of data, is by the initial data gathered or owing to FPGA occurs depositor adhesion to cause on earth.
2.FPGA gathers comparing coding
The method needs to carry out auxiliary group of data diagnosis by third party's processor, the cycle that outside is collected by FPGA
Data carry out being sent to CPU after corresponding data compare coding and do corresponding judgement process, and it is 8 ' that such as FPGA collects data
H06, processes by being sent to CPU interpretation after being encoded into 8 ' hCF with specific depositor comparison operation.Comparison data cataloged procedure
If it occur that to CPU, CPU, the data that depositor adhesion FPGA can send adhesion cannot judge that depositor has been sent out always
Send adhesion, and also the safety of system can be endangered.Just can carry out owing to FPGA needs to collect a complete cycle data
Corresponding coding, so CPU cannot obtain the data collected in real time, corresponding data all needs one cycle of time delay.In addition the party
The data in one cycle of method collection need to redirect realization by state machine, the depositor of FPGA be very easy to stick together after always
Data before transmission, and CPU cannot judge that FPGA depositor have sent adhesion.
Summary of the invention
The technical problem to be solved is just to provide a kind of detecting system preventing FPGA depositor adhesion and side
Method, it is ensured that the correctness of data, real-time, it is possible to quickly effectively detect whether FPGA occurs depositor adhesion.
For solving above-mentioned technical problem, the present invention adopts the following technical scheme that a kind of inspection preventing FPGA depositor adhesion
Examining system, including data acquisition module, data register module, data detection module, described data acquisition module is to Filtering Processing
After detection signal carry out multi collect and the data every time collected be stored in data register module, described Data Detection
The data collected are judged by module, when the data of interpretation collection are improper data, it is judged that FPGA depositor is sent out
Raw adhesion mistake.
Preferably carrying out 8 times to gather, 8 collection data are formed 8 bit data, the rising edge in reference signal will gather data
It is sent to data detection module, it is not necessary to FPGA judges to decrease owing to FPGA makes mistakes the erroneous judgement caused, and increases the safety of system
Property, and data can complete collection and the judgement of data within a cycle, it is provided that the real-time of data.Data detection module
It is improper data, it is judged that FPGA depositor sticks together when data height 4 bit data of interpretation collection are the most constant
Mistake.
Preferably, described data register module is the depositor of 8.
The corresponding above-mentioned detecting system preventing FPGA depositor adhesion, it is provided that a kind of detection preventing FPGA depositor adhesion
Method, first, FPGA carries out multi collect to the detection signal after Filtering Processing and stores the data collected every time to number
According in registration module；Then the data collected are transmitted directly to processor and carry out the judgement of data；Finally, when interpretation collection
Data when being improper data, then judge that FPGA depositor sticks together mistake.
The collection of current logarithmic evidence is being divided into 4 collections of height, and the trailing edge in reference signal starts to gather data, in ginseng
Examine the rising edge of signal to be i.e. sent to CPU and do data and judge, it is not necessary to one cycle of time delay i.e. can determine whether information again, and data are only
Can there is several correct combination, occur that high-low-position data are identical and constant can judge depositor adhesion.
Preferably, the detection signal after Filtering Processing is acquired by FPGA, adopts altogether 8 times, moving of low and high level change
Carry out continuous 4 times when state pulse comes to gather；And the 12.19ms after reference signal trailing edge carries out ensuing 4 times and gathers,
Gather is spaced apart 8.19ms every time.
Preferably, between the 6ms after 2ms and trailing edge before reference signal trailing edge, appearance height is not all had to become
During the dynamic pulse changed, then during 6ms after reference signal trailing edge, external input signal is carried out continuous 4 times and gathers, and
12.19ms after PHR trailing edge carries out ensuing 4 times being interrupted gathering, and gather is spaced apart 8.19ms every time.
Cycle reference signal is 65.52ms, and the data of collection are 8 bit data, it is therefore desirable to data within a cycle
Gathering 8 times, the detection signal owing to sending contains the pulse signal of a 0.8ms, it is necessary first to FPGA judges whether
This dynamic pulse signal determines different signals collecting strategies, if there is dynamic pulse, it is contemplated that prolonging of hardware device
Time and signal stabilization time, then in FPGA needs 0.8ms after reference signal trailing edge, continuous acquisition 4 times, exists afterwards
Gather 4 times every 8.19ms, at reference signal rising edge, 8 bit data are sent to CPU and make a decision.If there is no dynamic arteries and veins
Punching, it is contemplated that the time delay of hardware device and signal stabilization time, then in FPGA needs the 6ms after reference signal trailing edge
Continuous acquisition 4 times, is gathering 4 times every 8.19ms afterwards, at reference signal rising edge, 8 bit data is being sent to CPU and makes a decision.
Every time acquisition time be all consider hardware time delay after determine, now collected signal stablize that to there is not signal dry
Disturb, gather data accurately and reliably, beneficially the correct judgement of data.
The technical solution used in the present invention, the data that outside inputs are acquired and are transmitted directly to processor and enter by FPGA
The judgement of row data, it is not necessary to judge to gather the correctness of data by fpga chip, reduces what FPGA depositor adhesion caused
Error in data, improves the safety of system, and the data gathered can export in real time, it is not necessary to one cycle of time delay, it is ensured that
The real-time of data, processor also is able to quickly effectively detect whether FPGA occurs depositor adhesion, it is ensured that judgement fast
Speed is efficiently.
Accompanying drawing explanation
The invention will be further described with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is the theory diagram of the present invention；
Fig. 2 is the sequential chart that FPGA data gathers.
Detailed description of the invention
As depicted in figs. 1 and 2, a kind of detecting system preventing FPGA depositor adhesion, including data acquisition module, data
Registration module, data detection module, data register module is the depositor of 8.
Detection signal after Filtering Processing is carried out even after the trailing edge of reference signal arrives by described data acquisition module
Gather and the data every time collected are stored in data register module for continuous 8 times, 8 collection data are formed 8 bit data,
Collection data are sent to data detection module by the rising edge of reference signal, it is not necessary to FPGA judges to decrease to draw owing to FPGA makes mistakes
The erroneous judgement risen, increase the safety of system, and data can complete collection and the judgement of data within a cycle, it is provided that
The real-time of data.The data collected are judged by described data detection module, when data height 4 figure places that interpretation gathers
According to being improper data time the most constant, it is judged that FPGA depositor sticks together mistake.
The corresponding above-mentioned detecting system preventing FPGA depositor adhesion, it is provided that a kind of detection preventing FPGA depositor adhesion
Method, first, FPGA carries out multi collect to the detection signal after Filtering Processing and stores the data collected every time to number
According in registration module；Then the data collected are transmitted directly to processor and carry out the judgement of data；Finally, when interpretation collection
Data when being improper data, then judge that FPGA depositor sticks together mistake.
The collection of current logarithmic evidence is being divided into 4 collections of height, and the trailing edge in reference signal starts to gather data, in ginseng
Examine the rising edge of signal to be i.e. sent to CPU and do data and judge, it is not necessary to one cycle of time delay i.e. can determine whether information again, and data are only
Can there is several correct combination, occur that high-low-position data are identical and constant can judge depositor adhesion.
Detection signal after Filtering Processing is acquired by FPGA, adopts altogether 8 times, and the dynamic pulse in low and high level change comes
Shi Jinhang gathers for continuous 4 times；And the 12.19ms after reference signal trailing edge carries out ensuing 4 times and gathers, gather every time
Be spaced apart 8.19ms.Between 6ms after 2ms and trailing edge before reference signal trailing edge, appearance height is not all had to become
During the dynamic pulse changed, then during 6ms after reference signal trailing edge, external input signal is carried out continuous 4 times and gathers, and
12.19ms after PHR trailing edge carries out ensuing 4 times being interrupted gathering, and gather is spaced apart 8.19ms every time.
Cycle reference signal is 65.52ms, and the data of collection are 8 bit data, it is therefore desirable to data within a cycle
Gathering 8 times, the detection signal owing to sending contains the pulse signal of a 0.8ms, it is necessary first to FPGA judges whether
This dynamic pulse signal determines different signals collecting strategies, if there is dynamic pulse, it is contemplated that prolonging of hardware device
Time and signal stabilization time, then in FPGA needs 0.8ms after reference signal trailing edge, continuous acquisition 4 times, exists afterwards
Gather 4 times every 8.19ms, at reference signal rising edge, 8 bit data are sent to CPU and make a decision.If there is no dynamic arteries and veins
Punching, it is contemplated that the time delay of hardware device and signal stabilization time, then in FPGA needs the 6ms after reference signal trailing edge
Continuous acquisition 4 times, is gathering 4 times every 8.19ms afterwards, at reference signal rising edge, 8 bit data is being sent to CPU and makes a decision.
Every time acquisition time be all consider hardware time delay after determine, now collected signal stablize that to there is not signal dry
Disturb, gather data accurately and reliably, beneficially the correct judgement of data.
Claims (5)
1. the detecting system preventing FPGA depositor adhesion, it is characterised in that: include data acquisition module, data register mould
Block, data detection module, described data acquisition module carries out multi collect to the detection signal after Filtering Processing and will adopt every time
Collect to data be stored in data register module, the data collected are judged by described data detection module, work as interpretation
The data gathered are when being improper data, it is judged that FPGA depositor sticks together mistake.
A kind of detecting system preventing FPGA depositor adhesion the most according to claim 1, it is characterised in that: described data
Registration module is the depositor of 8.
3. the detection method preventing FPGA depositor adhesion, it is characterised in that: first, FPGA is to the detection after Filtering Processing
Signal carries out multi collect and the data every time collected is stored to data register module；Then by straight for the data that collect
The judgement that processor carries out data is given in sending and receiving；Finally, when the data of interpretation collection are improper data, then FPGA is judged
Depositor sticks together mistake.
A kind of detection method preventing FPGA depositor adhesion the most according to claim 3, it is characterised in that: FPGA is to filter
Detection signal after ripple processes is acquired, and adopts altogether 8 times, carries out continuous 4 times when the dynamic pulse of low and high level change comes and adopts
Collection；And the 12.19ms after reference signal trailing edge carries out ensuing 4 times and gathers, gather is spaced apart 8.19ms every time.
A kind of detection method preventing FPGA depositor adhesion the most according to claim 4, it is characterised in that: when in reference
Before signal trailing edge between 6ms after 2ms and trailing edge, when all the dynamic pulse that height change does not occurs, then in reference
During 6ms after signal trailing edge, external input signal is carried out continuous 4 times and gathers, and after PHR trailing edge
12.19ms carries out ensuing 4 times being interrupted gathering, and gather is spaced apart 8.19ms every time.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610564573.6A CN106201759B (en) | 2016-07-14 | 2016-07-14 | Detection system and method for preventing FPGA register from adhesion |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610564573.6A CN106201759B (en) | 2016-07-14 | 2016-07-14 | Detection system and method for preventing FPGA register from adhesion |
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| CN106201759A true CN106201759A (en) | 2016-12-07 |
| CN106201759B CN106201759B (en) | 2023-08-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114114997A (en) * | 2021-11-05 | 2022-03-01 | 南京国电南自电网自动化有限公司 | Reliability design method and device for sending merging unit sampling value message |
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