CN108226761A - A kind of rail traffic vehicles speed acquires the method with replacing self-test in real time - Google Patents
A kind of rail traffic vehicles speed acquires the method with replacing self-test in real time Download PDFInfo
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- CN108226761A CN108226761A CN201711465248.5A CN201711465248A CN108226761A CN 108226761 A CN108226761 A CN 108226761A CN 201711465248 A CN201711465248 A CN 201711465248A CN 108226761 A CN108226761 A CN 108226761A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P3/00—Measuring linear or angular speed; Measuring differences of linear or angular speeds
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31708—Analysis of signal quality
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Electric Propulsion And Braking For Vehicles (AREA)
- Train Traffic Observation, Control, And Security (AREA)
Abstract
It acquires the method with replacing self-test in real time the present invention relates to a kind of rail traffic vehicles speed, includes the following steps：（1）External sensor pulse signal and test self-test signal are filtered；（2）Four tunnel sensor signals and four road self-test signals are separately sent in two channels of FPGA by state machine, two independent channels are made there are two groups of difference pulses to enter after a certain time by the switching of state；（3）To entering two tetra- tunnel pulses of channel Nei, progress independently calculates frequency values and direction value respectively in respective channel；（4）The frequency values and direction value that calculate are judged by CPU, whether judgement is identical with the frequency values and direction value of expected self-test signal, represents that FPGA internal circuits work normally if identical, otherwise FPGA internal circuits abnormal work.The present invention carries out self-test by self-test pulse to collected sensor pulse frequency values, can accurately calculate the frequency magnitude of multiple signals, reduces the burden of CPU.
Description
Technical field
The present invention relates to field of track traffic, and in particular to a kind of acquisition in real time of rail traffic vehicles speed is with replacing self-test
Method.
Background technology
Some self test modes and frequency collection carry out self-test and acquisition using some CPU, microcontroller or DSP mostly at present,
Since it was run by the instruction cycle, even if having multithreading nor parallel operation truly.When needing, acquisition simultaneously is more
Road signal, and when carrying out self-test to collected signal, real-time can seem insufficient, and can occupy vast resources.In track
Field of traffic in order to reduce the burden of CPU, using the powerful parallel processing capabilities of FPGA, can accurately calculate multiple signals
Frequency magnitude.And it can also be found in time when FPGA internal registers stick together, and the deposit of any one flow
Device, which goes wrong, all can detect that failure and timely failure to the safe side.Matched based on this present invention provides one kind based on FPGA and CPU
The frequency quantity signal acquisition of conjunction and self-test scheme.
Invention content
The method with replacing self-test is acquired in real time the purpose of the present invention is to provide a kind of rail traffic vehicles speed, same
When accurately measure multiplex pulse frequency under the premise of, by self-test pulse come to collected sensor pulse frequency values carry out from
Inspection, improves.
To achieve the above object, present invention employs following technical schemes：
A kind of rail traffic vehicles speed acquires the method with replacing self-test in real time, includes the following steps：
（1）External sensor pulse signal and test self-test signal are filtered；
（2）Four tunnel sensor signals and four road self-test signals are separately sent in two channels of FPGA by state machine, are led to
Crossing the switching of state makes two independent channels have two groups of difference pulses to enter after a certain time；
（3）To entering two tetra- tunnel pulses of channel Nei, progress independently calculates frequency values and direction respectively in respective channel
Value；
（4）The frequency values and direction value that calculate are judged by CPU, judge with the frequency values of expected self-test signal and
Whether direction value is identical, represents that FPGA internal circuits work normally if identical, otherwise FPGA internal circuits abnormal work.
Further, the step（1）In, external sensor pulse signal and test self-test signal are filtered
Counter starts counting up after rising edge by detecting signal, judges this signal height electricity again after certain numerical value is count down to
It is flat, normal signal is considered if still high, if low be considered interference signal.
Further, the cutoff frequency of the filter module can be adjusted by adjusting parameter.
As shown from the above technical solution, a kind of rail traffic vehicles speed of the present invention acquisition in real time is with replacing self-test
Method, by self-test pulse come to collected sensor pulse frequency values carry out self-test.It is said when mistake occurs for frequency values
Bright FPGA internal registers are adhered, and data are unavailable at this time, and when any location register breaks down inside FPGA all
It can find in time, using the powerful parallel processing capabilities of FPGA, can accurately calculate the frequency magnitude of multiple signals, reduce
The burden of CPU.Frequency quantity signal is filtered present invention employs FPGA, cutoff frequency is adjustable.Employ improved M/T
Rule calculates frequency quantity information, improves real-time.
Description of the drawings
Fig. 1 is the system diagram of the present invention；
Fig. 2 is the improvement M/T rule partial timing diagrams of the present invention；
Fig. 3 is impulsive switched and frequency values switching schematic diagram of the present invention；
Fig. 4 is the state transition diagram of impulsive switched of the present invention；
Fig. 5 is walking direction sequence diagram of the present invention；
Fig. 6 is the method for the present invention flow chart.
Specific embodiment
The present invention will be further described below in conjunction with the accompanying drawings：
A kind of rail traffic vehicles speed such as Fig. 1 the present embodiment acquires and system packet used by the method for replacing self-test in real time
It includes：Microprocessor（CPU）, filter module, state machine handover module, frequency computing module, walking direction module and data register
Module, the input terminal of filter module and the input terminal of state machine connect, and the output terminal of state machine and the input terminal of register connect,
The output terminal of register and the input terminal of CPU connect.FPGA to from the sensor pulse signal come in of outside and self-test signal into
Row filters, and counter starts counting up after the rising edge by detecting signal, judges this signal again after certain numerical value is count down to
Low and high level is considered normal signal, if low be considered interference signal if still high.
FPGA carries out software filtering to the sensor pulse signal and self-test signal come in from outside.By detecting signal
Counter starts counting up after rising edge, judges this signal low and high level again after certain numerical value is count down to, and recognizes if still high
To be normal signal, if low, it is considered interference signal.In addition, count parameter is configurable；Filtered sensor
Signal and self-test signal enter impulsive switched state machine, make it into two different channels, carry out independent frequency respectively
Rate calculates and walking direction；Frequency computing module and walking direction module mainly believe collected sensor signal and self-test
Number carry out frequency quantity calculate and direction judgement；Data register module is mainly that the switching of two channels of FPGA is advanced into according to it
Signal, which carries out once switching again, makes each register preserve corresponding sensor signal and self-test signal.Avoid same post
What storage preserved for a moment be sensor signal preserve for a moment be self-test signal the problem of.CPU in this way will be protected according to interface sequence
The data for depositing deposit are directly read out.In addition FPGA has used independent time window house dog, and FPGA needs to see to outside
Door dog carries out feeding dog, so as to achieve the purpose that monitor FPGA work clocks.
As shown in Fig. 2, T1, T2, ch1 are synchronized under the work clock of FPGA, and T2 is the time of state switching, and T1 is
A condition of frequency quantity is calculated according to the preservation that the ATP cycles of operation set.The improved place of M/T rules is combined with pose
Signal and T1 signals are needed not wait for just to preserve at the end of T2 thresholdings in conventional method and be tied to preserve the frequency values being calculated
Fruit shortens calculating cycle, it is thus also avoided that the artificial boundary for judging height frequency.
As shown in figure 3, eight tunnels, two group pulse on right side enters two channels by switching state machine, result of calculation is using one
A alternative multiple selector is put into corresponding register, and the collected frequency values of FPGA and direction value are read for CPU.It avoids
The numerical value for preserving frequency values and the register of direction value switches with the switching of self-test signal and sensor signal, is convenient for
CPU section divides self-test frequency value register and real sensor frequency value register.
As shown in Figure 1, left side CPU is communicated with FPGA by parallel bus.CPU is to the frequency of self-test pulse that reads
Rate is judged, if equal with expected frequence value, then it is assumed that this channel FPGA circuitry does not break down.Think to cut next time
The result of calculation for the sensor pulse that swap-in comes then thinks to be available.It is if unequal with expected frequence value, then it is assumed that FPGA
Circuit malfunctions, it is believed that the sensor pulse calculated value being switched in next time is unavailable, so as to failure to the safe side side.
If Fig. 4 is switching state machine state transition diagram, as shown in figure 4, during according to the switching of self-test cycle set state machine
Between.Two independent signal processing modules that FPGA is switched to sensor signal and CPU self-test signal timesharing are handled, and are protected
It has demonstrate,proved all register values that FPGA is used all changing, has been not in the indeclinable feelings of value long-time of some register
Condition can be found in time after FPGA internal register failures.
If Fig. 5 is the sequence diagram of walking direction, as shown in figure 5, after two group pulses by switching enter different channels
It is identified immediately, judges the low and high level of ch2 when the rising edge of ch1 arrives.When ch1 is height, and ch2 is low, it is believed that dir is
It is low, and an eight bit is encoded into,.When ch1 is height, and ch2 is high, it is believed that dir is height, and is encoded into
Another eight bit.Think that direction changes at this time, direction signal is encoded into a string of binary codings, mainly
It is to malfunction in order to prevent.If self-test signal direction and desired value are inconsistent in the upper switching cycle that CPU is detected at this time,
The walking direction for then thinking this is incredible.
As shown in fig. 6, a kind of rail traffic vehicles speed of this implementation acquires method with replacing self-test in real time, including with
Lower step：
S1：External sensor pulse signal and test self-test signal are filtered, avoid external disturbance to frequency gauge
It calculates and walking direction interferes, and its cutoff frequency can be adjusted by parameter；
S2：Four tunnel sensor signals and four road self-test signal timesharing are sent to two channels of FPGA by a state machine
It is interior, two independent channels is made to have two groups of difference pulse signals after the regular hour by the switching of state and entered, so as to
Two independent channels is made to calculate the frequency and direction value of sensor and self-test signal simultaneously, are not interfere with each other；
S3：To entering two tetra- tunnel pulses of channel Nei, progress independently calculates frequency values and direction respectively in respective channel
Value：
Frequency values calculate the frequency that eight road pulse signals are calculated with improved M/T rules.On the one hand it is the signal of sensor is same
The work clock of FPGA is walked, two counters start counting up under this synchronizing signal, avoid counting error；On the other hand it is
Conventional method just preserves result of calculation at the end of threshold time T2, during herein in conjunction with rising edge of a pulse signal pose and T1 thresholding
Between preserve result of calculation；In addition before next rising edge is come register preserve be last rising edge value；This side
Method, which also avoids, is manually set low and high level frequency limit problem.Wherein T1 is generated under the premise of the execution cycle for meeting ATP
One threshold time can guarantee that enough basis pulses go to calculate frequency in high frequency.
S4：CPU reads the frequency of self-test signal and direction in two channels, judges whether it is equal with desired value, so as to
Conclude whether two autonomous channels of signal processing in FPGA break down.If self-test pulse frequency value is different from desired value,
Then think the signal processing channel failure inside FPGA.As long as any register that signal processing is participated in inside FPGA occurs viscous
Even failure can find simultaneously failure to the safe side immediately.
Embodiment described above is only that the preferred embodiment of the present invention is described, not to the model of the present invention
It encloses and is defined, under the premise of design spirit of the present invention is not departed from, those of ordinary skill in the art are to the technical side of the present invention
The various modifications and improvement that case is made should all be fallen into the protection domain that claims of the present invention determines.
Claims (3)
1. a kind of rail traffic vehicles speed acquires the method with replacing self-test in real time, which is characterized in that includes the following steps：
（1）External sensor pulse signal and test self-test signal are filtered；
（2）Four tunnel sensor signals and four road self-test signals are separately sent in two channels of FPGA by state machine, are led to
Crossing the switching of state makes two independent channels have two groups of difference pulses to enter after a certain time；
（3）To entering two tetra- tunnel pulses of channel Nei, progress independently calculates frequency values and direction respectively in respective channel
Value；
（4）The frequency values and direction value that calculate are judged by CPU, judge with the frequency values of expected self-test signal and
Whether direction value is identical, represents that FPGA internal circuits work normally if identical, otherwise FPGA internal circuits abnormal work.
2. rail traffic vehicles speed according to claim 1 acquires the method with replacing self-test in real time, it is characterised in that：
The step（1）In, external sensor pulse signal and test self-test signal are filtered by detecting the upper of signal
It rises and is started counting up along rear counter, judge this signal low and high level again after certain numerical value is count down to, think if still high
It is normal signal, if low, is considered interference signal.
3. rail traffic vehicles speed according to claim 1 acquires the method with replacing self-test in real time, it is characterised in that：
The cutoff frequency of the filter module is adjusted by adjusting parameter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711465248.5A CN108226761B (en) | 2017-12-28 | 2017-12-28 | Method for real-time acquisition and alternate self-inspection of speed of rail transit vehicle |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711465248.5A CN108226761B (en) | 2017-12-28 | 2017-12-28 | Method for real-time acquisition and alternate self-inspection of speed of rail transit vehicle |
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| CN108226761A true CN108226761A (en) | 2018-06-29 |
| CN108226761B CN108226761B (en) | 2020-06-02 |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109085370A (en) * | 2018-08-31 | 2018-12-25 | 高新兴创联科技有限公司 | Locomotive speed acquisition device and control method |
| CN109278674A (en) * | 2018-08-31 | 2019-01-29 | 百度在线网络技术（北京）有限公司 | Pilotless automobile system safety detection method, device, equipment and storage medium |
| CN110429934A (en) * | 2019-08-02 | 2019-11-08 | 西安星舟天启智能装备有限责任公司 | A kind of jamproof adaptometer counting method |
| CN111137701A (en) * | 2019-12-30 | 2020-05-12 | 合肥工大高科信息科技股份有限公司 | Non-stop ore drawing system and method |
| CN111220814A (en) * | 2019-11-12 | 2020-06-02 | 西安航空制动科技有限公司 | Airplane wheel speed acquisition system and fault detection method |
| CN112272023A (en) * | 2020-10-23 | 2021-01-26 | 成都航天通信设备有限责任公司 | FPGA-based signal processing channel selection method |
| CN112433064A (en) * | 2020-11-06 | 2021-03-02 | 杭州和利时自动化有限公司 | Rotating speed detection method, device and equipment |
| CN115629298A (en) * | 2022-12-19 | 2023-01-20 | 杭州加速科技有限公司 | Method and device for capturing abnormal synchronous trigger signal in ATE (automatic test equipment) |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109085370A (en) * | 2018-08-31 | 2018-12-25 | 高新兴创联科技有限公司 | Locomotive speed acquisition device and control method |
| CN109278674A (en) * | 2018-08-31 | 2019-01-29 | 百度在线网络技术（北京）有限公司 | Pilotless automobile system safety detection method, device, equipment and storage medium |
| CN109278674B (en) * | 2018-08-31 | 2020-10-09 | 百度在线网络技术（北京）有限公司 | Unmanned vehicle system safety detection method, device, equipment and storage medium |
| CN110429934A (en) * | 2019-08-02 | 2019-11-08 | 西安星舟天启智能装备有限责任公司 | A kind of jamproof adaptometer counting method |
| CN110429934B (en) * | 2019-08-02 | 2023-01-31 | 西安星舟天启智能装备有限责任公司 | Anti-interference self-adaptive counting method |
| CN111220814A (en) * | 2019-11-12 | 2020-06-02 | 西安航空制动科技有限公司 | Airplane wheel speed acquisition system and fault detection method |
| CN111137701A (en) * | 2019-12-30 | 2020-05-12 | 合肥工大高科信息科技股份有限公司 | Non-stop ore drawing system and method |
| CN112272023A (en) * | 2020-10-23 | 2021-01-26 | 成都航天通信设备有限责任公司 | FPGA-based signal processing channel selection method |
| CN112272023B (en) * | 2020-10-23 | 2023-06-20 | 成都航天通信设备有限责任公司 | Signal processing channel selection method based on FPGA |
| CN112433064A (en) * | 2020-11-06 | 2021-03-02 | 杭州和利时自动化有限公司 | Rotating speed detection method, device and equipment |
| CN115629298A (en) * | 2022-12-19 | 2023-01-20 | 杭州加速科技有限公司 | Method and device for capturing abnormal synchronous trigger signal in ATE (automatic test equipment) |
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