CN105068969A - Single event effect protection system and method for digital signal processing platform architecture - Google Patents
Single event effect protection system and method for digital signal processing platform architecture Download PDFInfo
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Abstract
The invention discloses a single event effect protection system and method for a digital signal processing platform architecture, and aims to solve the SEFI (Single Event Upset Function Interruption) problem of a digital signal processing platform in a space environment. According to the single event effect protection system and method, various measures are organically fused, a platform architecture supporting a multi-level single event soft error protection, detection and recovery technology is refined and perfected, and an SEFI fault detection and recovery method for a DSP (digital signal processor) and an FPGA (field programmable gate array) of the system is proposed, so that the SEFI effect of the digital signal processing platform can be effectively reduced. The single event effect protection system and method can effectively solve the SEFI problem of the system subjected to long-time on-orbit operation.
Description
Technical field
The present invention relates to a kind of system-level single particle effect guard system for digital signal processing platform framework and method, belong to space communications technique field.
Background technology
At present, in spaceborne digital signal processing platform, owing to mainly adopting extensive SRAM type FPGA and DSP to complete digital signal processing function, the probability of this series products generation single particle effect improves greatly.
Recognize from open publication, for current digital information processing system, alleviate the single particle effect of system mainly through methods such as redundancy, refreshing, error correction and detections, system still can normally be worked when there is SEU.But when SEFI occurs system, these measures above also can not solve, and must take SEFI recovery measure targetedly, and System recover could be allowed normal.
Summary of the invention
The object of the invention is: overcome the deficiencies in the prior art, a kind of single particle effect guard system for digital signal processing platform framework and method are provided, can the SEFI problem of resolution system, improve the space reliability of digital information processing system.
The technical solution used in the present invention is:
For the single particle effect guard system of digital signal processing platform framework, comprise: fpga chip, dsp chip, SEFI detect recovery unit, first memory and second memory, SEFI detects recovery unit and comprises FPGA state-detection and recovery module, DSP state-detection and recovery module, reads back check and refresh module, configuration module, house dog, DSP Loading Control module and memory control module;
Working state signal is sent to FPGA state-detection and recovers module by fpga chip, FPGA state-detection and recovery module detect the duty of fpga chip, if fpga chip is working properly, then proceed duty to detect, if fpga chip generation single event function interrupt SEFI, then FPGA state-detection and recovery module send reset signal to fpga chip, make its reset reshuffle;
Configuration module is by memory control module controls first memory, the configurator of fpga chip is loaded into the configuration store district of fpga chip from first memory, to read back check and the value of status register and control register reads out from the configuration store district of fpga chip by refresh module, compare with the original value of status register and control register, if identical, then proceed retaking of a year or grade to detect, if different, then to error indication signal to FPGA state-detection and recover module, by read back check and refresh module to fpga chip be configured memory block refresh, if state is still abnormal, then by FPGA state-detection and recovery module, fpga chip reset is reshuffled,
Working state signal is sent to DSP state-detection and recovers module by dsp chip, DSP state-detection and recovery module detect the duty of dsp chip, if dsp chip is working properly, then judge that check point information is the need of storage, if belong to the check point that will protect, then check point information is stored into second memory by store control logic, and proceed duty detection, check point is stored if do not need, still proceed duty to detect, if there is SEFI in dsp chip, then DSP state-detection and recovery module send reset signal to dsp chip, make it reset, described check point refers to the location point for recovering in the DSP program of DSP working site,
The configurator of dsp chip, by memory control module controls second memory, is loaded into the configuration store district of dsp chip by DSP Loading Control module from second memory;
Watchdog module timing receipt is from the duty indicator signal of dsp chip, if do not receive indicator signal for a long time, watchdog module resets to dsp chip.
For the single particle effect means of defence of digital signal processing platform framework, step is as follows:
(1) configuration module is by memory control module controls first memory, the configurator of fpga chip is loaded into the configuration store district of fpga chip from first memory; The configurator of dsp chip, by memory control module controls second memory, is loaded into the configuration store district of dsp chip by DSP Loading Control module from second memory;
(2) working state signal is sent to FPGA state-detection and recovers module by fpga chip, FPGA state-detection and recovery module detect the duty of fpga chip, if fpga chip is working properly, then proceed duty to detect, if fpga chip operation irregularity, then represent and there occurs single event function interrupt SEFI, then FPGA state-detection and recovery module send reset signal to fpga chip, make its reset reshuffle;
To read back check and the value of status register and control register reads out from the configuration store district of fpga chip by refresh module, compare with the value original value of status register and control register, if identical, then proceed retaking of a year or grade to detect, if different, then to error indication signal to FPGA state-detection and recover module, by read back check and refresh module to fpga chip be configured memory block refresh, if state is still abnormal, then by FPGA state-detection and recovery module, fpga chip reset is reshuffled;
(3) working state signal is sent to DSP state-detection and recovers module by dsp chip, DSP state-detection and recovery module detect the duty of dsp chip, if dsp chip is working properly, then judge that check point information is the need of storage, if belong to the check point that will protect, then check point information is stored into second memory by store control logic, and proceed duty detection, check point is stored if do not need, still proceed duty to detect, if dsp chip operation irregularity, then represent and there occurs single event function interrupt SEFI, then DSP state-detection and recovery module send reset signal to dsp chip, make it reset, described check point refers to the location point for recovering in the DSP program of DSP working site,
Watchdog module timing receipt is from the duty indicator signal of dsp chip, if do not receive indicator signal for a long time, watchdog module resets to dsp chip, completes the protection of described single particle effect.
The working state signal of described fpga chip comprises DONE signal, BUSY signal, FAR frame address register value, status register value and control register value.
Described step (2) is specially:
(4.1) monitor DONE signal: detect whether DONE signal is high level, if DONE signal is high level, then perform step (4.2); Otherwise, think that the electrify restoration circuit of fpga chip there occurs single event function interrupt, perform step (4.5);
(4.2) monitor BUSY signal: detect whether BUSY signal is high level, if BUSY signal is high level, perform step (4.3); Otherwise, think that fpga chip there occurs the single event function interrupt of SELECTMAP interface, perform step (4.5);
(4.3) FAR frame address register read-write: refreshing or before read back operation at every turn, FAR frame address register is first write the configuration store district of fpga chip, judge that whether the value that retaking of a year or grade goes out is correct, if correctly, then proceed step (4.4); Otherwise, think that fpga chip there occurs the single event function interrupt of SELECTMAP interface, perform step (4.5);
(4.4) status register value and control register value read-write: by the value of retaking of a year or grade status register and control register, if not identical with default value, think that fpga chip there occurs GlobalsignalsSEFI (single event function interrupt of overall signal) or PORSEFI (single event function interrupt of electrify restoration circuit), perform step (4.5);
(4.5) to be reshuffled by reset or power-off is reshuffled and carried out SEFI fault recovery.
Described step (3) is specially:
(5.1) start house dog, in DSP course of normal operation, produce feeding-dog signal, and monitor the working state signal that dsp chip sends, if working state signal is the right value of expection, then carry out step (5.2); Otherwise, think that dsp chip there occurs single event function interrupt, perform step (5.3);
(5.2) judge whether check point preservation condition meets, if belong to the check point that will protect, then by memory control module, the content of check point is saved to second memory, after having stored, return step (5.1); Otherwise, directly return step (5.1); The described check point that will protect refers to: need in the DSP program of being specified by user do the position of preservation action or automatically done the position of preservation action by appointment fixed interval;
(5.3) start the DSP reseting logic in DSP state-detection and recovery module, and perform check point recovery; The content that described check point recovers comprises: (1) DSP program performs scene: comprise control register and general-purpose register; (2) program execution stack; (3) the calculating data acquisition of program.
Described execution check point recovers to be specially:
The recovery of check point, by hardware trigger, is namely detected the DSP state-detection in recovery unit by SEFI and recovers module triggered interrupts, according to look-at-me reset DSP, after DSP restarts, automatically guiding, then performing check point in the mode of abnormality processing and recover; In check point rejuvenation, from second memory, read the information of a check point in DSP program, information is loaded in register and storehouse, then jumps into the program address of specifying, re-execute interrupted program.
The present invention's beneficial effect is compared with prior art:
(1) the present invention is in order to meet the requirement of digital information processing system space environment adaptive faculty, adopt the single event function interrupt of method detection system detecting DONE signal, BUSY signal and FAR value and status register value and control register value, solve FPGA that the SEFI due to SELECTMAP interface, POR electrify restoration circuit causes and power on and configure and the problem of refresh disable.
(2) the present invention realizes the recovery of systemic-function by the mode of write-back configuration file and check point storage file or system reset, greatly reduce the probability that single event function interrupt occurs when digital information processing system runs under space radiation environment, the anti-single particle ability of elevator system.
Accompanying drawing explanation
Fig. 1 is the theory diagram of guard system of the present invention;
Fig. 2 is means of defence process flow diagram of the present invention;
To be the present invention detect for the SEFI of system FPGA and recover process flow diagram Fig. 3;
To be the present invention detect for the SEFI of system DSP and recover process flow diagram Fig. 4.
Embodiment
The invention provides a kind of system-level single particle effect guard system and the means of defence that are adapted to digital signal processing platform, adopt SEFI detection recovery unit to carry out the state-detection of system, if judge there is SEFI in FPGA and DSP, takes recovery measure.SEFI for FPGA detects and recovers, detect recovery unit by SEFI to be configured FPGA, detect the DONE signal of FPGA, BUSY signal, FAR value, status register value and control register value after completing configuration, if generation SEFI, take to power on and to reshuffle or repositioning method carries out System recover.SEFI for DSP detects and recovers, and detects recovery unit carry out check point preservation to DSP by SEFI, detects DSP whether SEFI occurs by house dog, detect and SEFI does not occur, preserving check point simultaneously, when there is SEFI, the object of restoring system can be reached by recovering check point.
As shown in Figure 1, single particle effect guard system for digital signal processing platform framework provided by the invention, comprise: fpga chip, dsp chip, SEFI detect recovery unit, first memory and second memory, SEFI detects recovery unit and comprises FPGA state-detection and recovery module, DSP state-detection and recovery module, reads back check and refresh module, configuration module, house dog, DSP Loading Control module and memory control module;
Working state signal is sent to FPGA state-detection and recovers module by fpga chip, FPGA state-detection and recovery module detect the duty of fpga chip, if fpga chip is working properly, then proceed duty to detect, if fpga chip operation irregularity, then FPGA state-detection and recovery module send reset signal to fpga chip, make its reset reshuffle;
Configuration module is by memory control module controls first memory, the configurator of fpga chip is loaded into the configuration store district of fpga chip from first memory, to read back check and the value of status register and control register reads out from the configuration store district of fpga chip by refresh module, compare with the value original value of status register and control register, if identical, then proceed retaking of a year or grade to detect, if different, then to error indication signal to FPGA state-detection and recover module, by read back check and refresh module to fpga chip be configured memory block refresh, if state is still abnormal, then by FPGA state-detection and recovery module, fpga chip reset is reshuffled,
Working state signal is sent to DSP state-detection and recovers module by dsp chip, DSP state-detection and recovery module detect the duty of dsp chip, if dsp chip is working properly, then judge that check point information is the need of storage, if belong to the check point that will protect, then check point information is stored into second memory by store control logic, and proceed duty detection, check point is stored if do not need, still proceed duty to detect, if dsp chip operation irregularity, then DSP state-detection and recovery module send reset signal to dsp chip, make it reset, described check point refers to the location point for recovering in the DSP program of DSP working site,
The configurator of dsp chip, by memory control module controls second memory, is loaded into the configuration store district of dsp chip by DSP Loading Control module from second memory;
Watchdog module timing receipt is from the duty indicator signal of dsp chip, if do not receive indicator signal for a long time, watchdog module resets to dsp chip.
As shown in Figure 2, the present invention is based on above-mentioned single-particle guard system, also achieve a kind of single particle effect means of defence for digital signal processing platform framework, step is as follows:
(1) configuration module is by memory control module controls first memory, the configurator of fpga chip is loaded into the configuration store district of fpga chip from first memory; The configurator of dsp chip, by memory control module controls second memory, is loaded into the configuration store district of dsp chip by DSP Loading Control module from second memory;
(2) by working state signal, (working state signal of fpga chip comprises DONE signal to fpga chip, BUSY signal, FAR frame address register value, status register value and control register value) be sent to FPGA state-detection and recover module, FPGA state-detection and recovery module detect the duty of fpga chip, if fpga chip is working properly, then proceed duty to detect, if fpga chip operation irregularity, then represent and there occurs single event function interrupt SEFI, then FPGA state-detection and recovery module send reset signal to fpga chip, make it reset,
To read back check and the value of status register and control register reads out from the configuration store district of fpga chip by refresh module, compare with the value original value of status register and control register, if identical, then proceed retaking of a year or grade to detect, if different, then to error indication signal to FPGA state-detection and recover module, by read back check and refresh module to fpga chip be configured memory block refresh, if state is still abnormal, then by FPGA state-detection and recovery module, fpga chip is resetted;
As shown in Figure 3, be specially:
(2.1) monitor DONE signal: detect whether DONE signal is high level, if DONE signal is high level, then perform step (2.2); Otherwise, think that the electrify restoration circuit (POR) of fpga chip there occurs single event function interrupt, perform step (2.5); When fpga chip is in normal condition, after the configuration that powers on completes, DONE signal should be high level always, whenever be low situation if there is DONE, fpga chip then needs to reconfigure, if DONE signal is always low, then think that fpga chip there occurs electrify restoration circuit (POR) single event function interrupt; Por circuit is that fpga chip is inner for monitoring fpga chip core voltage VCCINT, the I/O voltage of BANK4 and the circuit of boosting voltage VCCAUX.When voltage drop, por circuit can reset fpga chip, removes configuration store district, the original state after electric current returns to and powers on, DONE signal step-down.The similar FPGA power down of phenomenon of POR-SEFI, or PROG signal is dragged down.
(2.2) monitor BUSY signal: detect whether BUSY signal is high level, if BUSY signal is high level, perform step (2.3); Otherwise, think that fpga chip there occurs the single event function interrupt of SELECTMAP interface, perform step (2.5); When fpga chip is in normal condition, when writing configuration store district, BUSY signal should be low level; When read back operation starts, BUSY signal is high level, and BUSY signal step-down level means that the back read data on data bus is effective; If after being switched to reading mode from WriteMode, BUSY signal is high level more than 32 CCLK cycles always, means the single event function interrupt SEFI that there occurs SELECTMAP interface;
(2.3) FAR frame address register read-write: refreshing or before read back operation at every turn, FAR frame address register is first write the configuration store district of fpga chip, judge that whether the value that retaking of a year or grade goes out is correct, if correctly, then proceed step (2.4); Otherwise, think that fpga chip there occurs the single event function interrupt of SELECTMAP interface, perform step (2.5); FAR is the frame address register of fpga chip inside, and FARSEFI may cause frame address register to read and write, also likely trigger frame address register Auto-counting, thus causes large area configuration data mistake;
(2.4) status register value and control register value read-write: by the value of retaking of a year or grade status register and control register, if not identical with default value, think that fpga chip there occurs GlobalsignalsSEFI, PORSEFI, perform step (2.5); When fpga chip is in normal condition, after the configuration that powers on completes, the value of status register should be X " 00007EFC ", the value of control register should be X " and 20000109 ", the value of retaking of a year or grade status register and control register can be passed through, judge whether fpga chip there occurs SEFI;
(2.5) reshuffled by reset or power-off reloading carry out SEFI fault recovery.Different SEFI is not identical on the impact of FPGA.The SEFI of por circuit and GlobalSignals can make FPGA function interrupt, and must reshuffle immediately.The SEFI of SELECTMAP interface and FAR frame address register does not affect user function, but the detection can lost SEU and recovery capability, cause SEU error accumulation, thus cause systemic-function to be interrupted, therefore, when task allows, should reshuffle as early as possible;
(3) working state signal is sent to DSP state-detection and recovers module by dsp chip, DSP state-detection and recovery module detect the duty of dsp chip, if dsp chip is working properly, then judge that check point information is the need of storage, if belong to the check point that will protect, then check point information is stored into second memory by store control logic, and proceed duty detection, check point is stored if do not need, still proceed duty to detect, if dsp chip operation irregularity, then represent and there occurs single event function interrupt SEFI, then DSP state-detection and recovery module send reset signal to dsp chip, make it reset, described check point refers to the location point for recovering in the DSP program of DSP working site,
Watchdog module timing receipt is from the duty indicator signal of dsp chip, if do not receive indicator signal for a long time, watchdog module resets to dsp chip, completes the protection of described single particle effect.
As shown in Figure 4, be specially:
(3.1) start house dog, in DSP course of normal operation, produce feeding-dog signal, and monitor the working state signal that dsp chip sends, if working state signal is the right value of expection, then carry out step (3.2); Otherwise, think that dsp chip there occurs single event function interrupt, perform step (3.3);
The working state signal that dsp chip sends comprises the significant variable of the interrupt response signal IACK of DSP, interruption code, specific function; Such as, during dsp chip employing external interrupt mechanism works, can by judging that IACK and interruption code identify that whether the duty of DSP is normal, according to external interrupt 4, interruption code should be normally " 0010 ", if not " 0010 ", then can conclude that dsp chip is abnormal and interrupt;
(3.2) judge whether check point preservation condition meets, if belong to the check point that will protect, then by memory control module, the content of check point is saved to second memory, after having stored, return step (3.1); Otherwise, directly return step (3.1); The described check point that will protect refers to: need in the DSP program of being specified by user do the position of preservation action or automatically done the position of preservation action by appointment fixed interval; Memory control module completes preservation to check point and retaking of a year or grade; Such as, the program pointer address location of DSP subroutine;
(3.3) start the DSP reseting logic in DSP state-detection and recovery module, and perform check point recovery; The content that described check point recovers comprises: (1) DSP program performs scene: comprise control register and general-purpose register; (2) program execution stack; (3) the calculating data acquisition of program.Dsp chip register is divided into general-purpose register and control register two kinds.General-purpose register is divided into two groups of registers, for storing data and data address pointer.Dsp chip has 10 control registers, is respectively addressing mode register, state of a control register, interrupt flag register, interruption arrange register, interrupt clear register, OIER, break in service list index, interrupt return pointer, non-maskable interrupts return pointer and programmable counter.Program execution stack is function inset call, interrupts, and stores the place of related register when task switch keeps the scene intact.The calculating data acquisition of program refers to the key variables at the program scene that will recover.Such as, the single event function interrupt of interrupt control register, causes the generation of accidental interruption, upsets normal procedure process, when check point is preserved, will store interrupt control register variate-value, and when performing check point recovery, the response that DSP can be correct is interrupted; Such as, if DSP completes the computing function that an order performs, the significant variable in computation process can be preserved, if dsp chip generation single event function interrupt, can recover from the check point of the last time, guarantee that recovery routine is on-the-spot as early as possible;
Perform check point to recover to be specially: the recovery of check point is by hardware trigger, namely detected the DSP state-detection in recovery unit by SEFI and recover module triggered interrupts, according to look-at-me reset DSP, after DSP restarts, automatic guiding, then performs check point in the mode of abnormality processing and recovers; In check point rejuvenation, from second memory, read the information of a check point in DSP program, information is loaded in register and storehouse, then jumps into the program address of specifying, re-execute interrupted program.
In sum, the single particle effect guard system that the present invention presents and method, effectively slow down the SEFI problem of the digital information processing system be made up of FPGA and DSP, improves the space environment adaptive faculty of digital information processing system.The digital signal processing series products of China's military communication, navigation, remote sensing satellite can be widely used in, promote China New Generation Military satellite technology to high-performance, highly reliable, miniaturization, long-life future development.
The unspecified part of the present invention belongs to technology as well known to those skilled in the art.
Claims (6)
1. for the single particle effect guard system of digital signal processing platform framework, it is characterized in that comprising: fpga chip, dsp chip, SEFI detect recovery unit, first memory and second memory, SEFI detects recovery unit and comprises FPGA state-detection and recovery module, DSP state-detection and recovery module, reads back check and refresh module, configuration module, house dog, DSP Loading Control module and memory control module;
Working state signal is sent to FPGA state-detection and recovers module by fpga chip, FPGA state-detection and recovery module detect the duty of fpga chip, if fpga chip is working properly, then proceed duty to detect, if fpga chip generation single event function interrupt SEFI, then FPGA state-detection and recovery module send reset signal to fpga chip, make its reset reshuffle;
Configuration module is by memory control module controls first memory, the configurator of fpga chip is loaded into the configuration store district of fpga chip from first memory, to read back check and the value of status register and control register reads out from the configuration store district of fpga chip by refresh module, compare with the original value of status register and control register, if identical, then proceed retaking of a year or grade to detect, if different, then to error indication signal to FPGA state-detection and recover module, by read back check and refresh module to fpga chip be configured memory block refresh, if state is still abnormal, then by FPGA state-detection and recovery module, fpga chip reset is reshuffled,
Working state signal is sent to DSP state-detection and recovers module by dsp chip, DSP state-detection and recovery module detect the duty of dsp chip, if dsp chip is working properly, then judge that check point information is the need of storage, if belong to the check point that will protect, then check point information is stored into second memory by store control logic, and proceed duty detection, check point is stored if do not need, still proceed duty to detect, if there is SEFI in dsp chip, then DSP state-detection and recovery module send reset signal to dsp chip, make it reset, described check point refers to the location point for recovering in the DSP program of DSP working site,
The configurator of dsp chip, by memory control module controls second memory, is loaded into the configuration store district of dsp chip by DSP Loading Control module from second memory;
Watchdog module timing receipt is from the duty indicator signal of dsp chip, if do not receive indicator signal for a long time, watchdog module resets to dsp chip.
2., for the single particle effect means of defence of digital signal processing platform framework, it is characterized in that step is as follows:
(1) configuration module is by memory control module controls first memory, the configurator of fpga chip is loaded into the configuration store district of fpga chip from first memory; The configurator of dsp chip, by memory control module controls second memory, is loaded into the configuration store district of dsp chip by DSP Loading Control module from second memory;
(2) working state signal is sent to FPGA state-detection and recovers module by fpga chip, FPGA state-detection and recovery module detect the duty of fpga chip, if fpga chip is working properly, then proceed duty to detect, if fpga chip operation irregularity, then represent and there occurs single event function interrupt SEFI, then FPGA state-detection and recovery module send reset signal to fpga chip, make its reset reshuffle;
To read back check and the value of status register and control register reads out from the configuration store district of fpga chip by refresh module, compare with the value original value of status register and control register, if identical, then proceed retaking of a year or grade to detect, if different, then to error indication signal to FPGA state-detection and recover module, by read back check and refresh module to fpga chip be configured memory block refresh, if state is still abnormal, then by FPGA state-detection and recovery module, fpga chip reset is reshuffled;
(3) working state signal is sent to DSP state-detection and recovers module by dsp chip, DSP state-detection and recovery module detect the duty of dsp chip, if dsp chip is working properly, then judge that check point information is the need of storage, if belong to the check point that will protect, then check point information is stored into second memory by store control logic, and proceed duty detection, check point is stored if do not need, still proceed duty to detect, if dsp chip operation irregularity, then represent and there occurs single event function interrupt SEFI, then DSP state-detection and recovery module send reset signal to dsp chip, make it reset, described check point refers to the location point for recovering in the DSP program of DSP working site,
Watchdog module timing receipt is from the duty indicator signal of dsp chip, if do not receive indicator signal for a long time, watchdog module resets to dsp chip, completes the protection of described single particle effect.
3. the single particle effect means of defence for digital signal processing platform framework according to claim 2, is characterized in that: the working state signal of described fpga chip comprises DONE signal, BUSY signal, FAR frame address register value, status register value and control register value.
4. the single particle effect means of defence for digital signal processing platform framework according to claim 2, is characterized in that: described step (2) is specially:
(4.1) monitor DONE signal: detect whether DONE signal is high level, if DONE signal is high level, then perform step (4.2); Otherwise, think that the electrify restoration circuit of fpga chip there occurs single event function interrupt, perform step (4.5);
(4.2) monitor BUSY signal: detect whether BUSY signal is high level, if BUSY signal is high level, perform step (4.3); Otherwise, think that fpga chip there occurs the single event function interrupt of SELECTMAP interface, perform step (4.5);
(4.3) FAR frame address register read-write: refreshing or before read back operation at every turn, FAR frame address register is first write the configuration store district of fpga chip, judge that whether the value that retaking of a year or grade goes out is correct, if correctly, then proceed step (4.4); Otherwise, think that fpga chip there occurs the single event function interrupt of SELECTMAP interface, perform step (4.5);
(4.4) status register value and control register value read-write: by the value of retaking of a year or grade status register and control register, if not identical with default value, think that fpga chip there occurs GlobalsignalsSEFI or PORSEFI, perform step (4.5);
(4.5) to be reshuffled by reset or power-off is reshuffled and carried out SEFI fault recovery.
5. the single particle effect means of defence for digital signal processing platform framework according to claim 2, is characterized in that: described step (3) is specially:
(5.1) start house dog, in DSP course of normal operation, produce feeding-dog signal, and monitor the working state signal that dsp chip sends, if working state signal is the right value of expection, then carry out step (5.2); Otherwise, think that dsp chip there occurs single event function interrupt, perform step (5.3);
(5.2) judge whether check point preservation condition meets, if belong to the check point that will protect, then by memory control module, the content of check point is saved to second memory, after having stored, return step (5.1); Otherwise, directly return step (5.1); The described check point that will protect refers to: need in the DSP program of being specified by user do the position of preservation action or automatically done the position of preservation action by appointment fixed interval;
(5.3) start the DSP reseting logic in DSP state-detection and recovery module, and perform check point recovery; The content that described check point recovers comprises: (1) DSP program performs scene: comprise control register and general-purpose register; (2) program execution stack; (3) the calculating data acquisition of program.
6. the single particle effect means of defence for digital signal processing platform framework according to claim 5, is characterized in that: described execution check point recovers to be specially:
The recovery of check point, by hardware trigger, is namely detected the DSP state-detection in recovery unit by SEFI and recovers module triggered interrupts, according to look-at-me reset DSP, after DSP restarts, automatically guiding, then performing check point in the mode of abnormality processing and recover; In check point rejuvenation, from second memory, read the information of a check point in DSP program, information is loaded in register and storehouse, then jumps into the program address of specifying, re-execute interrupted program.
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