CN114114997A - Reliability design method and device for sending merging unit sampling value message - Google Patents
Reliability design method and device for sending merging unit sampling value message Download PDFInfo
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Abstract
The invention discloses a design method for improving working reliability when a merging unit device uses a single CPU module to carry out data acquisition and IEC61850-9-2 message transmission in the field of relay protection, which can reliably carry out validity check on sampling value data when the device is subjected to external interference and faults of FPGA hardware, ensure that a protection device receiving the sampling value data at the rear end can correctly identify the faults of the merging unit device, lock protection is carried out in time, prevent misoperation of the protection device, reduce economic loss caused by misoperation and improve economic benefit.
Description
Technical Field
The invention relates to a reliability design method and device for sending a sampling value message of a merging unit, and belongs to the technical field of process layer devices of electric power digital substations.
Background
Currently, mainstream relay protection manufacturers generally use redundancy schemes of a master CPU module and a slave CPU module to improve reliability when designing a protection device. The merging unit, MU for short, is a device that merges and synchronizes the electrical quantities transmitted from the primary transformers and forwards the processed digital signals to the bay level devices according to a specific format for use. Due to the particularity of the merging unit device, only a single CPU module can be used in many occasions, and the reliability of the merging unit device is not high as the protection device.
However, the merging unit device is used as an important data centralized processing device in the digital substation, the reliability of the merging unit device directly affects the action of the subsequent protection device, and a great influence is caused by a plurality of accidents of misoperation of the protection device caused by data failure sent by the merging unit device at present.
How to further improve the reliability of the operation of the merging unit device has practical significance for the whole digital substation.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, provides a method and a device for designing the reliability of sending the sampling value message of the merging unit, and improves the working reliability of the merging unit device.
In order to achieve the purpose, the invention is realized by adopting the following technical scheme:
in a first aspect, the present invention provides a method for designing the reliability of a single CPU module of a merge unit apparatus, comprising the steps of:
the analog quantity is collected through the field programmable gate array FPGA and interpolation is carried out, and a message is formed and sent to the receiving end device.
Further, the method for collecting analog quantity and performing interpolation through the field programmable gate array FPGA comprises the following steps:
sampling data of the main sampling analog ADC device to obtain analog quantity, and storing the analog quantity in a data buffer area;
interpolating the analog quantity to generate a first sampling value group package;
carrying out interpolation on the analog quantity again to generate a second sampling value group package;
and carrying out data recombination on the first sampling value packet and the second sampling value packet to form a message and sending the message.
Further, the method for acquiring the analog quantity and performing interpolation by the field programmable gate array FPGA to form the message and send the message comprises the following steps:
sampling data of the main sampling analog ADC device to obtain analog quantity, and storing the analog quantity in a data buffer area;
interpolating the analog quantity to generate a first sampling value group package;
carrying out interpolation on the analog quantity again to generate a second sampling value group package;
and forming a message according to the first sampling value packet and the second sampling value packet, recombining the data and then transmitting the data.
Further, the method for sampling data of the main sampling analog ADC device to obtain the analog quantity and storing the analog quantity in the data buffer area comprises the following steps:
at the moment of generating sampling value pulses, performing 16-bit data sampling on the main sampling 24 paths of analog quantity, adding 8-bit Check FCS (Frame Check Sequence) to the 16-bit data, expanding the data into 24-bit analog quantity data, storing the data into a data buffer area, and adding 1 path of probe data with fixed data of 16' h5A5A to be fixedly stored in any data channel (such as the data channel 31); an IRIG-B (time code) time synchronization and time keeping high-precision circuit is designed in the FPGA, and can generate accurate 4000sps sampling pulses for acquisition and interpolation of analog quantity.
Furthermore, 8-bit data check FCS for mainly acquiring 24 channel data is arranged in the FPGA, a data probe with fixed data of 16' h5A5A is arranged to judge whether the internal calculation of the FPGA is correct, the 8-bit check FCS can identify whether the sampled value data is tampered when the sampled value data is carried in an RAM of the FPGA or processed in the FPGA, and the data probe can monitor whether single-bit or multi-bit data turnover and locking occur to hardware resources of an LUT and an REG register in the FPGA due to environmental factors, so that effective marks of the sampled value data can be timely and correctly marked.
Further, the method for generating the first sample value group package by interpolating the analog quantity comprises the following steps:
the interpolation algorithm needs to use 2 sampling points of (X0, Y0) and (X1, Y1) to implement, so at the moment of generating sampling value pulse, the adjacent 2 sampling points used for interpolation are found from the data buffer to carry out interpolation;
at the time of generating a sampling value pulse, firstly, interpolating fixed probe data of a first data channel (data channel 31), when reading 24-bit data from a data buffer, firstly, calculating a new FCS1 for the lower 16 bits of the obtained data, comparing the FCS1 with the upper 8-bit value FCS2 of the 24-bit data read by the buffer to determine whether the lower 16 bits of the interpolation result are probe data 16' h5A5A, and recording the working state of an interpolation circuit CirStatus =0 if the FCS1 is not equal to FCS2 or the probe data is in error;
then, linear interpolation is carried out on the channels 0-23 in sequence, all channels need to carry out FCS check on the lower 16 bits of 24-bit data when reading data from the receiving buffer, and if the FCS check of a certain channel is wrong, channel data is invalid for the channel data; if the working state of the interpolation circuit CirStatus is 0, the interpolation circuit in the FPGA is in error, and the channel data valid flags of all 24 channels are set to be in an invalid state;
and adding 8-bit data check FCS to the interpolated 24-path sampling value data and the interpolated result SyncData [ n ] of the probe data of the data channel 31, and storing the data in a first sampling value group packet buffer to form a first sampling value group packet.
Further, the method for generating the second sample value group package by interpolating the analog quantity again comprises the following steps:
and independently and repeatedly acquiring 24 channels, interpolating according to a method for generating the first sampling value group package by interpolating the analog quantity, and storing the interpolation into a second sampling value group package buffer area to form a second sampling value group package.
Furthermore, 2 independent IEC61850-9-2 sampling value messages are formed according to the configuration of the CPU and stored in an Ethernet transmission buffer area;
and during sending, recombining the 2 parts of grouped sampling value messages to form a recombined message, wherein the recombining strategy is to recombine the data of the first sampling value message and the CRC of the second sampling value message to form a recombined message, and sending the recombined message to a receiving end device.
Further, the method further comprises: after receiving end device receives message, it judges if the message validity, channel valid mark and interval between sampling value messages of the message meet 250us, if detecting relevant fault, locking protective device action, including following steps:
if the data of the received message is consistent with the CRC, the message is legal, if the data of the received message is inconsistent with the CRC and the message is illegal, the message is discarded, and the action of a protection device is locked;
if the data valid flag is in an invalid state, discarding the message, and locking the protection device to act;
if the interval between the messages exceeds 250us, the messages are discarded, and the protection device is locked.
In a second aspect, the present invention provides a device for designing reliability of sending a sampling value packet of a merging unit, where the device includes:
the field programmable gate array FPGA is used for collecting analog quantity and carrying out interpolation to form a message and sending the message to the protection device;
and the receiving end device is used for judging the message legality, the data valid mark and the interval between the sampling value messages of the message after receiving the message, and locking the protection device to act if a relevant fault is detected.
Furthermore, a time code timing and time keeping high-precision circuit is designed in the FPGA, and can generate accurate 4000sps sampling pulses for acquisition and interpolation of analog quantity;
the FPGA is internally provided with an 8-bit data verification FCS device for mainly acquiring 24 channel data, a data probe with fixed data of 16' h5A5A is arranged to judge whether the internal calculation of the FPGA is correct, the 8-bit verification FCS can identify whether the sampled value data is tampered when the sampled value data is carried in an RAM of the FPGA or processed in the FPGA, and the data probe can monitor whether single-bit or multi-bit data turnover and locking occur to hardware resources of an LUT and an REG register in the FPGA due to environmental factors, so that an effective mark for the sampled value data can be timely and correctly set.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention collects analog quantity and interpolates through FPGA, forms message and sends to the protection device; after the protection device receives the message, the message validity, the data valid flag and the interval between the sampling value messages of the message are judged, if the related fault is detected, the protection device is locked to act, so that the occurrence of a false action event can be prevented, and the reliability is improved;
2. the 8-bit data verification FCS in the FPGA can identify the phenomenon of single bit overturning or locking in blockRAM data in the FPGA, set channel data in time to be invalid, and lock the action of a protection device, so that a misoperation event can be prevented;
3. the probe data 16' h5A5A in the invention can identify the locking phenomenon of interpolation circuit logic and REG register in FPGA, and set channel data invalid in time to lock the action of the protection device and prevent the occurrence of false action event;
4. in the invention, 2 parts of packed sampling value data are adopted for sending the sampling value message for recombination, the strategy is to send the sampling value message by using the data of the sampling value package 1 and the CRC of the sampling value package 2, if the data of the 2 parts of sampling value packages are consistent, the message is legal at the moment, and if the data of the 2 parts of sampling value packages are inconsistent, the message is illegal and can be discarded by a protection device, the action of the protection device is locked, the occurrence of misoperation events is prevented, and the identification is more accurate.
Drawings
FIG. 1 is a block diagram of sample value processing according to the present invention;
FIG. 2 is a sample data save flow diagram of the present invention;
FIG. 3 is a flow chart of sample value interpolation according to the present invention;
FIG. 4 illustrates the present invention for reconstructing 2 samples.
Detailed Description
The invention is further described below with reference to the accompanying drawings. The following examples are only for illustrating the technical solutions of the present invention more clearly, and the protection scope of the present invention is not limited thereby.
The first embodiment is as follows:
the analog quantity processing mechanism of the invention is that 8-bit check FCS expansion is added to data of 24 channels which are mainly adopted and 24 channels which are repeatedly adopted to 24 bits, a data probe with fixed data of 16' h5A5A is added to judge whether the internal calculation of the FPGA is correct, the 8-bit check FCS can identify whether the sampled value data is carried in an RAM of the FPGA or is tampered during the internal processing of the FPGA, the data probe can monitor whether hardware resources such as an LUT (look-up table) and an REG (reference REG) register in the FPGA generate single-bit or multi-bit data inversion and locking due to environmental factors, and the data of the sampled value data can be effectively marked timely and correctly. An FPGA is a programmable logic device whose internal hardware logic can be configured by a designer. Since most FPGAs are volatile devices, they need to be reconfigured each time they are powered up, so they are called Field Programmable Gate arrays (Field Programmable Gate arrays).
The embodiment provides a reliability design method of a single CPU module of a merging unit device, which is characterized by comprising the following steps:
step 1, designing a high-precision circuit with IRIG-B time synchronization and timekeeping in an FPGA of a CPU module of a merging unit device, and generating accurate 4000sps sampling pulses for acquisition and interpolation of analog quantity;
Step 3, the FPGA starts linear interpolation at the moment of generating sampling value pulses, and finds 2 adjacent sampling points used for interpolation from the data buffer area for interpolation;
step 4, the FPGA firstly acquires data of a channel 31 to perform interpolation at the moment of generating sampling Value pulses, firstly performs 8-bit data and verification on the data when the data are read from a data buffer area, judges whether an interpolation result is probe data 16' h5A5A after the interpolation is finished, and records the working state CirStatus =0 of the interpolation circuit if the data are wrong, as shown in a Value31 shown in figure 3;
and 5: the FPGA carries out linear interpolation on the channels 0-23 in sequence, FCS (channel data correction) is needed to be carried out on the lower 16 bits of the 24-bit data when all the channels read data from the receiving buffer, and if the FCS is wrongly checked in the data check of a certain channel, channel data is invalid on the channel data SyncData [ n ] [29 ]; if the working state of the interpolation circuit CirStatus in the step 5 is 0, the interpolation circuit in the FPGA is wrong, and at the moment, the channel data of SyncData [ n ] [29] of all channels are invalid. n represents the channel number, 29 represents bit29 of the data;
step 6: the FPGA continues to add 8-bit data check FCS and channel data valid marks to the interpolated 24-path sampling value data and the interpolated result of the probe data of the data channel 31, and stores the data in a sampling value group packet buffer 1; here, the data channel is not limited to the data channel 31, and may be any one of the data channels;
and 7: independently processing the repeated acquisition 24 channels according to the steps from step 2 to step 6, storing the repeated acquisition data in a sampling value group packet buffer 2, and obtaining 2 completely independent sampling value group packet buffers 1 and 2;
and 8: the FPGA forms 2 independent IEC61850-9-2 sampling value messages according to the configuration of the CPU, and the sampling value messages are stored in an Ethernet transmission buffer area;
and step 9: the internal interpolation processing of the FPGA needs 38us, the package needs 42us, and the FPGA starts to send a sampling value message after the sampling value pulse generation time is delayed by 80 us;
step 10: the FPGA recombines 2 parts of packaged sampling value data when sending, the strategy is to use the data of the sampling value package 1 and the CRC of the sampling value package 2 to send a sampling value message, if the 2 parts of sampling value package data are consistent, the message is legal at the moment, if the 2 parts of sampling value package data are inconsistent, the message is illegal and can be discarded by a protection device, the strategy can detect errors caused by data faults in the FPGA device, and the reliability of a merging unit is effectively improved;
step 11: and the receiving end device judges the legality of the message sent by the merging unit, the data valid mark and the interval between sampling value messages according to the standard requirement of IEC61850-9-2, and locks the action of the protection device in time if a relevant fault is detected, so as to prevent the occurrence of a misoperation event.
After receiving end device receives message, it judges if the message validity, channel valid mark and interval between sampling value messages of the message meet 250us, if detecting relevant fault, locking protective device action, including following steps:
if the data of the received message is consistent with the CRC, the message is legal, if the data of the received message is inconsistent with the CRC and the message is illegal, the message is discarded, and the action of a protection device is locked; if the data valid flag is in an invalid state, discarding the message, and locking the protection device to act; if any channel data valid flag is in an invalid state, the message is discarded. If the interval between the messages exceeds 250us, the messages are discarded, and the protection device is locked.
The validity of the recombined message is judged by a receiving end device, the last 4 standard bytes of the Ethernet are CRC, and the check of the data and the CRC is finished by a network card of the receiving end.
The analog quantity processing mechanism of the invention is to add 8-bit data check FCS to the data of the main 24 channels and the repeated 24 channels, and add a data probe with fixed data of 16' h5A5A to judge whether the internal calculation of the FPGA is correct, the 8-bit data check FCS can identify whether the sampled value data is carried in the RAM of the FPGA or is tampered during the internal processing of the FPGA, the data probe can monitor whether the hardware resources such as LUT and REG register in the FPGA are subjected to single-bit or multi-bit data inversion and locking due to environmental factors, and can timely and correctly mark the channel data to the sampled value data.
The design method of the invention can correctly identify the following faults:
the 8-bit data verification FCS can identify the phenomenon of single bit overturning or locking in Block RAM data inside an FPGA and set channel data invalid in time;
the probe data 16' h5A5A in the invention can identify the locking phenomenon of interpolation circuit logic and REG register in FPGA, and set channel data invalid in time;
in the invention, 2 parts of packed sampling value data are adopted for sending the sampling value message for recombination, the strategy is to send the sampling value message by using the data of the sampling value package 1 and the CRC of the sampling value package 2, if the data of the 2 parts of sampling value packages are consistent, the message is legal, and if the data of the 2 parts of sampling value packages are inconsistent, the message is illegal, and the message can be discarded by a protection device. The CRC is also a cyclic redundancy check code.
The protection device in the digital substation legally judges the data valid flag sent by the merging unit and the interval between sampling value messages according to the standard requirement of IEC61850-9-2, and locks protection if the data is invalid or the message interval is wrong, so that a misoperation event is prevented.
Example two:
the present embodiment provides a device for designing reliability of sending a sampling value packet of a merging unit, where the device includes:
the field programmable gate array FPGA is used for collecting analog quantity and carrying out interpolation to form a message and sending the message to the protection device;
and the protection device is used for judging the message legality, the data valid flag and the interval between the sampling value messages of the message after receiving the message, and locking the protection device to act if a relevant fault is detected.
The analog quantity processing mechanism of the invention is that 8-bit data check FCS is added to data of 24 channels which are mainly adopted and 24 channels which are repeatedly adopted, a data probe with fixed data of 16' h5A5A is added to judge whether the internal calculation of the FPGA is correct, the 8-bit data check FCS can identify whether the sampled value data is carried in RAM of the FPGA or is tampered during the internal processing of the FPGA, the data probe can monitor whether hardware resources such as LUT (look up table) and REG (REG register) in the FPGA are subjected to single-bit or multi-bit data inversion and locking due to environmental factors, and the data valid mark of the sampled value data can be timely and correctly set.
The FPGA is internally provided with a device for adding 8-bit data verification FCS for the main sampling 24-channel data, a data probe with fixed data of 16' h5A5A is arranged to judge whether the internal calculation of the FPGA is correct, the 8-bit data verification FCS is used for identifying whether the sampling value data is tampered during the RAM transportation of the FPGA or the internal processing of the FPGA, and the data probe is used for monitoring whether the hardware resources of an LUT (look up table) and an REG (register) in the FPGA are subjected to single-bit or multi-bit data turnover and locking due to environmental factors, so that the effective mark of the sampling value data can be timely and correctly set.
The protection device in the digital substation legally judges the data valid flag sent by the merging unit and the interval between sampling value messages according to the standard requirement of IEC61850-9-2, and locks protection if the data is invalid or the message interval is wrong, so that a misoperation event is prevented.
The design method of the invention can correctly identify the following faults:
the 8-bit data and the check in the invention can identify the phenomenon of single bit turnover or locking in the Block RAM data in the FPGA, and set the data in time to be invalid;
the probe data 16' h5A5A in the invention can identify the locking phenomenon of interpolation circuit logic and REG register in FPGA, and set the data invalid in time;
the invention recombines 2 sampling value groups to realize data redundancy comparison mechanism.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (10)
1. A reliability design method for a single CPU module of a merging unit device is characterized by comprising the following steps:
the analog quantity is collected through the field programmable gate array FPGA and interpolation is carried out, and a message is formed and sent to the receiving end device.
2. The reliability design method according to claim 1, wherein the method for collecting analog quantity and interpolating by the Field Programmable Gate Array (FPGA) comprises the following steps:
sampling data of the main sampling analog ADC device to obtain analog quantity, and storing the analog quantity in a data buffer area;
interpolating the analog quantity to generate a first sampling value group package;
carrying out interpolation on the analog quantity again to generate a second sampling value group package;
and forming a message for the first sampling value packet and the second sampling value packet, carrying out data recombination and sending.
3. The reliability design method of claim 2, wherein the method for sampling data of the main sampling analog ADC device and storing the obtained analog quantity in the data buffer comprises the following steps:
and at the moment of generating sampling value pulses, the FPGA carries out 16-bit data sampling on the main sampling 24-path analog quantity, adds 8-bit data verification FCS to the 16-bit data, expands the data into 24-bit analog quantity data, then stores the data into a data buffer area, and adds 1-path probe data for fixing the data to be stored in any data channel.
4. The reliability design method according to claim 3, wherein the probe data is 16' h5A 5A.
5. The reliability design method according to claim 4, wherein the method for generating the first sample value group packet by interpolating the analog quantity comprises the following steps:
at the sampling value pulse generating moment, finding out 2 adjacent sampling points used for interpolation from the data buffer area for interpolation;
at the moment of generating sampling value pulses, firstly, interpolating fixed probe data of a data channel 31, when reading 24-bit data from a data buffer, firstly, calculating a new data check FCS1 for the lower 16 bits of the obtained data, comparing the new data check FCS1 with the upper 8 bits FCS2 of the obtained data to determine whether the lower 16 bits of the interpolation result are probe data or not after the interpolation is finished, and if the FCS1 is not equal to the FCS2 or the probe data is not equal to the probe data, recording the working state of an interpolation circuit, CirStatus = 0;
then, linear interpolation is carried out on the channels 0-23 in sequence, all channels need to carry out FCS check on the lower 16 bits of 24-bit data when reading data from the receiving buffer, and if the FCS check of a certain channel is wrong, the channel data valid flag of the channel data is set to be in an invalid state; if the working state of the interpolation circuit CirStatus is 0, the interpolation circuit in the FPGA is in error, and the channel data valid flags of all 24 channels are set to be in an invalid state;
and continuously adding 8-bit FCS to the interpolated 24-path sampling value data and the interpolated result of the probe data, and storing the FCS in a first sampling value group packet buffer area to form a first sampling value group packet.
6. The reliability design method according to claim 5, wherein the method of generating the second sample value group packet by interpolating the analog quantity again comprises the steps of:
and independently and repeatedly acquiring 24 channels, interpolating according to a method for generating the first sampling value group package by interpolating the analog quantity, and storing the interpolation into a second sampling value group package buffer area to form a second sampling value group package.
7. The reliability design method according to claim 2, wherein the method for forming the first sample value group packet and the second sample value group packet into a message, performing data reorganization, and sending comprises the following steps:
forming 2 independent IEC61850-9-2 sampling value messages according to the configuration of the CPU, and storing the sampling value messages in an Ethernet transmission buffer area;
and during sending, recombining the 2 parts of grouped sampling value messages to form a recombined message, wherein the recombining strategy is to recombine the data of the first sampling value message and the CRC of the second sampling value message to form a recombined message, and sending the recombined message to a receiving end device.
8. The reliability design method of claim 1, wherein the method further comprises: after receiving end device receives message, it judges if the message validity, channel valid mark and interval between sampling value messages of the message meet 250us, if detecting relevant fault, locking protective device action, including following steps:
if the data of the received message is consistent with the CRC, the message is legal, if the data of the received message is inconsistent with the CRC and the message is illegal, the message is discarded, and the action of a protection device is locked;
if the data valid flag is in an invalid state, discarding the message, and locking the protection device to act;
if the interval between the messages exceeds 250us, the messages are discarded, and the protection device is locked.
9. A reliability design device for sending a sampling value message of a merging unit is characterized by comprising the following steps:
the field programmable gate array FPGA is used for collecting analog quantity and carrying out interpolation to form a message and sending the message to the protection device;
and the receiving end device is used for judging the message legality, the data valid mark and the interval between the sampling value messages of the message after receiving the message, and locking the protection device to act if a relevant fault is detected.
10. The device for designing reliability of sending the sampling value messages of the merging units according to claim 9, wherein a time code pair and time keeping high-precision circuit is designed inside the FPGA, and can generate accurate sampling pulses of 4000sps for acquisition and interpolation of analog quantities;
the FPGA is internally provided with an 8-bit data verification FCS device for mainly acquiring 24 channel data, a data probe with fixed data of 16' h5A5A is arranged to judge whether the internal calculation of the FPGA is correct, the 8-bit verification FCS can identify whether the sampled value data is tampered when the sampled value data is carried in an RAM of the FPGA or processed in the FPGA, and the data probe can monitor whether single-bit or multi-bit data turnover and locking occur to hardware resources of an LUT and an REG register in the FPGA due to environmental factors, so that an effective mark for the sampled value data can be timely and correctly set.
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