CN105990259B - 半导体存储装置 - Google Patents

半导体存储装置 Download PDF

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Publication number
CN105990259B
CN105990259B CN201510996104.7A CN201510996104A CN105990259B CN 105990259 B CN105990259 B CN 105990259B CN 201510996104 A CN201510996104 A CN 201510996104A CN 105990259 B CN105990259 B CN 105990259B
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CN
China
Prior art keywords
joint sheet
wiring
electrically connected
memory
chips
Prior art date
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Active
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CN201510996104.7A
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English (en)
Chinese (zh)
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CN105990259A (zh
Inventor
谷本亮
铃谷信人
神山洋平
太田邦夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kioxia Corp
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Toshiba Memory Corp
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Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN105990259A publication Critical patent/CN105990259A/zh
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Publication of CN105990259B publication Critical patent/CN105990259B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Memory System (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201510996104.7A 2015-03-16 2015-12-25 半导体存储装置 Active CN105990259B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015052380A JP6293694B2 (ja) 2015-03-16 2015-03-16 半導体記憶装置
JP2015-052380 2015-03-16

Publications (2)

Publication Number Publication Date
CN105990259A CN105990259A (zh) 2016-10-05
CN105990259B true CN105990259B (zh) 2018-10-19

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510996104.7A Active CN105990259B (zh) 2015-03-16 2015-12-25 半导体存储装置

Country Status (3)

Country Link
JP (1) JP6293694B2 (ja)
CN (1) CN105990259B (ja)
TW (1) TWI608590B (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102556276B1 (ko) * 2018-06-26 2023-07-18 에스케이하이닉스 주식회사 저장 장치 및 그 동작 방법
CN110291631A (zh) 2019-05-17 2019-09-27 长江存储科技有限责任公司 具有静态随机存取存储器的三维存储器件
WO2020232571A1 (en) 2019-05-17 2020-11-26 Yangtze Memory Technologies Co., Ltd. Cache program operation of three-dimensional memory device with static random-access memory

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866915A (zh) * 2009-04-15 2010-10-20 三星电子株式会社 集成电路装置及其操作方法、存储器存储装置及电子***
CN103178036A (zh) * 2011-12-20 2013-06-26 株式会社东芝 半导体器件及其制造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6359340B1 (en) * 2000-07-28 2002-03-19 Advanced Semiconductor Engineering, Inc. Multichip module having a stacked chip arrangement
JP4963969B2 (ja) * 2007-01-10 2012-06-27 ルネサスエレクトロニクス株式会社 配線基板
KR20100114421A (ko) * 2009-04-15 2010-10-25 삼성전자주식회사 적층 패키지
KR101692441B1 (ko) * 2010-08-25 2017-01-03 삼성전자주식회사 반도체 패키지
KR20120035297A (ko) * 2010-10-05 2012-04-16 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
JP2012129464A (ja) * 2010-12-17 2012-07-05 Toshiba Corp 半導体装置およびその製造方法
JP2013021216A (ja) * 2011-07-13 2013-01-31 Toshiba Corp 積層型半導体パッケージ
KR101800440B1 (ko) * 2011-08-31 2017-11-23 삼성전자주식회사 다수의 반도체 칩들을 가진 반도체 패키지 및 그 형성 방법
JP5843803B2 (ja) * 2013-03-25 2016-01-13 株式会社東芝 半導体装置とその製造方法
TW201507067A (zh) * 2013-08-02 2015-02-16 Toshiba Kk 半導體裝置及其製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101866915A (zh) * 2009-04-15 2010-10-20 三星电子株式会社 集成电路装置及其操作方法、存储器存储装置及电子***
CN103178036A (zh) * 2011-12-20 2013-06-26 株式会社东芝 半导体器件及其制造方法

Also Published As

Publication number Publication date
TW201707187A (zh) 2017-02-16
JP6293694B2 (ja) 2018-03-14
JP2016174037A (ja) 2016-09-29
CN105990259A (zh) 2016-10-05
TWI608590B (zh) 2017-12-11

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Address after: Tokyo

Patentee after: Kaixia Co.,Ltd.

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Patentee before: TOSHIBA MEMORY Corp.

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Patentee before: Pangea Co.,Ltd.

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Effective date of registration: 20220221

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Patentee before: TOSHIBA MEMORY Corp.