CN105703767A - High-energy-efficiency low-jitter single loop clock data recovery circuit - Google Patents
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- H—ELECTRICITY
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Abstract
The invention discloses a high-energy-efficiency low-jitter single loop clock data recovery circuit. The circuit comprises an 1/N rate Bang-Bang phase discriminator with a 1:N demultiplexer function, a voltage-current converter, a loop filter and a multi-phase clock generator. An orthogonal clock signal generated by an orthogonal voltage control oscillator in the multi-phase clock generator is synthesized into a needed (N+2) phase recovery clock signal through a cascaded digital phase interpolator. And then the 1/N rate Bang-Bang phase discriminator receives input data and a phase clock signal, detects a phase relationship between the two to generate a lead/lag voltage signal and recovers N paths of parallel 1/N rate data signals. Then, the lead/lag voltage signal is converted into a current signal through the voltage-current converter. A current passes through loop filter filtering and then controls an output clock frequency and a phase relationship of the multi-phase clock generator so as to reduce a frequency deviation so that phase locking of a clock data recovery loop is reached. Jitter performance of the clock data recovery loop is effectively improved.
Description
Technical field
The present invention relates to serial communication and technical field of integrated circuits, particularly relate to the single loop clock data recovery circuit of a kind of high energy efficiency low jitter。
Background technology
It is the comprising modules of key in optical electrical communication system that high-frequency clock data recover (CDR) circuit, such as at synchronous optical network (SONET), the receiver end of the high speed serial communication systems such as EPON (PON) and ten thousand mbit ethernets (10GbE), the main target of clock data recovery circuit is exactly the data received in time recovering clock signal and to utilize this recovered clock to reset from input data in the way of high energy efficiency low jitter, this is a very challenging task with significance, constantly rising (having reached 10Gbps even higher) especially with message transmission rate。
Based on phaselocked loop (PLL,) clock data recovery circuit structure as shown in Figure 1, this structure is made up of frequency lock loop (FrequencyTrackingLoop) and phased lock loop (PhaseLockingLoop), when clock data recovery circuit starts, lock detector (LockDetector), by selecting control multiplexer (MUX) first to activate the frequency lock loop with phase frequency detector (Phase/FrequencyDetector), adjusts the frequency of oscillation of voltage controlled oscillator (VCO)；When the output frequency of voltage controlled oscillator is equal to external reference clock (Ref_Clk) frequency of M times, frequency lock loop disconnects, phased lock loop with phase discriminator (PhaseDetector) is started working, continuation adjusts the output frequency of voltage controlled oscillator until locking with input data phase, then passes through data decision (DataDecision) circuit retimed data。Two loops of this structure can share charge pump (ChargePump), loop filter (LoopFilter) and voltage controlled oscillator, loop switching is completed by lock detector, but so may interfere with controlling voltage and causing the metastable state between loop to change of voltage controlled oscillator, thus causing the losing lock of whole clock and data recovery loop；It addition, for the application (such as headend) of port separation distance and number critical constraints, use the low noise crystal oscillator of outside offer can increase extra cost and design difficulty as reference clock；The more important thing is, external reference clock signal can pass through encapsulation or printed circuit board (PCB) (PCB) is coupled in the input data of the low amplitude of oscillation, and then worsens the tradition jitter performance based on the clock data recovery circuit of phase-locked loop structures。
Based on phase interpolator (PI) clock data recovery circuit structure as shown in Figure 2, this structure needs also exist for two loops, it is different from and based on phase-locked loop structures is, frequency lock loop orthogonal voltage-controlled vibrator (QuadratureVCO) replaces voltage controlled oscillator herein, produces the quadrature clock signal needed for phased lock loop；And phased lock loop digital filter (DigitalLF) and digital to analog converter (DAC) replace electric charge pump and wave filter, voltage controlled oscillator is replaced, it is ensured that the stability of clock data recovery circuit and quick lock in by phase interpolator (Phaseinterpolator)。This structure can avoid the problem of shake peak value, but the jitter performance of clock data recovery circuit that the linearity of the precision of digital to analog converter, phase interpolator and loop delay all will directly affect based on phase interpolator structure；The more important thing is, structure medium frequency track loop based on phase interpolator needs to work always, bring very big power consumption and noise source thus to whole clock data recovery circuit, and on chip, between two loops, transmit the quadrature clock signal (reaching 10GHz or higher) of the same input the same frequency of data it is difficult to ensure that phase interpolator receives frequency stability and the phase orthogonality of clock, and then affect normally locking and the jitter performance of traditional clock data recovery circuit based on phase interpolator structure of phased lock loop。
Along with input data transfer rate, to rise to 10Gbps even higher, in order to reduce the operating frequency of phase discriminator, voltage controlled oscillator or phase interpolator, and then reducing required multi-phase clock frequency, the structure of the clock data recovery circuit of 1/N speed is widely used, as shown in Figure 3。This configuration avoids the accessible highest frequency restriction of clock on sheet, saves significantly on the power consumption of 1/N rate architecture；But the clock data recovery circuit of tradition 1/N rate architecture needs to provide 2N multi-phase clock to go sampling input data to the phase discriminator of 1/N speed, this adds extra power consumption and design complexities undoubtedly, the more important thing is, cross and between the multi-phase clock of more number, be easy to cause phase deviation, and then affect the jitter performance of the clock data recovery circuit of whole 1/N rate architecture。
Summary of the invention
Based on the technical problem that background technology exists, the present invention proposes the single loop clock data recovery circuit of a kind of high energy efficiency low jitter。
The single loop clock data recovery circuit of a kind of high energy efficiency low jitter that the present invention proposes, including: phase discriminator, voltage-current converter, loop filter and multi-phase clock generator, wherein, phase discriminator includes 1:N coupler functional module；
The first input end of phase discriminator accesses input data, its outfan is connected with voltage-current converter, voltage-current converter outfan is connected with loop filter input, the outfan of loop filter is connected with the input of multi-phase clock generator, and the outfan of multi-phase clock generator is connected with the second input of phase discriminator；
Phase discriminator receives input data and the M clock signal of multi-phase clock generator output, and generates leading voltage signal and lagging voltage signal, M=N+2 according to phase relation between the two；Voltage-current converter generates current signal according to leading voltage signal and lagging voltage signal, and current signal is filtered and generates control voltage signal by loop filter；Multi-phase clock generator constantly reduces the frequency departure between the M clock signal of output and input data and phase contrast under the adjustment controlling voltage signal, until the phase alignment of M clock signal and input data reaches loop-locking state；
The recovered clock signal of described clock recovery circuitry is the M clock signal of multi-phase clock generator output under loop-locking state。
Preferably, phase discriminator adopts 1/N speed Bang-Bang phase discriminator。
Preferably, phase discriminator includes: N number of data sampler, an edge sampler and two XOR gates；Described phase discriminator is preset with N phase data sampling clock, edge sampling clock and synchronised clock, and the frequency of N phase data sampling clock, the frequency of edge sampling clock and the frequency of synchronised clock are equal to the 1/N of input data frequency；
The input of N number of data sampler and the input of edge sampler are all connected with the first input end of described phase discriminator, N number of data sampler respectively under the control of N phase data sampling clock to sampling input data, sampled in the edge of input data by edge sampler under edge sampling clock controls；
N number of data sampler is a corresponding lock unit respectively, the outfan of data sampler connects the input of corresponding lock unit, N number of lock unit under the control of synchronised clock to respectively to input input data sampling signal reset time and produce 1/N rate recovery data signal, N number of microsyn output end output 1/N rate recovery data signal mutually parallel；Edge sampler is connected to a lock unit, and the data edge sampled signal of input is retimed and exports recovery edge signal under synchronised clock control by this lock unit；
Two inputs of one XOR gate are respectively connected to a 1/N rate recovery data signal and recover edge signal, then generate and comprise the leading voltage signal of phase information between data sampling clock and input data；Two inputs of another XOR gate are respectively connected to another 1/N rate recovery data signal and recover edge signal, then generate and comprise the lagging voltage signal of phase information between data sampling clock and input data。
Preferably, N=4。
Preferably, multi-phase clock generator is made up of the orthogonal voltage-controlled vibrator of cascade and numeral phase interpolator。
In the present invention, the quadrature clock signal that in multi-phase clock generator, orthogonal voltage-controlled vibrator produces, digit phase interpolation device through cascade synthesizes required M phase recovered clock signal, then 1/N speed Bang-Bang phase discriminator receives input data and M clock signal, detection phase relation therebetween generates lead-lag voltage signal, and recover the 1/N rate data signal that N road is parallel, then lead-lag voltage signal converts current signal to by voltage-current converter, output clock frequency and the phase relation of this electric current control multi-phase clock generator after loop filter filters reduce frequency departure and then reach the PGC demodulation of clock and data recovery loop。M=N+2。
The present invention proposes a kind of clock data recovery circuit framework with compact 1/N speed Bang-Bang phase discriminator, while reducing the module operating frequencies such as Bang-Bang phase discriminator, orthogonal voltage-controlled vibrator and numeral phase interpolator, not only alleviate circuit entire area burden and design complexities, and effectively reduce the required multi-phase clock number of Bang-Bang phase discriminator sampling and overall power consumption；The present invention adopts the single loop clock data recovery circuit structure without reference clock, not only eliminate external reference clock and input data are coupled the loop jitter performance deleterious effects caused, and avoid and between double loop, switch the interference on voltage controlled oscillator control voltage and the impact on loop stability；Additionally, orthogonal voltage-controlled vibrator and numeral phase interpolator level are associated in the multi-phase clock generator design in same clock and data recovery loop, eliminate extra power consumption and noise source that traditional double loop structure brings for the phase-locked loop producing multi-phase clock, not only enormously simplify the structure of whole clock data recovery circuit, and it is effectively increased the efficiency of clock data recovery circuit, effectively improve the jitter performance of clock and data recovery loop simultaneously。
Accompanying drawing explanation
Fig. 1 is the structural representation of the clock data recovery circuit based on phase-locked loop pll；
Fig. 2 is the structural representation of the clock data recovery circuit based on phase interpolator PI；
Fig. 3 is the structural representation of 1/N rate clock data recovery circuit；
Fig. 4 is the structural representation of the single loop clock data recovery circuit of a kind of high energy efficiency low jitter provided by the invention；
Fig. 5 is the structural representation of the single loop clock data recovery circuit of a kind of high energy efficiency low jitter of offer in the embodiment of the present invention；
The structural representation of the Fig. 6 a kind of 1/4 speed Bang-Bang phase discriminator QR-BBPD with 1:4 coupler DEMUX function for providing in the embodiment of the present invention；
The structural representation of the Fig. 7 a kind of multi-phase clock generator MPG for providing in the embodiment of the present invention；
The 6 phase recovered clock signal waveforms that the single loop clock data recovery circuit of the Fig. 8 a kind of high energy efficiency low jitter for providing in the embodiment of the present invention exports；
The single loop clock data recovery circuit of the Fig. 9 a kind of high energy efficiency low jitter for providing in the embodiment of the present invention exports the phase noise curve chart of recovered clock signal；
The recovered clock eye pattern that the single loop clock data recovery circuit of the Figure 10 a kind of high energy efficiency low jitter for providing in the embodiment of the present invention exports；
The recovery data eye that the single loop clock data recovery circuit of the Figure 11 a kind of high energy efficiency low jitter for providing in the embodiment of the present invention exports。
Detailed description of the invention
Reference Fig. 4, the single loop clock data recovery circuit of a kind of high energy efficiency low jitter that the present invention proposes, including: phase discriminator, voltage-current converter, loop filter and multi-phase clock generator。Wherein, phase discriminator phase discriminator adopts 1/N speed Bang-Bang phase discriminator, and it includes 1:N coupler functional module。
The first input end of phase discriminator accesses input data DATA, its outfan is connected with voltage-current converter, voltage-current converter outfan is connected with loop filter input, the outfan of loop filter is connected with the input of multi-phase clock generator, and the outfan of multi-phase clock generator is connected with the second input of phase discriminator。
Phase discriminator receives input data and the M clock signal of multi-phase clock generator output, and generates leading voltage signal UP and lagging voltage signal DN, M=N+2 according to phase relation between the two。
Phase discriminator includes: N number of data sampler, an edge sampler and two XOR gates。Described phase discriminator is preset with N phase data sampling clock, edge sampling clock and synchronised clock, and the frequency of N phase data sampling clock, the frequency of edge sampling clock and the frequency of synchronised clock are equal to the 1/N of input data DATA frequency。
The input of N number of data sampler and the input of edge sampler are all connected with the first input end of described phase discriminator, sampling input data is generated input data sampling signal by N number of data sampler respectively under the control of N phase data sampling clock, and the edge of input data is carried out sampling under edge sampling clock controls and generates data edge sampled signal by edge sampler。
N number of data sampler is a corresponding lock unit respectively, the outfan of data sampler connects the input of corresponding lock unit, N number of lock unit under the control of synchronised clock to respectively to input input data sampling signal reset time and produce 1/N rate recovery data signal, N number of microsyn output end output 1/N rate recovery data signal mutually parallel。Edge sampler is connected to a lock unit, and the data edge sampled signal of input is retimed and exports recovery edge signal under synchronised clock control by this lock unit。
Two inputs of one of them XOR gate are respectively connected to a 1/N rate recovery data signal and recover edge signal, then generate and comprise the leading voltage signal UP of phase information between data sampling clock and input data DATA；Two inputs of another XOR gate are respectively connected to another 1/N rate recovery data signal and recover edge signal, then generate and comprise the lagging voltage signal DN of phase information between data sampling clock and input data DATA。
Voltage-current converter generates current signal I according to leading voltage signal UP and lagging voltage signal DNVIC, loop filter is to current signal IVICIt is filtered and generates control voltage signal VCTRL。Multi-phase clock generator is controlling voltage signal VCTRLAdjustment under constantly reduce output M clock signal and input data DATA between frequency departure and phase contrast, until the phase alignment of M clock signal and input data reaches loop-locking state, the clock signal that namely recovered clock signal now is multi-phase clock generator recovers from input data, and recovery data signal now to be namely 1/N speed Bang-Bang phase discriminator synchronize, by (N+2) phase recovered clock signal sampling, the 1/N rate data signal that the N road that recovers is parallel。That is, the recovered clock signal RE_CIK of clock recovery circuitry is the M clock signal of multi-phase clock generator output under loop-locking state。
In present embodiment, multi-phase clock generator is made up of the orthogonal voltage-controlled vibrator of cascade and numeral phase interpolator, wherein, the input of orthogonal voltage-controlled vibrator as the outfan of the input linkloop wave filter of multi-phase clock generator with Access Control voltage signal VCTRL。Orthogonal voltage-controlled vibrator is controlling voltage signal VCTRLAdjustment under, constantly reduce output clock and input data Data between frequency departure。The input of digit phase interpolation device is connected with orthogonal voltage-controlled vibrator, its outfan is as the second input of the outfan connection phase discriminator of multi-phase clock generator, its signal syntheses M clock signal according to orthogonal voltage-controlled vibrator input, and controlling voltage signal VCTRLThe phase contrast between M clock signal and input data Data is reduced under effect。
Below in conjunction with a specific embodiment, the present invention is further explained。
With reference to Fig. 5, in the single loop clock data recovery circuit of a kind of high energy efficiency low jitter that the present embodiment provides, what phase discriminator adopted is with 1:4 coupler (DEMUX, Demultiplexer) 1/4 speed Bang-Bang phase discriminator (QR-BBPD, Quarter-RateBang-BangPhaseDetector) of functional module。
The 1/4 speed Bang-Bang phase discriminator with 1:4 coupler functional module receives input data Data and 6 phase recovered clock signal Re_Clk of multi-phase clock generator output, and the testing result according to phase relation therebetween generates leading voltage signal UP and lagging voltage signal DN。
Lead-lag voltage signal Up/Dn is converted to the current signal IVIC of correspondence by voltage-current converter VIC；Loop filter LF receives the current signal IVIC after the conversion of lead-lag voltage, generates the control voltage signal VCTRL of multi-phase clock generator MPG after filtering；Multi-phase clock generator MPG, under the adjustment controlling voltage signal VCTRL, constantly reduces the frequency departure between 6 phase recovered clock signal Re_Clk of output and input data Data and phase contrast。The phase alignment of clock signal Re_Clk and input data Data reaches loop-locking state when recovered, the clock signal that namely recovered clock signal Re_Clk now is multi-phase clock generator MPG recovers from input data Data, and 1/4 rate data signal that 4 tunnels that to be namely 1/4 speed Bang-Bang phase discriminator QR-BBPD recovered by 6 phase recovered clock signal Re_Clk sample-synchronous of recovery data signal Re_Data now are parallel。
Fig. 6 show the structural representation of the 1/4 speed Bang-Bang phase discriminator QR-BBPD with 1:4 coupler functional module that the present embodiment provides。
This phase discriminator utilizes 4 data sampler (samplers 1, sampler 2, sampler 4 and sampler 5) and 4 phase data sampling clock Re_Clk0, Re_Clk90, Re_Clk180 and Re_Clk270 samples and inputs data Data, and utilize an edge sampler (sampler 3) and edge sampling clock Re_Clk135 to input data edge of sampling, then 5 lock unit (lock units 1 are utilized, lock unit 2, lock unit 3, lock unit 4 and lock unit 5) and 4 tunnels input data sampling signal and data edge sampled signals when a synchronised clock Re_Clk315 resets, wherein input data sampling signal is the input data after sampling, data edge sampled signal is the input data edge after sampling。Phase discriminator recovers, according to input data sampling signal, the 1/4 rate recovery data signal Re_Data0 that 4 tunnels are parallel, Re_Data1, Re_Data2 and Re_Data3, and recover recovery edge signal Re_Edge0 according to data edge sampled signal, wherein two-way recovery data signal Re_Data1 and Re_Data2 comprises the leading voltage signal UP and lagging voltage signal DN of phase information between sampling clock Re_Clk and input data Data with recovery edge signal Re_Edge0 by XOR gate XOR_1 and XOR_2 generation respectively, all of which 6 phase clock Re_Clk0, Re_Clk90, Re_Clk135, Re_Clk180, the frequency of Re_Clk270 and Re_Clk315 is equal to the 1/4 of input data Data frequency。
Fig. 7 show the structural representation of the multi-phase clock generator MPG that the present embodiment provides。Multi-phase clock generator MPG is by the orthogonal voltage-controlled vibrator (QVCO of cascade, QuadratureVoltage-ControlledOscillator) and numeral phase interpolator (DPI, DigitalPhaseInterpolator) composition, is controlling voltage signal VCTRLAdjustment under, constantly reduce orthogonal voltage-controlled vibrator QVCO output orthogonal clock (Ip, Qp, In and Qn) and input data Data between frequency departure and digit phase interpolation device DPI synthesis 6 clock signal (Re_Clk0, Re_Clk90, Re_Clk135, Re_Clk180, Re_Clk270 and Re_Clk315) and input data Data between phase contrast。
In order to further illustrate beneficial effects of the present invention, the single loop clock data recovery circuit of the high energy efficiency low jitter that the present embodiment provides is carried out simulating, verifying。Inputting data Data in embodiment is the pseudo-random sequence of 10.3125Gbps, emulation duration is 10us, overall clock data recovery circuit loop locks at about about 2.3us, the recovered clock signal Re_Clk0 of 1/4 speed, Re_Clk90, Re_Clk135, Re_Clk180, Re_Clk270 and Re_Clk315 frequency are 2.578125GHz, and the recovery data signal Re_Data0 of 1/4 speed, Re_Data1, Re_Data2 and Re_Data3 data transfer rate are 2.578125Gbps。
6 phase recovered clock signal waveforms of output that Fig. 8 show in the present embodiment multi-phase clock generator MPG, orthogonal voltage-controlled vibrator QVCO and the 6 phase recovered clock signal Re_Clk0 of multi-phase clock generator MPG offer of numeral phase interpolator DPI cascade composition, Re_Clk90, Re_Clk135, Re_Clk180, Re_Clk270 and the Re_Clk315 average phase error in output frequency 2.578125GHz vicinity are 0.015 °, illustrate have accurate phase relation between the recovered clock signal that the clock data recovery circuit of the present invention exports。
Fig. 9 show the phase noise curve chart of the single loop clock data recovery circuit output recovered clock signal of a kind of high energy efficiency low jitter of offer in the present embodiment, the recovered clock signal Re_Clk that the multi-phase clock generator MPG of orthogonal voltage-controlled vibrator QVCO and numeral phase interpolator DPI cascade composition the provides phase noise at 1MHz frequency place is-118dBC/Hz, illustrates that the recovered clock signal of the clock data recovery circuit output of the present invention has good noiseproof feature。
Figure 10 show the recovered clock eye pattern of the single loop clock data recovery circuit output of a kind of high energy efficiency low jitter of offer in the embodiment of the present invention, when inputting 231-1 pseudo-random sequence data, the clock of 1/4 speed recovered has the Peak Jitter of 1.14ps, illustrates that the recovered clock signal of the clock data recovery circuit output of the present invention has good jitter performance。
Figure 11 show the recovery data eye of the single loop clock data recovery circuit output of a kind of high energy efficiency low jitter of offer in the embodiment of the present invention, when inputting 231-1 pseudo-random sequence data, the data of 1/4 speed recovered have the Peak Jitter of 1.21ps, and the advantage that the recovery data signal of the clock data recovery circuit output of the present invention has low jitter equally is described；Additionally, clock data recovery circuit in the embodiment of the present invention consumes 4.8mW altogether under 1.1V supply voltage, wherein multi-phase clock generator MPG consumes 3.4mW, and circuit entirety efficiency is 0.47pJ/b, illustrates that the clock data recovery circuit of the present invention has significantly high efficiency under high data rate applications。
Those skilled in the art is it can be understood that arrive, for convenience and simplicity of description, only it is illustrated with the division of above-mentioned each functional module, in practical application, as desired above-mentioned functions distribution can be completed by different functional modules, it is divided into different functional modules, to complete all or part of function described above by the internal structure of device。
The above; it is only the present invention preferably detailed description of the invention; but protection scope of the present invention is not limited thereto; any those familiar with the art is in the technical scope that the invention discloses; it is equal to replacement according to technical scheme and inventive concept thereof or is changed, all should be encompassed within protection scope of the present invention。
Claims (5)
1. the single loop clock data recovery circuit of a high energy efficiency low jitter, it is characterised in that including: phase discriminator, voltage-current converter, loop filter and multi-phase clock generator, wherein, phase discriminator includes 1:N coupler functional module；
The first input end of phase discriminator accesses input data (DATA), its outfan is connected with voltage-current converter, voltage-current converter outfan is connected with loop filter input, the outfan of loop filter is connected with the input of multi-phase clock generator, and the outfan of multi-phase clock generator is connected with the second input of phase discriminator；
Phase discriminator receives input data and the M clock signal of multi-phase clock generator output, and generates leading voltage signal (UP) and lagging voltage signal (DN), M=N+2 according to phase relation between the two；Voltage-current converter generates current signal (I according to leading voltage signal (UP) and lagging voltage signal (DN)VIC), loop filter is to current signal (IVIC) it is filtered and generates control voltage signal (VCTRL)；Multi-phase clock generator is controlling voltage signal (VCTRL) adjustment under constantly reduce the frequency departure between the M clock signal of output and input data (DATA) and phase contrast, until the phase alignment of M clock signal and input data reaches loop-locking state；
The recovered clock signal (RE_CIK) of described clock recovery circuitry is the M clock signal of multi-phase clock generator output under loop-locking state。
2. the single loop clock data recovery circuit of high energy efficiency low jitter as claimed in claim 1, it is characterised in that phase discriminator adopts 1/N speed Bang-Bang phase discriminator。
3. the single loop clock data recovery circuit of high energy efficiency low jitter as claimed in claim 1, it is characterised in that phase discriminator includes: N number of data sampler, an edge sampler and two XOR gates；Described phase discriminator is preset with N phase data sampling clock, edge sampling clock and synchronised clock, and the frequency of N phase data sampling clock, the frequency of edge sampling clock and the frequency of synchronised clock are equal to the 1/N of input data frequency；
The input of N number of data sampler and the input of edge sampler are all connected with the first input end of described phase discriminator, N number of data sampler respectively under the control of N phase data sampling clock to sampling input data, sampled in the edge of input data by edge sampler under edge sampling clock controls；
N number of data sampler is a corresponding lock unit respectively, the outfan of data sampler connects the input of corresponding lock unit, N number of lock unit under the control of synchronised clock to respectively to input input data sampling signal reset time and produce 1/N rate recovery data signal, N number of microsyn output end output 1/N rate recovery data signal mutually parallel；Edge sampler is connected to a lock unit, and the data edge sampled signal of input is retimed and exports recovery edge signal under synchronised clock control by this lock unit；
Two inputs of one XOR gate are respectively connected to a 1/N rate recovery data signal and recover edge signal, then generate and comprise the leading voltage signal (UP) of phase information between data sampling clock and input data (Data)；Two inputs of another XOR gate are respectively connected to another 1/N rate recovery data signal and recover edge signal, then generate and comprise the lagging voltage signal (DN) of phase information between data sampling clock and input data (Data)。
4. the single loop clock data recovery circuit of high energy efficiency low jitter as claimed in claim 3, it is characterised in that N=4。
5. the single loop clock data recovery circuit of high energy efficiency low jitter as claimed in claim 1, it is characterised in that multi-phase clock generator is made up of the orthogonal voltage-controlled vibrator of cascade and numeral phase interpolator。
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