CN109889196A - A kind of small area low power consuming clock data recovery circuit - Google Patents
A kind of small area low power consuming clock data recovery circuit Download PDFInfo
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- CN109889196A CN109889196A CN201910102503.2A CN201910102503A CN109889196A CN 109889196 A CN109889196 A CN 109889196A CN 201910102503 A CN201910102503 A CN 201910102503A CN 109889196 A CN109889196 A CN 109889196A
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Abstract
The invention discloses a kind of small area low power consuming clock data recovery circuits, including phase frequency detector, frequency divider, the first charge pump, the second charge pump, Bang-bang phase discriminator, loop filter, voltage controlled oscillator, the 7th switch, the input of phase frequency detector terminates input signal, and the first output end of divided device connection voltage controlled oscillator；The input terminal of voltage controlled oscillator is connected with loop filter, and second and third four or five output end is connected with first to fourth input terminal of Bang-bang phase discriminator, five or six input of Bang-bang phase discriminator terminates positive and negative differential input signal, and its first to fourth output end, as entire circuit output end, the 5th output end is connected with the second charge pump；Second charge pump passes through the 7th switch connection power supply and the second input terminal of output end and loop filterIt is connected；First charge pump connects phase frequency detector, and output end is connected to the first input end of loop filter.The bicyclic alternation power consumption of the present invention is lower, reduces area, takes into account and establish speed and noiseproof feature.
Description
Technical field
The present invention relates to a kind of small area low power consuming clock data recovery circuits, belong to clock data recovery circuit technology neck
Domain.
Background technique
Clock and data recovery (Clock Data Recovery, abbreviation CDR) is the nucleus module of high-speed communication interface,
Effect be recover high quality clock information, and with the clock signal recovered to produced in transmission process distortion, superposition
The data-signal of noise carries out resampling, recovers the data of high-quality.
Existing CDR designing technique, generallys use twin nuclei: using frequency locking ring (Frequency-Locked Loop,
Abbreviation FLL) realize clock frequency recovery, make clock edge using phaselocked loop (Phase-Locked Loop, abbreviation PLL)
Aligned data center, i.e. optimum sampling point, then the resampling of complete paired data.In order to keep the result of FLL and be applied to
It is bicyclic to need while opening in PLL.In order to reduce power consumption, FLL and PLL can be allowed to work alternatively, but FLL locks result
Holding need additional loop filtering capacitor to realize.Loop filtering capacitor occupies biggish area in entire chip, with
For the CDR of ring oscillator, loop filtering capacity area accounts for the CDR gross area about 50%.
Bicyclic multiplexing loop filtering technology can alleviate the contradiction between above-mentioned power consumption and area, but FLL has with PLL
Different missions and feature: usually requiring that FLL can use the smallest resource quick lock in, and requires PLL noise suppression with higher
System level and stability.The parameter of other modules of FLL Yu PLL loop also has bigger difference.Simple multiplexing loop filter makes
It obtains bicyclic flexibility to lose, loop parameter can not be reasonably set, and the optimization of CDR performance is restricted.
Summary of the invention
Technical problem to be solved by the present invention lies in overcome in available data restoring circuit using bicyclic so that flexibility
It loses, loop parameter can not be reasonably set, and the deficiency that the optimization of CDR performance is restricted provides a kind of small area low-power consumption
Clock data recovery circuit.Pass through bicyclic alternation and use novel capacitor composite loop filter, can both save core
Piece area, and advantage of the bicyclic parameter flexibility in the optimization of CDR performance can not be lost.
The present invention specifically uses following technical scheme to solve above-mentioned technical problem:
A kind of small area low power consuming clock data recovery circuit, including phase frequency detector, frequency divider, the first charge pump,
Two charge pumps, Bang-bang phase discriminator, loop filter, voltage controlled oscillator, the 7th switch, wherein the first of phase frequency detector
Input termination input signal Fref, the second input terminal of phase frequency detector is connected with the output end of frequency divider, and frequency divider is defeated
Enter end to be connected with the first output end of voltage controlled oscillator；The output end phase of the input terminal of the voltage controlled oscillator and loop filter
Even and the second, third, fourth, fifth output end of voltage controlled oscillator respectively with the first, second of Bang-bang phase discriminator, the
Three, the 4th input terminal is connected, and the five, the 6th input terminals of the Bang-bang phase discriminator connect positive and negative differential input signal respectively,
And the data that the first, second, third, fourth output end of Bang-bang phase discriminator restores as the output of entire circuit output end,
And the 5th output end of Bang-bang phase discriminator is connected with the input terminal of the second charge pump；Second charge pump passes through the 7th
Switch is connected to power supply, and the output end of the second charge pump is connected with the second input terminal of loop filter；First electricity
The output end of the input terminal connection phase frequency detector of lotus pump, and the output end of the first charge pump is connected to the first of loop filter
Input terminal.
Further, as a preferred technical solution of the present invention, the loop filter includes first switch, second
Switch, third switch, the 4th switch, the 5th switch, the 6th switch, first resistor, second resistance, 3rd resistor, first capacitor,
Second capacitor, third capacitor, the 4th capacitor, the first operational amplifier；The first end of the first switch is as loop filter
First input end meet input signal inf, the second end of first switch respectively with the first end of second switch, first resistor
One end is connected；The second end of the second switch first end with the positive input terminal of the first operational amplifier, the second capacitor respectively
It is connected, and the second end ground connection of the second capacitor；The negative input end of first operational amplifier is connected to the first operational amplifier
Output end, and the output end of the first operational amplifier respectively with third switch first end, the 4th switch first end, the 5th
The first end of switch is connected；The second end of third switch, the first end of 3rd resistor, the first end of third capacitor and the
The first end of two resistance inputs as the second of loop filter after connecting jointly and terminates input signal inp；The third capacitor
Second end ground connection；Second end, the second end of second resistance of the first resistor are connected with the first end of first capacitor respectively,
And the second end ground connection of first capacitor；The second end of the 3rd resistor, the second end of the 4th switch, the first end of the 6th switch
It is connected respectively with the first end of the 4th capacitor, and the second end ground connection of the 4th capacitor；The second end and the 6th of 5th switch
Output end after the second end of switch is connected as loop filter obtains output signal out.
Further, as a preferred technical solution of the present invention, the first switch, second switch, third switch,
4th switch and the 5th switch are by first control signal Φ1Control, the 6th switch and the 7th switch are by the second control
SignalControl, and first control signal Φ1And second control signalFor a pair of opposite control signal.
Further, as a preferred technical solution of the present invention, the first control signal Φ1Control circuit work
In FLL state, specifically:
First control signal Φ1Control first switch, second switch, third switch, the 4th switch and the 5th switch S5It leads
Logical, the 6th switch and the 7th switch disconnect；Second-order filter circuit is constituted by first resistor, first capacitor, the second capacitor；It utilizes
First operational amplifier replicates the output current potential of second-order filter circuit, and is pre-charged to third capacitor and the 4th capacitor, and
Output signal out is obtained through the 5th switch.
Further, as a preferred technical solution of the present invention, the second control signalControl circuit work
In PLL state, specifically:
By first control signal Φ1Switch to second control signalSo that first switch, second switch, third switch,
4th switch and the 5th switch disconnect, by second control signalControl the 6th switch and the 7th switch S7Conducting, it is described
Second resistance, first capacitor, third capacitor, 3rd resistor and the 4th capacitor constitute three rank filter circuits, and Ji Jing six is switched
To output signal out.
The present invention by adopting the above technical scheme, can have the following technical effects:
Small area low power consuming clock data recovery circuit of the invention, is based on twin nuclei, and bicyclic alternation is simultaneously multiplexed
The biggish first capacitor C of area occupied1, both reduced power consumption and also significantly reduced chip area.In addition, pulling ring in frequency
Second order filter is used in FLL and loop bandwidth is relatively large, so that loop-locking speed is fast.And it is extensive in phase alignment and data
During multiple, i.e. what is come into force in PLL is third-order filter, and loop bandwidth is also relatively small, and noiseproof feature gets a promotion.In clock
In data recovery procedure, noise characteristic that the signal quality for influencing finally to recover is PLL.Therefore, disclosed in this invention
Small area low power consuming clock data recovery circuit can be taken into account while reducing area and establish speed and noiseproof feature.
Detailed description of the invention
Fig. 1 is a kind of structure principle chart of small area low power consuming clock data recovery circuit of the present invention.
Fig. 2 is schematic diagram of the loop filter of the present invention work under FLL state.
Fig. 3 is schematic diagram of the loop filter of the present invention work under PLL state.
Fig. 4 is the simulation result of clock data recovery circuit establishment process in the present invention.
Specific embodiment
Embodiments of the present invention are described with reference to the accompanying drawings of the specification.
As shown in Figure 1, the present invention provides a kind of small area low power consuming clock data recovery circuit, including frequency and phase discrimination
Device, frequency divider, the first charge pump, the second charge pump, Bang-bang phase discriminator, loop filter, voltage controlled oscillator, the 7th open
Close S7.Wherein, the first input end of phase frequency detector connects input signal Fref, the second input terminal and frequency divider of phase frequency detector
Output end be connected, and the input terminal of frequency divider is connected with the first output end of voltage controlled oscillator；The voltage controlled oscillator it is defeated
Enter end be connected with the output end of loop filter and the second, third, fourth, fifth output end of voltage controlled oscillator respectively with
First, second, third, fourth input terminal of Bang-bang phase discriminator is connected in Clk 0, Clk 90, Clk 180, Clk270 letter
Number, the five, the 6th input terminals of the Bang-bang phase discriminator meet positive and negative differential input signal Data+, Data- respectively, and
The data that first, second, third, fourth output end of Bang-bang phase discriminator restores as the output of entire circuit output end, and
5th output end of Bang-bang phase discriminator is connected with the input terminal of the second charge pump；Second charge pump is opened by the 7th
It closes S7 and is connected to power supply, and the output end of the second charge pump is connected with the second input terminal of loop filter；First electricity
The output end of the input terminal connection phase frequency detector of lotus pump, and the output end of the first charge pump is connected to the first of loop filter
Input terminal.
In the present invention, the structure of the loop filter is as shown in Figure 1, it mainly includes first switch S1, second switch
S2, third switch S3, the 4th switch S4, the 5th switch S5, the 6th switch S6, first resistor R1F, second resistance R1P, 3rd resistor
R2, first capacitor C1, the second capacitor C2F, third capacitor C2P, the 4th capacitor C3, the first operational amplifier A1；Wherein, described first
Switch S1First end meet input signal inf, first switch S as the first input end of loop filter1Second end respectively with
Second switch S2First end, first resistor R1FFirst end be connected；The second switch S2Second end respectively with first fortune
Calculate amplifier A1Positive input terminal, the second capacitor C2FFirst end be connected, and the second capacitor C2FSecond end ground connection；Described first
Operational amplifier A1Negative input end be connected to the first operational amplifier A1Output end, and the first operational amplifier A1Output
End respectively with third switch S3First end, the 4th switch S4First end, the 5th switch S5First end be connected；The third
Switch S3Second end, 3rd resistor R2First end, third capacitor C2PFirst end and second resistance R1PFirst end it is total
With the second input termination input signal inp after connection as loop filter；The third capacitor C2PSecond end ground connection；Institute
State first resistor R1FSecond end, second resistance R1PSecond end respectively with first capacitor C1First end be connected, and first electricity
Hold C1Second end ground connection；The 3rd resistor R2Second end, the 4th switch S4Second end, the 6th switch S6First end
Respectively with the 4th capacitor C3First end be connected, and the 4th capacitor C3Second end ground connection；The 5th switch S5Second end with
6th switch S6Second end be connected after as the output end of loop filter obtain output signal out.
Small area low power consuming clock data recovery circuit of the invention includes FLL loop and PLL loop, the two loops
It works alternatively；When by first control signal Φ1The first switch S of control1, second switch S2, third switch S3, the 4th switch S4With
And the 5th switch S5When conducting, the 6th switch S6And the 7th switch S7It disconnects, circuit works in FLL state；When by the second control
Signal6th switch S of control6And the 7th switch S7When disconnecting conducting, first switch S1, second switch S2, third switch
S3, the 4th switch S4And the 5th switch S5It disconnects, circuit works in PLL state.The first control signal Φ1With the second control
Signal processedFor a pair of opposite control signal.
As shown in Fig. 2, being the schematic diagram of loop filter operative of the invention under FLL state.At this point, by the first control
Signal Phi1Control first switch S1, second switch S2, third switch S3, the 4th switch S4And the 5th switch S5Conducting, at this time the
Six switch S6And the 7th switch S7It disconnects.First resistor R1F, first capacitor C1, the second capacitor C2FConstitute second-order filter circuit.
Utilize the first operational amplifier of operation A1The output current potential for replicating the second-order filter circuit, to third capacitor C2PWith the 4th capacitor C3
It is pre-charged, and through the 5th switch S5Obtain output signal out.In addition, the second charge pump power supply is cut off under FLL state,
Second charge pump outputs current potential also follows the output of the second-order filter circuit, and charge point is generated when preventing circuit state from switching
Enjoy influence stability.Above-mentioned precharge follows and final output, is all in the first operational amplifier A1Later, this be for
Eliminate the first operational amplifier A1Mismatch circuit state switch when cause to disturb.
As shown in figure 3, being the schematic diagram of loop filter operative of the invention under PLL state.First control signal Φ1
And second control signalThis pair of opposite control signal is switched fast, so that first switch S1, second switch S2, third opens
Close S3, the 4th switch S4And the 5th switch S5It disconnects, second control signalControl the 6th switch S6And the 7th switch S7It leads
It is logical.Moment after switching, first capacitor C1, third capacitor C2P, the 4th capacitor C3Upper step current potential and node i np current potential protect
The output result after FLL stablizes is held.Into after PLL state, second resistance R1P, first capacitor C1, third capacitor C2P, third electricity
Hinder R2With the 4th capacitor C3Constitute three rank filter circuits, six switch S of Ji Jing6Obtain output signal out.
In loop filter designs, first capacitor C1Capacitance it is maximum, area occupied is also maximum, about 90%.This hair
It is bright to have shared first capacitor C1, substantially reduce chip area.In addition, using second order filter and loop bandwidth phase in FLL
To larger, although noiseproof feature is poor, loop-locking speed is fast.And what is come into force in a pll is third-order filter, loop bandwidth
Also relatively small, noiseproof feature gets a promotion.
As shown in figure 4, imitative for a kind of establishment process of small area low power consuming clock data recovery circuit disclosed by the invention
True result.In (1) stage, clock data recovery circuit works in FLL state, loop quick lock in；Circuit switches after 10 μ s
To PLL state, that is, enter in (2) stage, circuit locks after phase is corrected in one small disturbance of experience.In order to sufficiently test
Circuit is demonstrate,proved, the locking frequency of FLL differs 10MHz with the code rate of input data, therefore the final stabilization in (1) stage and (2) stage
Voltage is different.
To sum up, small area low power consuming clock data recovery circuit of the invention influences most during clock and data recovery
The noise characteristic that the signal quality recovered eventually is PLL.In addition, bicyclic alternation, power consumption are lower.Therefore, institute of the present invention
Disclosed small area low power consuming clock data recovery circuit can be taken into account while reducing area and establish speed and noise-induced
Energy.
Embodiments of the present invention are explained in detail above in conjunction with attached drawing, but the present invention is not limited to above-mentioned implementations
Mode within the knowledge of a person skilled in the art can also be without departing from the purpose of the present invention
It makes a variety of changes.
Claims (5)
1. a kind of small area low power consuming clock data recovery circuit, it is characterised in that: including phase frequency detector, frequency divider, first
Charge pump, the second charge pump, Bang-bang phase discriminator, loop filter, voltage controlled oscillator, the 7th switch (S7), wherein frequency discrimination
The first input end of phase discriminator meets input signal Fref, and the second input terminal of phase frequency detector is connected with the output end of frequency divider,
And the input terminal of frequency divider is connected with the first output end of voltage controlled oscillator；The input terminal and loop filtering of the voltage controlled oscillator
The output end of device be connected and the second, third, fourth, fifth output end of voltage controlled oscillator respectively with Bang-bang phase discriminator
First, second, third, fourth input terminal is connected, and the five, the 6th input terminals of the Bang-bang phase discriminator connect positive and negative respectively
First, second, third, fourth output end of differential input signal and Bang-bang phase discriminator is defeated as entire circuit output end
5th output end of the data and Bang-bang phase discriminator restored out is connected with the input terminal of the second charge pump；Second electricity
Lotus pump is connected to power supply, and the second input terminal of the output end of the second charge pump and loop filter by the 7th switch (S7)
It is connected；The output end of the input terminal connection phase frequency detector of first charge pump, and the output end of the first charge pump is connected to
The first input end of loop filter.
2. small area low power consuming clock data recovery circuit according to claim 1, it is characterised in that: the loop filtering
Device includes first switch (S1), second switch (S2), third switch (S3), the 4th switch (S4), the 5th switch (S5), the 6th switch
(S6), first resistor (R1F), second resistance (R1P), 3rd resistor (R2), first capacitor (C1), the second capacitor (C2F), third electricity
Hold (C2P), the 4th capacitor (C3), the first operational amplifier (A1)；First switch (the S1) first end as loop filter
First input end meet input signal inf, first switch (S1) second end respectively with second switch (S2) first end, first
Resistance (R1F) first end be connected；Second switch (the S2) second end respectively with the first operational amplifier (A1) positive input
End, the second capacitor (C2F) first end be connected, and the second capacitor (C2F) second end ground connection；First operational amplifier (the A1)
Negative input end be connected to the first operational amplifier (A1) output end, and the first operational amplifier (A1) output end respectively with
Third switchs (S3) first end, the 4th switch (S4) first end, the 5th switch (S5) first end be connected；The third is opened
Close (S3) second end, 3rd resistor (R2) first end, third capacitor (C2P) first end and second resistance (R1P)
One end inputs as the second of loop filter after connecting jointly and terminates input signal inp；Third capacitor (the C2P) second
End ground connection；First resistor (the R1F) second end, second resistance (R1P) second end respectively with first capacitor (C1) first
End is connected, and first capacitor (C1) second end ground connection；3rd resistor (the R2) second end, the 4th switch (S4) second
End, the 6th switch (S6) first end respectively with the 4th capacitor (C3) first end be connected, and the 4th capacitor (C3) second termination
Ground；5th switch (the S5) second end with the 6th switch (S6) second end be connected after output end as loop filter
Obtain output signal out.
3. small area low power consuming clock data recovery circuit according to claim 2, it is characterised in that: the first switch
(S1), second switch (S2), third switch (S3), the 4th switch (S4) and the 5th switch (S5) by first control signal Φ1Control
System, the 6th switch (S6) and the 7th switch (S7) by second control signalControl, and first control signal Φ1With
Two control signalsFor a pair of opposite control signal.
4. small area low power consuming clock data recovery circuit according to claim 3, it is characterised in that: first control
Signal Phi1Control circuit works in FLL state, specifically:
First control signal Φ1Control first switch (S1), second switch (S2), third switch (S3), the 4th switch (S4) and
5th switch (S5) conducting, the 6th switch (S6) and the 7th switch (S7) disconnect；By first resistor (R1F), first capacitor (C1)、
Second capacitor (C2F) constitute second-order filter circuit；Utilize the first operational amplifier (A1) duplication second-order filter circuit output electricity
Position, and to third capacitor (C2P) and the 4th capacitor (C3) be pre-charged, and through the 5th switch (S5) obtain output signal out.
5. small area low power consuming clock data recovery circuit according to claim 3, it is characterised in that: second control
SignalControl circuit works in PLL state, specifically:
By first control signal Φ1Switch to second control signalSo that first switch (S1), second switch (S2), third
It switchs (S3), the 4th switch (S4) and the 5th switch (S5) to disconnect, by second control signalControl the 6th switch (S6) with
And the 7th switch (S7) conducting, the second resistance (R1P), first capacitor (C1), third capacitor (C2P), 3rd resistor (R2) and
4th capacitor (C3) three rank filter circuits are constituted, Ji Jing six switchs (S6) obtain output signal out.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910102503.2A CN109889196B (en) | 2019-02-01 | 2019-02-01 | Small-area low-power-consumption clock data recovery circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910102503.2A CN109889196B (en) | 2019-02-01 | 2019-02-01 | Small-area low-power-consumption clock data recovery circuit |
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| CN109889196B CN109889196B (en) | 2023-01-03 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104202048A (en) * | 2014-08-27 | 2014-12-10 | 中国科学技术大学 | Broadband totally-integrated phase-locked loop frequency synthesizer |
| CN105703767A (en) * | 2016-01-13 | 2016-06-22 | 中国科学技术大学先进技术研究院 | High-energy-efficiency low-jitter single loop clock data recovery circuit |
-
2019
- 2019-02-01 CN CN201910102503.2A patent/CN109889196B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104202048A (en) * | 2014-08-27 | 2014-12-10 | 中国科学技术大学 | Broadband totally-integrated phase-locked loop frequency synthesizer |
| CN105703767A (en) * | 2016-01-13 | 2016-06-22 | 中国科学技术大学先进技术研究院 | High-energy-efficiency low-jitter single loop clock data recovery circuit |
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