CN111835346B - Clock data recovery circuit - Google Patents

Clock data recovery circuit Download PDF

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Publication number
CN111835346B
CN111835346B CN202010687275.2A CN202010687275A CN111835346B CN 111835346 B CN111835346 B CN 111835346B CN 202010687275 A CN202010687275 A CN 202010687275A CN 111835346 B CN111835346 B CN 111835346B
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input end
output end
voltage
data
input
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CN111835346A (en
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唐重林
刘寅
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Niuxin Semiconductor Shenzhen Co ltd
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Niuxin Semiconductor Shenzhen Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/087—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using at least two phase detectors or a frequency and phase detector in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0807—Details of the phase-locked loop concerning mainly a recovery circuit for the reference signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The application relates to a clock data recovery circuit and a loop regulating method, wherein the clock data recovery circuit comprises: an LC oscillator for outputting a signal of a predetermined frequency; the first frequency detection module comprises two input ends, the first frequency detection module is used for outputting driving current according to the frequency difference between signals input by the two input ends, and one input end of the first frequency detection module is connected with the output end of the LC oscillator; the second frequency detection module comprises a clock input end and a data input end, and is used for outputting driving current according to the frequency difference between the signal input by the clock input end of the second frequency detection module and the signal input by the data input end of the second frequency detection module. The technical scheme provided by the application can effectively reduce pins of the IC chip and reduce the manufacturing cost of the IC chip.

Description

Clock data recovery circuit
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a clock data recovery circuit.
Background
In a serial communication system, a clock data recovery circuit plays a key role in a received IC chip, which extracts a clock from input serial data through the clock data recovery circuit and performs data recovery.
The precondition for data recovery is to ensure that the input serial data is synchronized with the clock inside the IC chip, and in the related art, the clock data recovery circuit design of the IC chip generally uses an off-chip structure to provide a clock reference source, such as an off-chip crystal oscillator to provide a reference clock, and the off-chip structure is required to provide the reference clock, so that the pins of the IC chip are more, and the manufacturing cost of the IC chip is higher.
Disclosure of Invention
The application aims to provide a clock data recovery circuit, which solves the technical problems of more pins of an IC chip and high manufacturing cost caused by the fact that a clock reference source is required to be provided through an off-chip structure in the prior art.
In order to solve the technical problems, the application adopts the following technical scheme:
according to one aspect of the present application, there is provided a clock data recovery circuit comprising: an LC oscillator for outputting a signal of a predetermined frequency; the first frequency detection module comprises two input ends, the first frequency detection module is used for outputting driving current according to the frequency difference between signals input by the two input ends, and one input end of the first frequency detection module is connected with the output end of the LC oscillator; the second frequency detection module comprises a clock input end and a data input end, and is used for outputting driving current according to the frequency difference between the signal input by the clock input end of the second frequency detection module and the signal input by the data input end of the second frequency detection module, and the clock input end of the second frequency detection module is connected with a serial data signal; the phase locking module comprises a clock input end and a data input end, and is used for outputting driving current according to the phase difference between the signal input by the clock input end of the phase locking module and the signal input by the data input end of the phase locking module, and the data input end of the phase locking module is connected with the serial data signal; the filter is used for outputting driving voltage according to the input driving current, and the input end of the filter is respectively connected with the output end of the first frequency detection module, the output end of the second frequency detection module and the output end of the phase locking module; the voltage-controlled oscillator is used for adjusting the frequency and the phase of an output signal according to the input driving voltage, the input end of the voltage-controlled oscillator is connected with the output end of the filter, and the output end of the voltage-controlled oscillator is respectively connected with the other input end of the first frequency detection module, the data input end of the second frequency detection module and the clock input end of the phase locking module.
In some embodiments, the first frequency detection module comprises: the two input ends of the frequency discriminator are respectively connected with the output end of the LC oscillator and the output end of the voltage-controlled oscillator; the input end of the first charge pump is connected with the output end of the frequency discriminator, and the output end of the first charge pump is connected with the input end of the filter.
In some embodiments, the second frequency detection module comprises: the high-precision frequency detection submodule comprises a clock input end and a data input end, the high-precision frequency detection submodule is used for outputting deviation voltage according to the frequency difference between the signal input by the clock input end of the high-precision frequency detection submodule and the signal input by the data input end of the high-precision frequency detection submodule, the data input end of the high-precision frequency detection submodule is connected with the output end of the voltage-controlled oscillator, and the clock input end of the high-precision frequency detection submodule is connected with the serial data signal; the second charge pump is used for outputting driving current according to the input deviation voltage, the input end of the second charge pump is connected with the output end of the high-precision frequency detection circuit, and the output end of the second charge pump is connected with the input end of the filter.
In some embodiments, the high precision frequency detection submodule includes; the data sampling circuit comprises a clock input end and a data input end, the data sampling circuit is used for outputting a frequency deviation signal according to the frequency difference between a signal input by the clock input end of the data sampling circuit and a signal input by the data input end of the data sampling circuit, the data input end of the data sampling circuit is connected with the output end of the voltage-controlled oscillator, and the clock input end of the data sampling circuit is connected with the serial data signal; the data sampling circuit is used for outputting deviation voltage according to the input frequency deviation signal, the input end of the data processing circuit is connected with the output end of the data sampling circuit, and the output end of the data processing circuit is connected with the input end of the second charge pump.
In some embodiments, the data sampling circuit comprises: the data access end of the first trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the first trigger is connected with the serial data signal, and the non-inverting output end of the first trigger is connected with the input end of the data processing circuit; the data access end of the second trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the second trigger is connected with the serial data signal, and the non-inverting output end of the second trigger is connected with the input end of the data processing circuit; the data access end of the third trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the third trigger is connected with the serial data signal, and the non-inverting output end of the third trigger is connected with the input end of the data processing circuit; the data access end of the fourth trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the fourth trigger is connected with the serial data signal, and the non-inverting output end of the fourth trigger is connected with the input end of the data processing circuit.
In some embodiments, the data processing circuit comprises: the input end of the first exclusive-OR gate circuit is respectively connected with the positive phase output end of the first trigger and the positive phase output end of the third trigger; the input end of the second exclusive-OR gate circuit is respectively connected with the positive phase output end of the second trigger and the positive phase output end of the fourth trigger; the clock input end of the fifth trigger is connected with the output end of the voltage-controlled oscillator, and the data input end of the fifth trigger is connected with the output end of the first exclusive-OR gate circuit; the clock input end of the sixth trigger is connected with the output end of the voltage-controlled oscillator, and the data input end of the sixth trigger is connected with the output end of the second exclusive-OR gate circuit; a clock input end of the seventh trigger is connected with an output end of the voltage-controlled oscillator, and a data input end of the seventh trigger is connected with an output end of the fifth trigger; the clock input end of the eighth trigger is connected with the output end of the voltage-controlled oscillator, and the data input end of the eighth trigger is connected with the output end of the sixth trigger; the input end of the logic gate circuit is respectively connected with the positive phase output end of the fifth trigger, the negative phase output end of the fifth trigger, the positive phase output end of the sixth trigger, the positive phase output end of the seventh trigger, the negative phase output end of the seventh trigger and the positive phase output end of the eighth trigger, and the output end of the logic gate circuit is connected with the input end of the second charge pump.
In some embodiments, the logic gate circuit comprises: the input end of the first AND gate circuit is respectively connected with the inverting output end of the fifth trigger and the non-inverting output end of the seventh trigger; the input end of the NAND gate circuit is respectively connected with the positive phase output end of the sixth trigger and the positive phase output end of the eighth trigger; the input end of the second AND gate circuit is respectively connected with the positive phase output end of the fifth trigger and the negative phase output end of the seventh trigger; the input end of the third AND gate circuit is respectively connected with the output end of the first AND gate circuit and the output end of the NAND gate circuit, and the output end of the third AND gate circuit is connected with the input end of the second charge pump; and the input end of the fourth AND gate circuit is respectively connected with the output end of the second AND gate circuit and the output end of the NAND gate circuit, and the output end of the fourth AND gate circuit is connected with the input end of the second charge pump.
In some embodiments, the phase lock circuit comprises: the data input end of the phase discriminator is connected with the serial data signal, and the clock input end of the phase discriminator is connected with the output end of the voltage-controlled oscillator; and the input end of the third charge pump is connected with the output end of the phase discriminator, and the output end of the third charge pump is connected with the input end of the filter.
In some embodiments, the phase detector comprises: the clock input end of the first latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the first latch is connected with the serial data signal; the clock input end of the second latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the second latch is connected with the serial data signal; the clock input end of the third latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the third latch is connected with the serial data signal; the clock input end of the fourth latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the first latch is connected with the serial data signal; the input end of the third exclusive-OR gate is respectively connected with the positive output end of the first latch and the positive output end of the third latch, and the output end of the third exclusive-OR gate is connected with the input end of the third charge pump; and the input end of the fourth exclusive-OR gate is respectively connected with the positive phase output end of the second latch and the positive phase output end of the fourth latch, and the output end of the fourth exclusive-OR gate is connected with the input end of the third charge pump.
In some embodiments, the first frequency detection module further includes a frequency divider, an input of the frequency divider is connected to an output of the voltage-controlled oscillator, and an output of the frequency divider is connected to an input of the frequency discriminator; the clock data recovery circuit also comprises a deserializer, and the input end of the deserializer is connected with the output end of the phase locking module.
According to an aspect of the present application, there is provided a loop adjustment method applied to the clock data recovery circuit in the above embodiment, the loop adjustment method including: the first frequency detection module adjusts the frequency of the voltage controlled oscillator output signal based on the frequency of the LC oscillator output signal; stopping adjusting the frequency of the voltage controlled oscillator output signal based on the frequency of the LC oscillator output signal if the first frequency detection module detects that the frequency difference between the voltage controlled oscillator output signal and the LC oscillator output signal reaches a predetermined frequency difference threshold; the second frequency detection module adjusts the frequency of the voltage controlled oscillator output signal based on the data transmission rate of the serial data signal; if the second frequency detection module detects that the frequency of the output signal of the voltage-controlled oscillator is consistent with the data transmission rate of the serial data signal, stopping adjusting the frequency of the output signal of the voltage-controlled oscillator based on the data transmission rate of the serial data signal; the phase locking module adjusts the phase of the voltage controlled oscillator output signal based on the phase of the serial data signal; the phase lock module adjusts a phase of the voltage controlled oscillator output signal based on a phase of the serial data signal such that the phase of the voltage controlled oscillator output signal coincides with the phase of the serial data signal.
According to the technical scheme, the application has at least the following advantages and positive effects: by arranging the clock data recovery circuit on the IC chip, the clock synchronization between the inside of the IC chip and the serial data signal outside can be realized under the condition that the IC chip does not provide a reference clock through an off-chip crystal oscillator, pins of the IC chip can be effectively reduced, and the manufacturing cost of the IC chip is reduced.
Drawings
FIG. 1 is a block diagram of a clock data recovery circuit according to an embodiment of the application;
FIG. 2 is a block diagram of a clock data recovery circuit according to another embodiment of the present application;
FIG. 3 is a schematic diagram of a data sampling circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a data processing circuit according to an embodiment of the present application;
fig. 5 is a schematic circuit diagram of a phase detector according to an embodiment of the application;
fig. 6 is a schematic diagram of a loop adjustment method according to an embodiment of the application.
Detailed Description
Exemplary embodiments that embody features and advantages of the present application will be described in detail in the following description. It will be understood that the application is capable of various modifications in various embodiments, all without departing from the scope of the application, and that the description and illustrations herein are intended to be by way of illustration only and not to be construed as limiting the application.
Referring to fig. 1, fig. 1 is a block diagram of a clock data recovery circuit according to an embodiment of the present application, which is generally applied to an IC chip in a serial communication system, and may include an LC oscillator 11, a first frequency detection module 12, a second frequency detection module 13, a phase locking module 14, a filter 15, and a voltage-controlled oscillator 16.
The first frequency detection module 12 comprises two input ends, and one input end of the first frequency detection module 12 is connected with the output end of the LC oscillator 11; the second frequency detection module 13 includes a clock input end and a data input end, the clock input end of the second frequency detection module 13 is connected with a serial data signal 17, and the serial data signal 17 is an external serial data signal of the IC needing clock synchronization; the phase lock module 14 comprises a clock input and a data input, the data input of the phase lock module 14 also being connected to an external serial data signal 17; the input end of the filter 15 is respectively connected with the output end of the first frequency detection module 12, the output end of the second frequency detection module 13 and the output end of the phase locking module 14; the input end of the voltage-controlled oscillator 16 is connected to the output end of the filter 15, and the output end of the voltage-controlled oscillator 16 is respectively connected to the other input end of the first frequency detection module 12, the data input end of the second frequency detection module 13, and the clock data input end of the phase locking module 14.
The LC oscillator 11 may be an LC oscillating circuit inside the IC chip, which may output a signal of a predetermined frequency.
The first frequency detection module 12 is a module for performing frequency detection, and the first frequency detection module 12 may detect a frequency difference between signals input by two input terminals and output a driving current according to the detected frequency difference.
The second frequency detection module 13 is also a module for performing frequency detection, where the second frequency detection module 13 can detect a frequency difference between a signal input by a clock input end and a signal input by a data input end thereof, and output a driving current according to the detected frequency difference, and it should be noted that the second frequency detection module 13 is a frequency detection module with higher accuracy than the first frequency detection module 12.
The phase lock module 14 is a module that can realize phase detection, which can detect a phase difference between a signal input from its clock input terminal and a signal input from its data input terminal, and output a driving current according to the detected phase difference.
The filter 15 converts an input drive current to output a drive voltage corresponding to the input drive current.
The voltage controlled oscillator 16 may adjust the frequency and phase of the output signal according to the input drive voltage.
In one embodiment, LC oscillator 11, first frequency detection module 12, filter 15, and voltage controlled oscillator 16 form a first frequency detection loop. In the first frequency detection loop, the IC chip may control the LC oscillator 11 to generate a reference signal of a predetermined frequency, which is determined according to the data transmission rate of the external serial data signal 17 that is accessed. It should be noted that the frequency of the output signal of the LC oscillator 11 is greatly different from the data transmission rate of the external serial data signal 17, and cannot be used as a clock signal for clock synchronization with the external serial data signal 17 inside the IC chip, and thus adjustment is also required.
In the first frequency detection loop, the LC oscillator 11 inputs the generated signal of a predetermined frequency to one input terminal of the first frequency detection module 12. The input end of the first frequency detection module 12 is also connected to the output signal of the voltage-controlled oscillator 16, the first frequency detection module 12 performs frequency detection on the output signal of the LC oscillator 11 and the output signal of the voltage-controlled oscillator 16, determines a frequency difference between the two signals, outputs a driving current according to the detected frequency difference, the first frequency detection module 12 outputs the driving current to the filter 15, generates a corresponding output voltage after conversion processing by the filter 15, and the filter 15 inputs the output voltage to the voltage-controlled oscillator 16, so that the frequency of the output signal of the voltage-controlled oscillator 16 is regulated, and further, a frequency error between the frequency of the output signal of the voltage-controlled oscillator 16 and the data transmission rate of the external serial data signal 17 is within a predetermined error range, so that clock synchronization of the serial data signal 17 inside and outside the IC chip is facilitated.
In the first frequency detection loop, when the frequency difference between the frequency of the output signal of the voltage-controlled oscillator 16 and the data transmission rate of the serial data signal 17 is within a predetermined error range, the frequency of the output signal of the voltage-controlled oscillator 16 is stopped from being adjusted based on the frequency of the output signal of the LC oscillator 11, and locking of the first frequency detection loop is achieved. After the first frequency detection loop is locked, the frequency of the voltage controlled oscillator 16 output signal remains unchanged. The predetermined error range may be whether the ratio of the frequency difference between the frequency of the voltage controlled oscillator output signal and the data transmission rate of the serial data signal 17 to the data transmission rate of the serial data signal 17 is less than or equal to a predetermined value, such as less than or equal to 10%, which is not limited herein.
In one embodiment, the second frequency detection module 13, the filter 15 and the voltage controlled oscillator 16 form a second frequency detection loop that needs to be turned on when the first frequency detection loop is in a locked state. In the second frequency detection loop, the clock input of the second frequency detection module 13 is connected to an external serial data signal 17, and the data input is connected to an output signal of the voltage-controlled oscillator 16 when the first frequency detection loop is in a locked state. The second frequency detection module 13 performs frequency detection on the input output signal of the voltage-controlled oscillator 16 and the serial data signal 17, determines a frequency difference between the two signals, outputs a driving current according to the detected frequency difference, the second frequency detection module 13 outputs the driving current to the filter 15, generates a corresponding output voltage after conversion processing by the filter 15, and the filter 15 inputs the output voltage into the voltage-controlled oscillator 16 to realize frequency adjustment of the output signal of the voltage-controlled oscillator 16 so as to realize higher-precision adjustment of the frequency of the output signal of the voltage-controlled oscillator 16, so that the frequency of the output signal of the voltage-controlled oscillator 16 is consistent with the data transmission rate of the external serial data signal 17.
In the second frequency detection loop, when the frequency of the output signal of the voltage-controlled oscillator 16 is consistent with the data transmission rate of the external serial data signal 17, the frequency of the output signal of the voltage-controlled oscillator 16 is stopped from being adjusted based on the data transmission rate of the external serial data signal 17, so that the second frequency detection loop is locked. After the second frequency detection loop is locked, the frequency of the output signal of the voltage-controlled oscillator 16 is consistent with the data transmission rate of the serial data, and the frequency of the output signal of the voltage-controlled oscillator 16 remains unchanged.
In one embodiment, the phase lock module 14, the filter 15 and the voltage controlled oscillator 16 form a phase lock loop that needs to be turned on when the second frequency detection loop is in a locked state. In the phase locked loop, the clock input of the phase lock module 14 is connected to the output signal of the voltage controlled oscillator 16 when the second frequency detection loop is in the locked state, and the data input is connected to the external serial data signal 17. The phase locking module 14 performs phase detection on the input output signal of the voltage-controlled oscillator 16 and the serial data signal 17, determines a phase difference value between the two signals, outputs a driving current according to the detected phase difference value, the phase locking module 14 outputs the driving current to the filter 15, generates a corresponding output voltage after conversion processing by the filter 15, and the filter 15 inputs the output voltage to the voltage-controlled oscillator 16, so that the phase of the output signal of the voltage-controlled oscillator 16 is adjusted, and the phase of the output signal of the voltage-controlled oscillator 16 is consistent with the phase of the external serial data signal 17.
In the phase lock loop, when the phase of the output signal of the voltage controlled oscillator 16 matches the phase of the external serial data signal 17, the phase of the serial data signal 17 is stopped to adjust the phase of the output signal of the voltage controlled oscillator 16, thereby realizing the lock of the phase lock loop. After the phase locking loop is locked, the frequency of the output signal of the voltage-controlled oscillator 16 is consistent with the data transmission rate of the serial data, and the phase of the output signal of the voltage-controlled oscillator 16 is also consistent with the phase of the serial data signal 17, so that clock synchronization can be performed between the inside of the IC chip and the serial data signal 17 outside of the IC chip, and the clock and data recovery system function of the IC chip can be realized conveniently.
As can be seen from the above, by providing the above clock data recovery circuit on the IC chip, clock synchronization between the inside of the IC chip and the external serial data signal 17 can be performed even if the IC chip does not provide the reference clock through the off-chip crystal oscillator, so that pins of the IC chip can be effectively reduced, and manufacturing cost of the IC chip can be reduced.
Referring to fig. 2, fig. 2 is a schematic diagram of a clock data recovery circuit according to another embodiment of the present application, in which the first frequency detection module 12 may include a frequency discriminator 121 and a first charge pump 122, two input terminals of the frequency discriminator 121 are respectively connected to the output terminal of the LC oscillator 11 and the output terminal of the voltage-controlled oscillator 16, an input terminal of the first charge pump 122 is connected to the output terminal of the frequency discriminator 121, and an output terminal of the first charge pump 122 is connected to the input terminal of the filter 15.
The frequency discriminator 121 performs frequency detection on the output signal of the LC oscillator 11 and the output signal of the voltage-controlled oscillator 16, determines a frequency difference between the two input signals, and outputs a corresponding offset voltage according to the detected frequency difference, and the frequency discriminator 121 outputs the corresponding offset voltage to the first charge pump 122. The first charge pump 122 may generate a driving current corresponding to the offset voltage according to the input offset voltage, the first charge pump 122 may input the generated offset voltage to the filter 15, generate a driving voltage corresponding to the driving current after performing conversion processing by the filter 15, and the filter 15 may input the driving voltage to the voltage-controlled oscillator 16, thereby implementing frequency adjustment of an output signal of the voltage-controlled oscillator 16.
Optionally, the first frequency detection module 12 further includes a frequency divider 123, an input end of the frequency divider 123 is connected to an output end of the voltage-controlled oscillator 16, and an output end of the frequency divider 123 is connected to an input end of the frequency discriminator 121, where the frequency divider 123 is configured to perform a frequency-reducing process when the frequency of the output signal of the LC oscillator 11 is relatively high, so that the frequency of the output signal of the LC oscillator 11 can meet a requirement that the data transmission rate of the serial data signal 17 is in the same order of magnitude, so that the clock data recovery circuit performs clock synchronization.
Optionally, the clock data recovery circuit further includes a deserializer 18, an input end of the deserializer 18 is connected to an output end of the phase locking circuit 14, after the IC chip realizes clock synchronization with the external serial data signal 17 through the clock data recovery circuit, the IC chip can correctly sample data and clock corresponding to the external serial data signal 17, and then the data and clock are input to the deserializer, and serial-to-parallel conversion is completed by the deserializer, so as to realize a system function of clock and data recovery of the IC chip.
Still referring to fig. 2, the second frequency detection module 13 in the present embodiment includes a high-precision frequency detection sub-module 131 and a second charge pump 132. The high precision frequency detection sub-module 131 comprises a clock input connected to the output of the voltage controlled oscillator 16 and a data input connected to the serial data signal 17. An input end of the second charge pump 132 is connected to an output end of the high-precision frequency detection circuit 131, and an output end of the second charge pump 132 is connected to an input end of the filter 15.
The high-precision frequency detection sub-module 131 is configured to perform frequency detection on an output signal of the voltage-controlled oscillator 16 input to the data input terminal of the voltage-controlled oscillator and the serial data signal 17 input to the clock input terminal of the voltage-controlled oscillator, determine a frequency difference between the two signals, and output a corresponding offset voltage according to the detected frequency difference, where the high-precision frequency detection sub-module 131 outputs the corresponding offset voltage to the second charge pump 132, the second charge pump 132 can generate a driving current corresponding to the offset voltage according to the input offset voltage, the second charge pump 132 inputs the generated offset voltage to the filter 15, generates an output voltage corresponding to the driving current after performing conversion processing by the filter 15, and the filter 15 inputs the output voltage to the voltage-controlled oscillator 16, thereby implementing adjustment on a frequency range of the output signal of the voltage-controlled oscillator 16.
Optionally, the high-precision frequency detection sub-module 131 includes a data sampling circuit, where the data sampling circuit includes a clock input end and a data input end, the data input end of the data sampling circuit is connected to the output end of the voltage-controlled oscillator 16, and the clock input end of the data sampling circuit is connected to the serial data signal 17; the input end of the data processing circuit is connected with the output end of the data sampling circuit, and the output end is connected with the input end of the second charge pump 132.
The data sampling circuit is a circuit that outputs a frequency deviation signal according to the frequency difference between the signal input from its clock input terminal and the signal input from its data input terminal, and in this embodiment, the data sampling circuit is configured to output a frequency deviation signal according to the frequency difference between the serial data signal 17 input from its clock input terminal and the input signal input from its data input terminal to the voltage-controlled oscillator 16, and the data sampling circuit inputs the output frequency deviation signal to the data processing circuit.
The data sampling circuit is used as a circuit for outputting a bias voltage according to the input frequency bias signal, and in this embodiment, the data sampling circuit is used for outputting the bias voltage according to the frequency bias signal input by the data sampling circuit so as to generate a bias voltage corresponding to the frequency difference, and then the bias voltage is conveniently input to the second charge pump 132 for processing, so as to realize adjustment of the voltage-controlled oscillator 16.
Fig. 3 is a circuit diagram of a data sampling circuit according to an embodiment of the application, and fig. 4 is a circuit diagram of a data processing circuit according to an embodiment of the application.
Referring to fig. 2 to 3, in one embodiment of the present application, the data sampling circuit includes a first flip-flop Q1, a second flip-flop Q2, a third flip-flop Q3, a fourth flip-flop Q4, a first exclusive-or circuit, and a second exclusive-or circuit.
The data access terminal D of the first flip-flop Q1 is used for connecting to the output terminal of the voltage-controlled oscillator 16, and the clock access terminal CK of the first flip-flop Q1 accesses the external serial data signal 17. The data access terminal D of the second flip-flop Q2 is used for connecting to the output terminal of the voltage-controlled oscillator 16, and the clock access terminal CK of the second flip-flop Q2 accesses the external serial data signal 17. The data access terminal D of the third flip-flop Q3 is used for connecting to the output terminal of the voltage-controlled oscillator 16, and the clock access terminal CK of the third flip-flop Q3 accesses the external serial data signal 17. The data access terminal D of the fourth flip-flop Q4 is used for connecting to the output terminal of the voltage-controlled oscillator 16, and the clock access terminal CK of the fourth flip-flop Q4 accesses the external serial data signal 17. The positive phase output end Q of the first trigger Q1, the positive phase output end Q of the second trigger Q2, the positive phase output end Q of the third trigger Q3 and the positive phase output end Q of the fourth trigger Q4 are respectively connected with the input end of the data processing circuit.
When the frequency detection is performed on the output signal of the voltage-controlled oscillator 16 input by the data sampling circuit and the serial data signal 17 input by the clock, the first flip-flop Q1 may be connected to the output signals of which the phases are 0 ° and 180 ° output by the output of the voltage-controlled oscillator 16, the second flip-flop Q2 may be connected to the output signals of which the phases are 45 ° and 225 ° output by the output of the voltage-controlled oscillator 16, the third flip-flop Q3 may be connected to the output signals of which the phases are 90 ° and 270 ° output by the output of the voltage-controlled oscillator 16, and the fourth flip-flop Q4 may be connected to the output signals of which the phases are 135 ° and 315 ° output by the output of the voltage-controlled oscillator 16. By forming four state intervals by adjacent phase intervals among the input signals of the four flip-flops Q1, Q2, Q3, and Q4, the first flip-flop Q1, Q2, Q3, and Q4 will sample the serial data signal 17 when it is at a rising edge, and when the first rising edge of the serial data signal 17 is sampled to the state interval 1 and the second rising edge is sampled to the state interval 2, it can be determined that the frequency of the output signal of the voltage-controlled oscillator 16 is higher than the data transmission rate of the serial data signal 17, and if the second rising edge is sampled to the state interval 4, it can be determined that the frequency of the output signal of the voltage-controlled oscillator 16 is lower than the data transmission rate of the serial data signal 17, thereby determining that the frequency between the frequency of the output signal of the voltage-controlled oscillator 16 and the data transmission rate of the serial data signal 17 is higher.
Referring to fig. 2 to 4, in one embodiment of the present application, the data processing circuit includes a first exclusive or gate circuit, a second exclusive or gate circuit, a fifth flip-flop Q5, a sixth flip-flop Q6, a seventh flip-flop Q7, an eighth flip-flop Q8, and a logic gate circuit.
The input end of the first exclusive-OR gate circuit is respectively connected with the positive phase output end Q of the first trigger Q1 and the positive phase output end Q of the third trigger Q3. The input end of the second exclusive-or gate circuit is respectively connected with the positive phase output end Q of the second trigger Q3 and the positive phase output end Q of the fourth trigger Q4.
The clock input CK of the fifth flip-flop Q5 is connected to the output of the voltage-controlled oscillator 16, and the data input D of the fifth flip-flop Q5 is connected to the output of the first exclusive-or circuit. The clock input CK of the sixth flip-flop Q6 is connected to the output of the voltage controlled oscillator 16, and the data input D of the sixth flip-flop Q6 is connected to the output of the second exclusive or circuit. The clock input CK of the seventh flip-flop Q7 is connected to the output of the voltage controlled oscillator 16, and the data input D of the seventh flip-flop Q7 is connected to the output Q of the fifth flip-flop Q5. The clock input CK of the eighth flip-flop Q8 is connected to the output of the voltage controlled oscillator 16, and the data input D of the eighth flip-flop Q8 is connected to the output Q of the sixth flip-flop Q6. The clock input CK of the fifth flip-flop Q5, the clock input CK of the sixth flip-flop Q6, the clock input CK of the seventh flip-flop Q5, and the clock input CK of the eighth flip-flop Q8 may receive signals of the same phase, such as output signals with phases of 0 ° all outputted from the output terminal of the voltage-controlled oscillator 16.
The input end of the logic gate circuit is respectively connected with the positive phase output end Q of the fifth trigger Q5, the negative phase output end Q of the fifth trigger, the positive phase output end Q of the sixth trigger Q6, the positive phase output end Q of the seventh trigger Q7, the negative phase output end Q of the seventh trigger Q7 and the positive phase output end Q of the eighth trigger Q8, and the output end of the logic gate circuit is connected with the input end of the second charge pump 132.
Optionally, the logic gate circuit includes a first and gate circuit, a nand gate circuit, a second and gate circuit, a third and gate circuit, and a fourth and gate circuit.
The input end of the first AND gate circuit is respectively connected with the inverting output end Q of the fifth trigger Q5 and the non-inverting output end Q of the seventh trigger Q7.
The input end of the NAND gate circuit is respectively connected with the output end of the sixth trigger Q6 and the output end Q of the eighth trigger Q8.
The input end of the second AND gate circuit is respectively connected with the non-inverting output end Q of the fifth trigger Q5 and the inverting output end Q of the seventh trigger Q7.
The input end of the third AND gate circuit is respectively connected with the output end of the first AND gate circuit and the output end of the NAND gate circuit, and the output end of the third AND gate circuit is connected with the input end of the second charge pump 132; the input end of the fourth AND gate circuit is respectively connected with the output end of the second AND gate circuit and the output end of the NAND gate circuit, and the output end is connected with the input end of the second charge pump 132.
For the frequency detection result in the data sampling circuit, delay processing and logic processing are required to be performed on the frequency detection result through the data processing circuit so as to generate a deviation voltage for determining to drive the voltage-controlled oscillator to adjust. If the third and circuit in the data sampling circuit outputs the high indication signal p_up, the frequency of the output signal of the voltage-controlled oscillator 16 needs to be increased, and if the fourth and circuit in the data sampling circuit outputs the high indication signal p_dn, the frequency of the output signal of the voltage-controlled oscillator 16 needs to be decreased.
According to the technical schemes of the embodiments shown in fig. 2 to fig. 4, the second frequency detection module 13 can realize high-precision adjustment of the frequency of the output signal of the voltage-controlled oscillator 16, so that the frequency of the output signal of the voltage-controlled oscillator 16 is consistent with the data transmission rate of the external serial data signal, and further clock synchronization between the internal part of the IC chip and the external serial data signal is facilitated.
Still referring to fig. 2, the phase lock circuit 14 includes a phase detector 141 and a third charge pump 142, wherein a data input terminal of the phase detector 141 is connected to the external serial data signal 17, and a clock input terminal of the phase detector 141 is connected to an output terminal of the voltage-controlled oscillator 16; an input terminal of the third charge pump 142 is connected to an output terminal of the phase detector 141, and an output terminal of the third charge pump 142 is connected to an input terminal of the filter 15.
The phase detector 141 performs frequency detection on the external serial data signal and the output signal of the voltage-controlled oscillator 16, determines a phase difference value between the two signals, and outputs a corresponding offset voltage according to the detected phase difference value, and the frequency detector 121 outputs the corresponding offset voltage to the third charge pump 142. The third charge pump 142 may generate a driving current corresponding to the offset voltage according to the input offset voltage, the third charge pump 142 may input the generated offset voltage to the filter 15, generate a driving voltage corresponding to the driving current after performing conversion processing by the filter 15, and the filter 15 may input the driving voltage to the voltage-controlled oscillator 16, thereby implementing phase adjustment of an output signal of the voltage-controlled oscillator 16.
Fig. 5 is a schematic circuit diagram of a phase detector according to an embodiment of the present application, referring to fig. 5, in one embodiment, the phase detector 141 may include a first latch L1, a second latch L2, a third latch L3, a fourth latch L4, a third exclusive or gate, and a fourth exclusive or gate.
The clock input CK of the first latch L1 is connected to the output of the voltage controlled oscillator 16, and the data input D of the first latch L1 is connected to the external serial data signal 17. The clock input CK of the second latch L2 is connected to the output of the voltage controlled oscillator 16, and the data input D of the second latch L2 is connected to the external serial data signal 17. The clock input CK of the third latch L3 is connected to the output of the voltage controlled oscillator 16, and the data input D of the third latch L3 is connected to the external serial data signal 17. The clock input CK of the fourth latch L4 is connected to the output of the voltage controlled oscillator 16, and the data input D of the fourth latch L4 is connected to the external serial data signal 17. The input end of the third exclusive-or gate circuit is connected to the positive output end Q of the first latch L1 and the positive output end Q of the third latch L3, respectively, and the output end of the third exclusive-or gate circuit is connected to the input end of the third charge pump 142. The input end of the fourth exclusive-or circuit is connected to the positive output end Q of the second latch L2 and the positive output end Q of the fourth latch L4, respectively, and the output end of the fourth exclusive-or circuit is connected to the input end of the third charge pump 142.
When the phase detector 141 detects the phase of the output signal of the voltage controlled oscillator 16 and the serial data signal 17 of the data input terminal thereof, the clock access terminal CK of the first latch L1 and the clock access terminal CK of the third latch L3 need to be connected to the output signal of the output terminal of the voltage controlled oscillator 16, wherein the phase is 0 ° and the frequency is half of the data transmission rate of the external serial data signal 17; the clock access terminal CK of the second latch L2 and the clock access terminal CK of the fourth latch L4 need to be connected to an output signal of 180 ° phase and half the data transmission rate of the external serial data signal 17. The data access terminal D of the first latch L1, the data access terminal D of the second latch L2, the data access terminal D of the third latch L3, and the data access terminal D of the fourth latch L4 are connected to the external serial data signal 17. The input end of the third exclusive-or gate circuit is respectively connected with the positive phase output end Q of the first latch L1 and the positive phase output end Q of the third latch L3, and the input end of the fourth exclusive-or gate circuit is also respectively connected with the positive phase output end Q of the second latch L2 and the positive phase output end Q of the fourth latch L4.
The phase sampling of the external serial data signal 17 is realized by the output signal with half the data transmission rate of the external serial data signal 17 input by the voltage-controlled oscillator 16 to the first latch L1, the second latch L2, the third latch L3 and the fourth latch L4, if the indication signal p_up output by the output end of the third exclusive-or circuit is high, the phase of the output signal of the voltage-controlled oscillator 16 is greater than the phase of the external serial data signal 17, and the phase of the output signal of the voltage-controlled oscillator 16 needs to be adjusted backwards; if the indication signal p_dn output by the output end of the fourth exclusive or gate circuit is high, the phase of the output signal of the voltage-controlled oscillator 16 is smaller than the phase of the external serial data signal 17, and the phase of the output signal of the voltage-controlled oscillator 16 needs to be adjusted forward, so that the phase of the output signal of the voltage-controlled oscillator 16 is adjusted with high precision, and the phase of the output signal of the voltage-controlled oscillator 16 is consistent with the phase of the external serial data signal 17.
Fig. 6 is a schematic diagram of a loop adjustment method according to an embodiment of the present application, where the loop adjustment method according to the present application is applied to the clock data recovery circuit according to any one of the foregoing embodiments, and the loop adjustment method according to the present application includes steps S610 to S650, which are described in detail below.
In step S610, the first frequency detection module adjusts the frequency of the voltage controlled oscillator output signal based on the frequency of the LC oscillator output signal.
In one embodiment, the IC chip forms a first frequency detection loop according to the LC oscillator 11, the first frequency detection module 12, the filter 15 and the voltage controlled oscillator 16, in which the frequency of the output signal of the voltage controlled oscillator 16 is adjusted by the first frequency detection module 12.
In step S620, if the first frequency detection module detects that the frequency difference between the voltage controlled oscillator output signal and the LC oscillator output signal reaches the predetermined frequency difference threshold, the adjusting of the frequency of the voltage controlled oscillator output signal based on the frequency of the LC oscillator output signal is stopped.
In one embodiment, locking the first frequency detection loop is achieved when the frequency difference between the frequency of the voltage controlled oscillator 16 output signal and the data transfer rate of the serial data signal 17 is within a predetermined error range. After the first frequency detection loop is locked, the frequency of the voltage controlled oscillator 16 output signal remains unchanged.
In step S630, the second frequency detection module adjusts the frequency of the voltage controlled oscillator output signal based on the data transmission rate of the serial data signal.
In one embodiment, the second frequency detection module 13, the filter 15 and the voltage controlled oscillator 16 form a second frequency detection loop, which needs to be turned on when the first frequency detection loop is in a locked state, and the second frequency detection loop adjusts the frequency of the output signal of the voltage controlled oscillator 16 based on the data transmission rate of the serial data signal.
In step S640, if the second frequency detection module detects that the frequency of the output signal of the voltage-controlled oscillator is consistent with the data transmission rate of the serial data signal, the adjusting of the frequency of the output signal of the voltage-controlled oscillator based on the data transmission rate of the serial data signal is stopped.
In one embodiment, when the second frequency detection module detects that the frequency of the output signal of the voltage controlled oscillator 16 is consistent with the data transmission rate of the external serial data signal 17, the adjusting of the frequency of the output signal of the voltage controlled oscillator 16 based on the data transmission rate of the external serial data signal 17 is stopped, so as to lock the second frequency detection loop. After the second frequency detection loop is locked, the frequency of the output signal of the voltage-controlled oscillator 16 is consistent with the data transmission rate of the serial data, and the frequency of the output signal of the voltage-controlled oscillator 16 remains unchanged.
In step S650, the phase locking module adjusts the phase of the voltage controlled oscillator output signal based on the phase of the serial data signal so that the phase of the voltage controlled oscillator output signal coincides with the phase of the serial data signal.
In one embodiment, phase lock module 14, filter 15, and voltage controlled oscillator 16 form a phase lock loop that needs to be turned on when the second frequency detection loop is in a locked state. When the phase locking module 14 detects that the phase of the output signal of the voltage-controlled oscillator 16 is consistent with the phase of the external serial data signal 17, the phase of the serial data signal 17 is stopped to adjust the phase of the output signal of the voltage-controlled oscillator 16, so that the phase locking loop is locked. After the phase lock loop is locked, the frequency of the output signal of the voltage controlled oscillator 16 is consistent with the data transmission rate of the serial data, and the phase of the output signal of the voltage controlled oscillator 16 is also consistent with the phase of the serial data signal 17. It should be noted that the loop adjustment method in the present embodiment is a dynamic adjustment process, and when the serial data signal 17 inputted from the outside changes, the loop adjustment method starts to be executed so that the inside of the IC chip can be clock-synchronized with the serial data signal 17 from the outside.
In the technical solution of the embodiment shown in fig. 6, the IC chip performs adjustment control on the clock and data recovery function of the IC chip by using the above method, after the adjustment is completed, the internal of the IC chip can perform clock synchronization with the external serial data signal 17, so as to implement the clock and data recovery system function of the IC chip, and further, under the condition that the IC chip does not provide the reference clock by using the off-chip crystal oscillator, the internal of the IC chip can perform clock synchronization with the external serial data signal 17, so that pins of the IC chip can be effectively reduced, and manufacturing cost of the IC chip is reduced.
While the application has been described with reference to several exemplary embodiments, it is to be understood that the terminology used is intended to be in the nature of words of description and of limitation. As the present application may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims (9)

1. A clock data recovery circuit, comprising:
an LC oscillator for outputting a signal of a predetermined frequency;
the first frequency detection module comprises two input ends, the first frequency detection module is used for outputting driving current according to the frequency difference between signals input by the two input ends, and one input end of the first frequency detection module is connected with the output end of the LC oscillator;
the second frequency detection module comprises a clock input end and a data input end, and is used for outputting driving current according to the frequency difference between the signal input by the clock input end of the second frequency detection module and the signal input by the data input end of the second frequency detection module, and the clock input end of the second frequency detection module is connected with a serial data signal;
the phase locking module comprises a clock input end and a data input end, and is used for outputting driving current according to the phase difference between the signal input by the clock input end of the phase locking module and the signal input by the data input end of the phase locking module, and the data input end of the phase locking module is connected with the serial data signal;
The filter is used for outputting driving voltage according to the input driving current, and the input end of the filter is respectively connected with the output end of the first frequency detection module, the output end of the second frequency detection module and the output end of the phase locking module;
the voltage-controlled oscillator is used for adjusting the frequency and the phase of an output signal according to the input driving voltage, the input end of the voltage-controlled oscillator is connected with the output end of the filter, and the output end of the voltage-controlled oscillator is respectively connected with the other input end of the first frequency detection module, the data input end of the second frequency detection module and the clock input end of the phase locking module;
wherein the first frequency detection module includes:
the two input ends of the frequency discriminator are respectively connected with the output end of the LC oscillator and the output end of the voltage-controlled oscillator;
the input end of the first charge pump is connected with the output end of the frequency discriminator, and the output end of the first charge pump is connected with the input end of the filter;
the second frequency detection module includes:
the high-precision frequency detection submodule comprises a clock input end and a data input end, the high-precision frequency detection submodule is used for outputting deviation voltage according to the frequency difference between the signal input by the clock input end of the high-precision frequency detection submodule and the signal input by the data input end of the high-precision frequency detection submodule, the data input end of the high-precision frequency detection submodule is connected with the output end of the voltage-controlled oscillator, and the clock input end of the high-precision frequency detection submodule is connected with the serial data signal;
The second charge pump is used for outputting driving current according to the input deviation voltage, the input end of the second charge pump is connected with the output end of the high-precision frequency detection submodule, and the output end of the second charge pump is connected with the input end of the filter.
2. The clock data recovery circuit of claim 1, wherein the high precision frequency detection submodule comprises;
the data sampling circuit comprises a clock input end and a data input end, the data sampling circuit is used for outputting a frequency deviation signal according to the frequency difference between a signal input by the clock input end of the data sampling circuit and a signal input by the data input end of the data sampling circuit, the data input end of the data sampling circuit is connected with the output end of the voltage-controlled oscillator, and the clock input end of the data sampling circuit is connected with the serial data signal;
the data sampling circuit is used for outputting deviation voltage according to the input frequency deviation signal, the input end of the data processing circuit is connected with the output end of the data sampling circuit, and the output end of the data processing circuit is connected with the input end of the second charge pump.
3. The clock data recovery circuit of claim 2, wherein the data sampling circuit comprises:
the data access end of the first trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the first trigger is connected with the serial data signal, and the non-inverting output end of the first trigger is connected with the input end of the data processing circuit;
the data access end of the second trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the second trigger is connected with the serial data signal, and the non-inverting output end of the second trigger is connected with the input end of the data processing circuit;
the data access end of the third trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the third trigger is connected with the serial data signal, and the non-inverting output end of the third trigger is connected with the input end of the data processing circuit;
the data access end of the fourth trigger is connected with the output end of the voltage-controlled oscillator, the clock access end of the fourth trigger is connected with the serial data signal, and the non-inverting output end of the fourth trigger is connected with the input end of the data processing circuit.
4. A clock data recovery circuit according to claim 3, wherein the data processing circuit comprises:
the input end of the first exclusive-OR gate circuit is respectively connected with the positive phase output end of the first trigger and the positive phase output end of the third trigger;
the input end of the second exclusive-OR gate circuit is respectively connected with the positive phase output end of the second trigger and the positive phase output end of the fourth trigger;
the clock input end of the fifth trigger is connected with the output end of the voltage-controlled oscillator, and the data input end of the fifth trigger is connected with the output end of the first exclusive-OR gate circuit;
the clock input end of the sixth trigger is connected with the output end of the voltage-controlled oscillator, and the data input end of the sixth trigger is connected with the output end of the second exclusive-OR gate circuit;
a clock input end of the seventh trigger is connected with an output end of the voltage-controlled oscillator, and a data input end of the seventh trigger is connected with an output end of the fifth trigger;
the clock input end of the eighth trigger is connected with the output end of the voltage-controlled oscillator, and the data input end of the eighth trigger is connected with the output end of the sixth trigger;
The input end of the logic gate circuit is respectively connected with the positive phase output end of the fifth trigger, the negative phase output end of the fifth trigger, the positive phase output end of the sixth trigger, the positive phase output end of the seventh trigger, the negative phase output end of the seventh trigger and the positive phase output end of the eighth trigger, and the output end of the logic gate circuit is connected with the input end of the second charge pump.
5. The clock data recovery circuit of claim 4, wherein the logic gate circuit comprises:
the input end of the first AND gate circuit is respectively connected with the inverting output end of the fifth trigger and the non-inverting output end of the seventh trigger;
the input end of the NAND gate circuit is respectively connected with the positive phase output end of the sixth trigger and the positive phase output end of the eighth trigger;
the input end of the second AND gate circuit is respectively connected with the positive phase output end of the fifth trigger and the negative phase output end of the seventh trigger;
the input end of the third AND gate circuit is respectively connected with the output end of the first AND gate circuit and the output end of the NAND gate circuit, and the output end of the third AND gate circuit is connected with the input end of the second charge pump;
And the input end of the fourth AND gate circuit is respectively connected with the output end of the second AND gate circuit and the output end of the NAND gate circuit, and the output end of the fourth AND gate circuit is connected with the input end of the second charge pump.
6. The clock data recovery circuit of claim 1, wherein the phase lock circuit comprises:
the data input end of the phase discriminator is connected with the serial data signal, and the clock input end of the phase discriminator is connected with the output end of the voltage-controlled oscillator;
and the input end of the third charge pump is connected with the output end of the phase discriminator, and the output end of the third charge pump is connected with the input end of the filter.
7. The clock data recovery circuit of claim 6, wherein the phase detector comprises:
the clock input end of the first latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the first latch is connected with the serial data signal;
the clock input end of the second latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the second latch is connected with the serial data signal;
The clock input end of the third latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the third latch is connected with the serial data signal;
the clock input end of the fourth latch is connected with the output end of the voltage-controlled oscillator, and the data input end of the first latch is connected with the serial data signal;
the input end of the third exclusive-OR gate is respectively connected with the positive output end of the first latch and the positive output end of the third latch, and the output end of the third exclusive-OR gate is connected with the input end of the third charge pump;
and the input end of the fourth exclusive-OR gate is respectively connected with the positive phase output end of the second latch and the positive phase output end of the fourth latch, and the output end of the fourth exclusive-OR gate is connected with the input end of the third charge pump.
8. The clock data recovery circuit of claim 1, wherein the first frequency detection module further comprises a frequency divider, an input of the frequency divider is connected to an output of the voltage controlled oscillator, and an output of the frequency divider is connected to an input of the frequency discriminator;
The clock data recovery circuit also comprises a deserializer, and the input end of the deserializer is connected with the output end of the phase locking module.
9. A loop adjustment method applied to the clock data recovery circuit according to any one of claims 1 to 8, characterized in that the loop adjustment method comprises:
the first frequency detection module adjusts the frequency of the voltage controlled oscillator output signal based on the frequency of the LC oscillator output signal;
stopping adjusting the frequency of the voltage controlled oscillator output signal based on the frequency of the LC oscillator output signal if the first frequency detection module detects that the frequency difference between the voltage controlled oscillator output signal and the LC oscillator output signal reaches a predetermined frequency difference threshold;
the second frequency detection module adjusts the frequency of the voltage controlled oscillator output signal based on the data transmission rate of the serial data signal;
if the second frequency detection module detects that the frequency of the output signal of the voltage-controlled oscillator is consistent with the data transmission rate of the serial data signal, stopping adjusting the frequency of the output signal of the voltage-controlled oscillator based on the data transmission rate of the serial data signal;
The phase lock module adjusts a phase of the voltage controlled oscillator output signal based on a phase of the serial data signal such that the phase of the voltage controlled oscillator output signal coincides with the phase of the serial data signal.
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