CN105633052B - 封装结构及其制法 - Google Patents

封装结构及其制法 Download PDF

Info

Publication number
CN105633052B
CN105633052B CN201410603698.6A CN201410603698A CN105633052B CN 105633052 B CN105633052 B CN 105633052B CN 201410603698 A CN201410603698 A CN 201410603698A CN 105633052 B CN105633052 B CN 105633052B
Authority
CN
China
Prior art keywords
protective layer
insulating protective
encapsulating structure
layer
dielectric substance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410603698.6A
Other languages
English (en)
Other versions
CN105633052A (zh
Inventor
白裕呈
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siliconware Precision Industries Co Ltd
Original Assignee
Siliconware Precision Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siliconware Precision Industries Co Ltd filed Critical Siliconware Precision Industries Co Ltd
Publication of CN105633052A publication Critical patent/CN105633052A/zh
Application granted granted Critical
Publication of CN105633052B publication Critical patent/CN105633052B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3178—Coating or filling in grooves made in the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Geometry (AREA)
  • Laminated Bodies (AREA)

Abstract

一种封装结构及其制法，该制法包括：于一载板上形成第一绝缘保护层；于该第一绝缘保护层上形成具有相对的第一表面与第二表面的介电体，该介电体嵌埋有线路层与形成于该线路层上的多个导电柱；于该介电体的第二表面形成第二绝缘保护层，其中，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度大于250℃；以及移除该载板，所以藉由使用玻璃转移温度大于该介电体的第一或第二绝缘保护层，因而无须以支撑件做辅助，仍具有较佳的强度，得以避免封装结构发生翘曲的缺失。

Description

封装结构及其制法
技术领域
本发明涉及一种封装结构及其制法，尤指一种供半导体封装的线路封装结构及其制法。
背景技术
随着电子产业的蓬勃发展，许多高阶电子产品都逐渐朝往轻、薄、短、小等高集积度方向发展，且随着封装技术的演进，晶片的封装技术也越来越多样化，半导体封装件的尺寸或体积也随之不断缩小，藉以使该半导体封装件达到轻薄短小的目的。
一般封装结构的制法如图1A至图1F所示者为现有的封装结构的制法的剖视图。
如图1A所示，于一载板10上形成线路层11。
再于部分该线路层11上形成导电柱13，如图1B所示。
接着，形成具有相对的第一表面12a与第二表面12b的介电体12，使该导电柱13与线路层11嵌埋于其中，如图1C所示。
如图1D所示，移除部份该载板10，并保留部分该载板10’以作为支撑之用，并于该介电体12的第一表面12a上设置并电性连接半导体元件40。
如图1E至图1F所示，以模具90于由该介电体12的第一表面12a与该模具90所构成的容置空间900中灌注封装胶体42，而得到如图1F的经封装的现有封装结构1。
上述封装结构的制法中未避免在温度较高的制程中，该封装结构发生翘曲因而藉由所保留的部分该载板10’作为支撑。
然而，通常而言，该载板10’(如，钢板)因加工方式的限制，厚度最低仅能达到200微米(μm)，即便将模具90的模穴拉成与该载板10’齐平，如图1E’所示，所形成的封装胶体42的厚度h1仍无法突破200微米厚度的限制，遂使整体封装结构的厚度难以降低。
随着电子产业朝轻、薄、短、小的方向发展，此结构也无法。因此，需要予以改善。
但随着电子产品微小化的需求增加，现有封装结构显然无法符合电子元件轻薄短小的发展趋势，因此，如何在不增加制程的复杂度，即能得到厚度更薄的封装结构，实为业界迫切待开发的方向。
发明内容
鉴于上述现有技术的缺失，本发明提供一种封装结构及其制法，避免封装结构发生翘曲的缺失。
本发明的封装结构的制法，包括：于一载板上形成第一绝缘保护层；于该第一绝缘保护层上形成具有相对的第一表面与第二表面的介电体，且该介电体以其第一表面形成于该第一绝缘保护层上，该介电体中嵌埋有线路层与形成于该线路层上的多个导电柱；于该介电体的第二表面形成第二绝缘保护层，其中，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度大于250℃；以及移除该载板。
本发明还提供一种封装结构，包括：介电体，其具有相对的第一表面与第二表面；线路层，其嵌埋于该介电体中；多个导电柱，其嵌埋于该介电体中并形成于该线路层上；第一绝缘保护层，其形成于该介电体的第一表面上；以及第二绝缘保护层，其形成于该介电体的第二表面上，其中，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度大于250℃。
于本发明的封装结构及其制法中，该导电柱外露于该介电体的第二表面。其中，该第一绝缘保护层还包括多个外露出该线路层的第一开口；该第二绝缘保护层还包括多个外露出该导电柱端面的第二开口。还包括在外露于各该第一开口的部分该线路层上形成多个导电凸块，该导电凸块的高度为50微米。
于本发明的封装结构及其制法中，还包括于该第一绝缘保护层上设置半导体元件，该半导体元件电性连接至该线路层。还包括于该第一绝缘保护层上形成封装胶体，使该封装胶体包覆该半导体元件。
于前述本发明的封装结构及其制法中，该封装胶体的厚度介于20至180微米。
于本发明的封装结构及其制法中，该第一绝缘保护层的厚度及/或该第二绝缘保护层的厚度介于1至20微米。
于本发明的封装结构及其制法中，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度大于400℃。
于本发明的封装结构及其制法中，形成该第一绝缘保护层及/或该第二绝缘保护层的材质选自聚酰亚胺、聚酰胺酰亚胺、或聚苯咪唑。
由上可知，本发明藉由使用玻璃转移温度较高的第一绝缘保护层及/或第二绝缘保护层，得以在不需保留部分该载板作为支撑的情况下，即能防止封装结构发生翘曲的问题。
此外，本案的第一绝缘保护层与第二绝缘保护层更可做为绝缘保护线路之用，也不会额外增加整体封装的厚度，得以使后续设置半导体元件时，用于嵌埋该半导体元件的封装胶体的厚度低于200微米，因此得以降低整体封装结构的厚度，进而应用于厚度较小的电子产品。
附图说明
图1A至图1F为现有封装结构的制法的示意图，其中，图1E’为图1E的现有封装结构的另一实施例；以及
图2A至图2E”为显示本发明封装结构的制法的示意图，其中，图2A’为图2A的另一实施例，图2B’为图2B的另一实施例，图2D’为图2D的另一实施例，图2E’为图2E的另一实施例，以及图2E”为图2E的再一实施例。
符号说明
1、3、3’、4、4’、4” 封装结构
10、10’、20 载板
11、31 线路层
12、32 介电体
12a、32a 第一表面
12b、32b 第二表面
13、33 导电柱
21 晶种层
30 第一绝缘保护层
30a 第一开口
33a 端面
34 第二绝缘保护层
34a 第二开口
37、37’ 表面处理层
40 半导体元件
41、41’ 导电凸块
42 封装胶体
90 模具
900 容置空间
h1、h2 厚度
t 高度。
具体实施方式
以下藉由特定的具体实例说明本发明的实施方式，熟悉此技艺的人士可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。本发明也可藉由其他不同的具体实例加以施行或应用，本说明书中的各项细节也可基于不同观点与应用，在不悖离本发明的精神下进行各种修饰与变更。
须知，本说明书所附图式所绘示的结构、比例、大小等，均仅用于配合说明书所揭示的内容，以供熟悉此技艺的人士的了解与阅读，并非用于限定本创作可实施的限定条件，所以不具技术上的实质意义，任何结构的修饰、比例关系的改变或大小的调整，在不影响本创作所能产生的功效及所能达成的目的下，均应仍落在本创作所揭示的技术内容得能涵盖的范围内。同时，本说明书中所引用的如「上」、「第一」、「第二」、「端面」等用语，也仅为便于叙述的明了，而非用于限定本创作可实施的范围，其相对关系的改变或调整，在无实质变更技术内容下，当亦视为本创作可实施的范畴。
请参阅图2A至图2E为显示本发明封装结构的制法的剖视图。
如图2A所示，于一载板20上形成第一绝缘保护层30。
于本实施例中，以表面形成有金属层(例如，铜)的承载板(如，钢板、硅板、玻璃承载板)作为载板20。
此外，该第一绝缘保护层30的玻璃转移温度(glass transition temperature，简称TG)大于250℃，较佳为大于400℃。
又，形成该第一绝缘保护层30的材质选自聚酰亚胺(polyimide，简称PI)、聚酰胺酰亚胺(polyamide-imide，简称PAI)或聚苯咪唑(polybenzimidazole，简称PBI)。
另外，于其它实施例中，该第一绝缘保护层30上还可形成有晶种层(seed layer)21，以用于后续电镀线路之用，如图2A’所示，其中，对于该晶种层21的材质并未有特殊限制，仅需为可被蚀刻图案化的金属即可。
如图2B所示，于该第一绝缘保护层30上形成具有相对的第一表面32a与第二表面32b的介电体32，该介电体32嵌埋有线路层31与形成于该线路层31上的多个导电柱33，且该导电柱33的端面33a外露于该第二表面32b。
于本实施例中，对于该介电体32、线路层31与导电柱33的设置顺序并未有特殊限制，于本实施例中先于该第一绝缘保护层30上形成线路层31，并于部分该线路层31上形成导电柱33，再形成介电材料于该第一绝缘保护层30上使该等线路层31与导电柱33嵌埋于该介电体32中。
此外，对于形成该介电体32的材质并未有特殊限制，包括模压树脂(moldingcompound)、预浸材(prepreg)或感光型介电层(photodielectric)。或者，形成该介电体32的材质也可使用与该第一绝缘层30相同的材质形成。
又，对于该导电柱33的形状并未有特殊限制，可为圆柱体、椭圆柱体或多边形柱体皆可。
此外，倘若为延续如图2A’的制程，该线路层31形成于该晶种层21上，如图2B’所示。
如图2C所示，于该介电体30的第二表面30b形成第二绝缘保护层34。
于本实施例中，该第二绝缘保护层34的玻璃转移温度大于250℃，更佳为大于400℃。
此外，形成该第二绝缘保护层34的材质选自聚酰亚胺(PI)、聚酰胺酰亚胺(PAI)或聚苯咪唑(PBI)。
如图2D所示，其接续第2C图的制程，移除该载板20，以外露出整该第一绝缘保护层30。接着，于该第一绝缘保护层30与该第二绝缘保护层34上分别形成用于外露出该线路层31与导电柱33的多个第一开口30a与多个第二开口34a。之后并进行切单制程得到本发明的封装结构3。
于本实施例中，可于该线路层31与该导电柱33上分别形成表面处理层37,37’。其中，形成该表面处理层37,37’的材质为镍、钯、金所组群组的合金或有机保焊层(OrganicSolderability Preservatives，简称OSP)。
此外，若接续图2B’的制程，该表面处理层37将形成于该线路层31的晶种层21的表面上，如图2D’所示的封装结构3’。
于本发明的封装结构3中，藉由该第一绝缘保护层30的玻璃转移温度及/或该第二绝缘保护层34的玻璃转移温度大于250℃，使后续制程中不需保留载板20作为支撑，即能藉由该第一绝缘保护层30及/或该第二绝缘保护层34提供本发明的封装结构3不易脆裂、于高温制程中不具有流动性的良好地结构刚性。
于后续制程中，如图2E所示，于该第一绝缘保护层30上可设置半导体元件40，该半导体元件40电性连接至该线路层31，且于该第一绝缘保护层30上形成封装胶体42，以包覆该半导体元件40。具体地，形成多个如焊锡材料的导电凸块41于外露于各该第一开口30a的部分该线路层31上，使该半导体元件40藉由该些导电凸块41电性连接至该线路层31。
于本实施例中，该封装胶体42的玻璃转移温度小于该第一绝缘保护层30的玻璃转移温度或该第二绝缘保护层34的玻璃转移温度。
此外，图2E’为接续图2D’的制程。
又，如图2E”所示，该导电凸块41’包含铜柱与焊锡材料。
另外，该封装胶体42的厚度h2为介于20至180微米，且该导电凸块41的高度t为50微米。
于本发明的封装结构4,4’,4”中，由于该第一绝缘保护层30的玻璃转移温度及/或该第二绝缘保护层34的玻璃转移温度大于250℃，所以不需保留载板20作为支撑，因此该封装胶体42的厚度h2能介于20至180微米。
本发明提供一种封装结构3,3’,4,4’,4”，包括：一介电体32、一线路层31、多个导电柱33、一第一绝缘保护层30以及一第二绝缘保护层34。
所述的介电体32具有相对的第一表面32a与第二表面32b。
所述的线路层31嵌埋于该介电体32中。
所述的多个导电柱33嵌埋于该介电体32中并形成于该线路层31上。
所述的第一绝缘保护层30形成于该介电体32的第一表面32a上，所述的第二绝缘保护层34形成于该介电体32的第二表面32b上，该第一绝缘保护层30及/或该第二绝缘保护层34的厚度为介于1至20微米。其中，该第一绝缘保护层30的玻璃转移温度及/或该第二绝缘保护层34的玻璃转移温度为大于250℃。
于一实施例中，该导电柱33外露于该介电体32的第二表面32b。该第一绝缘保护层30还包括外露出该线路层31的第一开口30a，该第二绝缘保护层34还包括外露出该导电柱33的第二开口34a。还包括多个导电凸块41,41’，其对应形成于各该第一开口30a中的该线路层31上。其中，该导电凸块41,41’的高度t为50微米。
于一实施例中，还包括于该第一绝缘保护层30上设置半导体元件40，该半导体元件40电性连接至该线路层31。还包括于该第一绝缘保护层30上形成封装胶体42，使该封装胶体42包覆该半导体元件40，且该封装胶体42的厚度h2为介于20至180微米。
于一实施例中，该第一绝缘保护层30的玻璃转移温度及/或该第二绝缘保护层34的玻璃转移温度大于400℃。
于一实施例中，形成该第一绝缘保护层30及/或该第二绝缘保护层34的材质选自聚酰亚胺、聚酰胺酰亚胺、或聚苯咪唑。
由上可知，于本发明藉由使用玻璃转移温度较高的第一绝缘保护层及/或第二绝缘保护层，得以在不需保留部分该载板作为支撑的情况下，即能防止封装结构发生翘曲的问题。
此外，由于本发明的第一绝缘保护层及/或第二绝缘保护层具有较高的玻璃转移温度，因此于进行高温且时间较长的回焊制程(如，红外线回焊制程(IR reflow))时，不会发生软化的现象、变形量小、不易产生位移，相较于现有封装结构本发明的封装结构更具有对位精准度高的功效。
此外，本案的第一绝缘保护层与第二绝缘保护层更可做为绝缘保护线路之用，也不会额外增加整体封装结构的厚度，得以使后续设置半导体元件时，用于嵌埋该半导体元件的封装胶体的厚度低于200微米(μm)，因此得以降低整体封装结构的厚度，进而应用于厚度较小的电子产品。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范畴下，对上述实施例进行修饰与改变。因此，本发明的权利保护范围，应如权利要求书所列。

Claims (20)

1.一种封装结构的制法，包括：
于一载板上形成第一绝缘保护层；
于该第一绝缘保护层上形成具有相对的第一表面与第二表面的介电体，且该介电体以其第一表面形成于该第一绝缘保护层上，该介电体中嵌埋有线路层与形成于该线路层上的多个导电柱；
于该介电体的第二表面形成第二绝缘保护层，其中，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度为大于250℃；
移除该载板；以及
于该第一绝缘保护层形成外露出该线路层的第一开口，于该第二绝缘保护层形成外露出该导电柱的第二开口。
2.如权利要求1所述的封装结构的制法，其特征为，该导电柱外露于该介电体的第二表面。
3.如权利要求1所述的封装结构的制法，其特征为，该制法还包括在外露于各该第一开口的部分该线路层上形成多个导电凸块。
4.如权利要求3所述的封装结构的制法，其特征为，该导电凸块的高度为50微米。
5.如权利要求1所述的封装结构的制法，其特征为，该制法还包括于该第一绝缘保护层上设置半导体元件，该半导体元件电性连接至该线路层。
6.如权利要求5所述的封装结构的制法，其特征为，该制法还包括于该第一绝缘保护层上形成封装胶体，使该封装胶体包覆该半导体元件。
7.如权利要求6所述的封装结构的制法，其特征为，该封装胶体的厚度为20至180微米。
8.如权利要求1所述的封装结构的制法，其特征为，该第一绝缘保护层的厚度或该第二绝缘保护层的厚度介于1至20微米。
9.如权利要求1所述的封装结构的制法，其特征为，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度为大于400℃。
10.如权利要求1所述的封装结构的制法，其特征为，形成该第一绝缘保护层及/或该第二绝缘保护层的材质选自聚酰亚胺、聚酰胺酰亚胺、或聚苯咪唑。
11.一种封装结构，包括：
介电体，其具有相对的第一表面与第二表面；
线路层，其嵌埋于该介电体中；
多个导电柱，其嵌埋于该介电体中并形成于该线路层上；
第一绝缘保护层，其形成于该介电体的第一表面上，其中，该第一绝缘保护层还包括多个外露出该线路层的第一开口；以及
第二绝缘保护层，其形成于该介电体的第二表面上，其中，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度大于250℃，且该第二绝缘保护层还包括多个外露出该导电柱的第二开口。
12.如权利要求11所述的封装结构，其特征为，该导电柱外露于该介电体的第二表面。
13.如权利要求11所述的封装结构，其特征为，该封装结构还包括多个导电凸块，各该导电凸块对应形成于各该第一开口中的该线路层上。
14.如权利要求13所述的封装结构，其特征为，该导电凸块的高度为50微米。
15.如权利要求11所述的封装结构，其特征为，该封装结构还包括设于该第一绝缘保护层上的半导体元件，其电性连接至该线路层。
16.如权利要求15所述的封装结构，其特征为，该封装结构还包括形成于该第一绝缘保护层上的封装胶体，其包覆该半导体元件。
17.如权利要求16所述的封装结构，其特征为，该封装胶体的厚度介于20至180微米。
18.如权利要求11所述的封装结构，其特征为，该第一绝缘保护层的厚度或该第二绝缘保护层的厚度介于1至20微米。
19.如权利要求11所述的封装结构，其特征为，该第一绝缘保护层的玻璃转移温度及/或该第二绝缘保护层的玻璃转移温度为大于400℃。
20.如权利要求11所述的封装结构，其特征为，形成该第一绝缘保护层及/或该第二绝缘保护层的材质选自聚酰亚胺、聚酰胺酰亚胺、或聚苯咪唑。
CN201410603698.6A 2014-10-22 2014-10-31 封装结构及其制法 Active CN105633052B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW103136417 2014-10-22
TW103136417A TWI559829B (zh) 2014-10-22 2014-10-22 封裝結構及其製法

Publications (2)

Publication Number Publication Date
CN105633052A CN105633052A (zh) 2016-06-01
CN105633052B true CN105633052B (zh) 2018-11-27

Family

ID=55792580

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410603698.6A Active CN105633052B (zh) 2014-10-22 2014-10-31 封装结构及其制法

Country Status (3)

Country Link
US (2) US20160118323A1 (zh)
CN (1) CN105633052B (zh)
TW (1) TWI559829B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090294961A1 (en) * 2008-06-02 2009-12-03 Infineon Technologies Ag Semiconductor device
CN106783794B (zh) * 2017-03-16 2019-03-22 江阴芯智联电子科技有限公司 预包封无导线可电镀引线框架封装结构及其制造方法
CN110729255A (zh) * 2019-08-08 2020-01-24 厦门云天半导体科技有限公司 一种键合墙体扇出器件的三维封装结构和方法
US20210408354A1 (en) * 2020-06-29 2021-12-30 Nec Corporation Quantum device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101730396A (zh) * 2008-10-27 2010-06-09 欣兴电子股份有限公司 增加线路密度的增层电路板制造方法及其结构
CN104103596A (zh) * 2013-04-09 2014-10-15 英特尔公司 包括玻璃焊接掩模层的集成电路封装组件

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3773896B2 (ja) * 2002-02-15 2006-05-10 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
EP1579477A2 (en) * 2002-10-11 2005-09-28 Tessera, Inc. Components, methods and assemblies for multi-chip packages
JP4567328B2 (ja) * 2003-12-26 2010-10-20 日本特殊陶業株式会社 多層セラミック基板の製造方法
JP4558413B2 (ja) * 2004-08-25 2010-10-06 新光電気工業株式会社 基板、半導体装置、基板の製造方法、及び半導体装置の製造方法
US7335608B2 (en) * 2004-09-22 2008-02-26 Intel Corporation Materials, structures and methods for microelectronic packaging
US20060160346A1 (en) * 2005-01-19 2006-07-20 Intel Corporation Substrate bump formation
US7713859B2 (en) * 2005-08-15 2010-05-11 Enthone Inc. Tin-silver solder bumping in electronics manufacture
JP4473807B2 (ja) * 2005-10-27 2010-06-02 パナソニック株式会社 積層半導体装置及び積層半導体装置の下層モジュール
JP4806279B2 (ja) * 2006-03-17 2011-11-02 三菱樹脂株式会社 ガラスクロス含有絶縁基材
JP4431123B2 (ja) * 2006-05-22 2010-03-10 日立電線株式会社 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法
US20090001599A1 (en) * 2007-06-28 2009-01-01 Spansion Llc Die attachment, die stacking, and wire embedding using film
US8604352B2 (en) * 2008-03-31 2013-12-10 Sumitomo Bakelite Co., Ltd. Multilayer circuit board, insulating sheet, and semiconductor package using multilayer circuit board
TWI389279B (zh) * 2009-01-23 2013-03-11 Unimicron Technology Corp 電路板結構及其製法
US7851269B2 (en) * 2009-02-19 2010-12-14 Intel Corporation Method of stiffening coreless package substrate
TWI446496B (zh) * 2009-06-24 2014-07-21 Unimicron Technology Corp 封裝基板裝置及其製法
US9355951B2 (en) * 2009-08-28 2016-05-31 Marvell World Trade Ltd. Interconnect layouts for electronic assemblies
US8901724B2 (en) * 2009-12-29 2014-12-02 Intel Corporation Semiconductor package with embedded die and its methods of fabrication
JP5566200B2 (ja) * 2010-06-18 2014-08-06 新光電気工業株式会社 配線基板及びその製造方法
US8127979B1 (en) * 2010-09-25 2012-03-06 Intel Corporation Electrolytic depositon and via filling in coreless substrate processing
US20120326300A1 (en) * 2011-06-24 2012-12-27 National Semiconductor Corporation Low profile package and method
TWI463925B (zh) * 2011-07-08 2014-12-01 Unimicron Technology Corp 封裝基板及其製法
TWI475935B (zh) * 2011-07-08 2015-03-01 Unimicron Technology Corp 無核心層之封裝基板及其製法
US9947606B2 (en) * 2012-04-26 2018-04-17 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including electromagnetic absorption and shielding
TWI544599B (zh) * 2012-10-30 2016-08-01 矽品精密工業股份有限公司 封裝結構之製法
US8946900B2 (en) * 2012-10-31 2015-02-03 Intel Corporation X-line routing for dense multi-chip-package interconnects
GB2520952A (en) * 2013-12-04 2015-06-10 Ibm Flip-chip electronic device with carrier having heat dissipation elements free of solder mask
EP3099730A4 (en) * 2014-01-31 2017-08-09 Fujifilm Electronic Materials USA, Inc. Novel polyimide compositions
US9401287B2 (en) * 2014-02-07 2016-07-26 Altera Corporation Methods for packaging integrated circuits
US9466554B2 (en) * 2014-02-13 2016-10-11 Qualcomm Incorporated Integrated device comprising via with side barrier layer traversing encapsulation layer
TW201537646A (zh) * 2014-03-31 2015-10-01 Chipmos Technologies Inc 半導體封裝及其製造方法
US9202789B2 (en) * 2014-04-16 2015-12-01 Qualcomm Incorporated Die package comprising die-to-wire connector and a wire-to-die connector configured to couple to a die package
TWI548052B (zh) * 2014-04-22 2016-09-01 矽品精密工業股份有限公司 半導體中介板及封裝結構
TWI555101B (zh) * 2014-05-27 2016-10-21 矽品精密工業股份有限公司 封裝結構及其製法
US20150361264A1 (en) * 2014-06-12 2015-12-17 E I Du Pont De Nemours And Company Light emitting diode assembly and thermal control blanket and methods relating thereto
TWI624018B (zh) * 2014-08-04 2018-05-11 恆勁科技股份有限公司 封裝結構及其製法
US9385073B2 (en) * 2014-08-19 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packages having integrated devices and methods of forming same
KR101676916B1 (ko) * 2014-08-20 2016-11-16 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
US9543170B2 (en) * 2014-08-22 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
TWI611523B (zh) * 2014-09-05 2018-01-11 矽品精密工業股份有限公司 半導體封裝件之製法
TWI558288B (zh) * 2014-09-10 2016-11-11 恆勁科技股份有限公司 中介基板及其製法
TWI566659B (zh) * 2014-09-18 2017-01-11 矽品精密工業股份有限公司 封裝基板及其製法
TWI570816B (zh) * 2014-09-26 2017-02-11 矽品精密工業股份有限公司 封裝結構及其製法
TWI578472B (zh) * 2014-11-27 2017-04-11 矽品精密工業股份有限公司 封裝基板、半導體封裝件及其製法
TWI550744B (zh) * 2014-12-04 2016-09-21 矽品精密工業股份有限公司 單層線路式封裝基板及其製法、單層線路式封裝結構及其製法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101730396A (zh) * 2008-10-27 2010-06-09 欣兴电子股份有限公司 增加线路密度的增层电路板制造方法及其结构
CN104103596A (zh) * 2013-04-09 2014-10-15 英特尔公司 包括玻璃焊接掩模层的集成电路封装组件

Also Published As

Publication number Publication date
US20170229319A1 (en) 2017-08-10
TWI559829B (zh) 2016-11-21
TW201616933A (zh) 2016-05-01
US20160118323A1 (en) 2016-04-28
US10147615B2 (en) 2018-12-04
CN105633052A (zh) 2016-06-01

Similar Documents

Publication Publication Date Title
US9536864B2 (en) Package structure and its fabrication method
CN107799482A (zh) 半导体封装结构及制造其之方法
CN107424970B (zh) 半导体装置封装及其制造方法
CN105633052B (zh) 封装结构及其制法
CN107785334B (zh) 电子封装结构及其制法
CN105321926A (zh) 封装装置及其制作方法
CN105405775B (zh) 封装结构的制法
CN108962840A (zh) 电子封装件及其制法
US20160093546A1 (en) Package stucture and method of fabricating the same
CN103165484A (zh) 堆迭式封装及其制造方法
TWI591739B (zh) 封裝堆疊結構之製法
US11037716B2 (en) Inductor and method of manufacturing the same
CN104979219B (zh) 封装结构及其制法
US20160079170A1 (en) Semiconductor package structure and method of fabricating the same
CN106169427B (zh) 基于薄膜的扇出及多晶粒封装平台
CN108447829A (zh) 封装结构及其制法
TWI566330B (zh) 電子封裝結構之製法
CN108987355A (zh) 电子封装件及其制法
TWI557860B (zh) 半導體封裝件及其製法
CN108511352A (zh) 电子封装结构及其制法
CN105810659A (zh) 封装装置及其制作方法
US10643863B2 (en) Semiconductor package and method of manufacturing the same
US20160293578A1 (en) Multi-chip-module semiconductor chip package having dense package wiring
CN107768320A (zh) 电子封装件及其制法
CN104795369B (zh) 用于接置半导体装置的层结构及其制法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant