CN108962840A - 电子封装件及其制法 - Google Patents

电子封装件及其制法 Download PDF

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Publication number
CN108962840A
CN108962840A CN201710436397.2A CN201710436397A CN108962840A CN 108962840 A CN108962840 A CN 108962840A CN 201710436397 A CN201710436397 A CN 201710436397A CN 108962840 A CN108962840 A CN 108962840A
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line construction
packing piece
electronic
electronic component
piece according
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CN108962840B (zh
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邱志贤
陈嘉扬
何志强
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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Abstract

一种电子封装件及其制法,先提供一包含有一支撑板与多个设于该支撑板上的导电柱的金属件,再将线路结构结合至该些导电柱上,且接置电子元件于该金属件上并电性连接该线路结构,并以封装层包覆该些导电柱与该第一电子元件,无需配合该电子封装件的尺寸使用特定尺寸的模压模具,因而能降低生产成本。

Description

电子封装件及其制法
技术领域
本发明关于一种半导体结构,特别是关于一种封装结构及其制法。
背景技术
随着近年来可携式电子产品的蓬勃发展,各类相关产品逐渐朝向高密度、高性能以及轻、薄、短、小的趋势发展,其中,应用于该可携式电子产品的各态样的半导体封装结构也因而配合推陈出新,以期能符合轻薄短小与高密度的要求。
图1为现有半导体封装结构1的剖视示意图。该半导体封装结构1于一线路结构10的上、下两侧设置半导体元件11与被动元件11’,再以封装胶体14包覆该些半导体元件11与被动元件11’,并使该线路结构10的接点(I/O)100外露出该封装胶体(molding compound)14,之后形成多个焊球13于该些接点100上,以于后续制程中,该半导体封装结构1透过该焊球13接置如电路板的电子装置(图略)。
惟,现有半导体封装结构1中,由于需使该封装胶体14的模压(molding)范围缩减以外露该些接点100,因而需视该半导体封装结构1的尺寸而使用特定尺寸的模压模具,故单一模压模具无法适用于各式半导体封装结构的尺寸,因而增加生产成本。
又,该些半导体元件11与被动元件11’包覆于该封装胶体14中,致使该些半导体元件11与被动元件11’的散热效果不佳。
因此,如何克服上述现有技术的种种问题,实已成目前亟欲解决的课题。
发明内容
鉴于上述现有技术的缺失,本发明提供一种电子封装件及其制法,能降低生产成本。
本发明的电子封装件,包括:线路结构,其具有相对的第一侧与第二侧;多个导电柱,其设于该线路结构的第一侧上;多个导电体,其对应设于各该导电柱上以位于各该导电柱与该线路结构的第一侧之间,使该些导电柱通过该些导电体电性连接该线路结构;至少一第一电子元件,其设于该线路结构的第一侧上并电性连接该线路结构;至少一第二电子元件,其设于该线路结构的第二侧上并电性连接该线路结构;以及封装层,其形成于该线路结构的第一侧上以包覆该些导电柱与该第一电子元件。
本发明还提供一种电子封装件的制法,包括:提供一金属件,该金属件包含有一支撑板及多个设于该支撑板上的导电柱;将具有相对的第一侧与第二侧的线路结构以该第一侧结合至该些导电柱上,使该些导电柱通过导电体电性连接该线路结构,其中,该线路结构的第一侧与第二侧上分别接置有至少一第一电子元件与至少一第二电子元件,并以封装层包覆该些导电柱、该些导电体与该第一电子元件;以及移除该支撑板。
前述的制法中,该线路结构的第一侧第二侧先接置有该第一电子元件与第二电子元件,接着将该线路结构的第一侧接置于该导电柱上,再于该线路结构的第一侧与该支撑板间形成包覆该导电柱与该第一电子元件的封装层,之后移除该支撑板。
前述的制法中,该第一电子元件先接置于该支撑板上,接着于该支撑板上形成包覆该导电柱及该第一电子元件的封装层,然后于该封装层上形成电性连接该导电柱与该第一电子元件的该线路结构,再于该线路结构上接置该第二电子元件,之后移除该支撑板。
前述的电子封装件及其制法中,该金属件还具有嵌设于该封装层中以结合该第一电子元件的结合垫。
前述的电子封装件及其制法中,该线路结构的第二侧形成有包覆该第二电子元件的包覆层;抑或该封装层还形成于该线路结构的第二侧上以包覆该第二电子元件。
前述的电子封装件及其制法中,该导电柱的顶面外露出该封装层。进一步地,该导电柱的部分侧面也外露出该封装层。
前述的电子封装件及其制法中,还包括结合该导电柱的电性接触垫。进一步地,该电性接触垫的侧面外露出该封装层。
前述的电子封装件及其制法中,该导电体为焊锡材、金属柱或其二者组合。
由上可知,本发明的电子封装件及其制法中,主要通过包含有支撑板及导电柱的金属件的设计,以令电子元件及线路结构接置于该支撑板及导电柱上,再于该支撑板上形成包覆该电子元件、导电体及该导电柱的封装层,故相较于现有技术,本发明使用共用模压模具形成该封装层即可,而无需配合该电子封装件的尺寸,因而能降低生产成本。
此外,通过该金属架包含有用以结合至电子元件的结合垫的设计,以提升该电子封装件的散热效果。
附图说明
图1为现有半导体封装结构的剖面示意图;
图2A至图2C为本发明的电子封装件的制法的第一实施例的剖面示意图;
图2C’及图2C”为对应图2C的其它实施例的剖面示意图;
图3A至图3C为本发明的电子封装件的制法的第二实施例的剖面示意图;
图4A及图4B为本发明的电子封装件的第三实施例的剖面示意图;以及
图5A及图5B为本发明的电子封装件的第四实施例的剖面示意图。
符号说明:
1 半导体封装结构
10,20,30 线路结构
100 接点
11 半导体元件
11’ 被动元件
13 焊球
14 封装胶体
2,2’,2”,3,4,4’,5,5’ 电子封装件
2a 电子组件
20a,30a 第一侧
20b,30b 第二侧
200,300 线路层
21 第一电子元件
210,220 导电凸块
22 第二电子元件
23,33,53 导电体
24 包覆层
25 金属件
250 导电柱
250a 顶面
250b 端部
250c 侧面
251 结合垫
252 支撑板
252’ 电性接触垫
252c 侧面
26,26’ 封装层
26a 第一表面
26b 第二表面
26c 侧表面
28 结合层
40 焊锡材料。
具体实施方式
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点及功效。
须知,本说明书所附图式所绘示的结构、比例、大小等,均仅用以配合说明书所揭示的内容,以供本领域技术人员的了解与阅读,并非用以限定本发明可实施的限定条件,故不具技术上的实质意义,任何结构的修饰、比例关系的改变或大小的调整,在不影响本发明所能产生的功效及所能达成的目的下,均应仍落在本发明所揭示的技术内容得能涵盖的范围内。同时,本说明书中所引用的如“上”、“第一”、“第二”、及“一”等的用语,也仅为便于叙述的明了,而非用以限定本发明可实施的范围,其相对关系的改变或调整,在无实质变更技术内容下,当也视为本发明可实施的范畴。
图2A至图2C为本发明的电子封装件的制法的第一实施例的剖面示意图。
如图2A所示,提供一金属件25,其包含一支撑板252、相分离地设于该支撑板252上的多个导电柱250与至少一结合垫251。
于本实施例中,该支撑板252、导电柱250与结合垫251一体成形。例如,以蚀刻、雷射或其它方式移除一金属板体上的材质,以形成该金属件25。
如图2B所示,将一电子组件2a结合至该些导电柱250上,使该电子组件2a堆迭于该金属件25上。
于本实施例中,该电子组件2a包含有线路结构20以及设于该线路结构20上的第一电子元件21与第二电子元件22。
所述的线路结构20具有相对的第一侧20a与第二侧20b。于本实施例中,该线路结构20为如具有核心层与线路结构的封装基板(substrate)或无核心层(coreless)的线路结构,其具有多个线路层200,如扇出(fan out)型重布线路层(redistribution layer,简称RDL)。应可理解地,该线路结构20也可为其它可供承载如芯片等电子元件的承载单元,例如导线架(leadframe),并不限于上述。
所述的第一电子元件21设于该线路结构20的第一侧20a上。于本实施例中,该第一电子元件21为主动元件、被动元件或其二者组合等,其中,该主动元件为例如半导体芯片,且该被动元件为例如电阻、电容及电感。例如,该第一电子元件21通过多个如焊锡材料的导电凸块210以覆晶方式设于该线路层200上并电性连接该线路层200;或者,该第一电子元件21可通过多个焊线(图略)以打线方式电性连接该线路层200。然而,有关该第一电子元件21电性连接该线路结构20的方式不限于上述。
所述的第二电子元件22设于该线路结构20的第二侧20b上。于本实施例中,该第二电子元件22为主动元件、被动元件或其二者组合等,其中,该主动元件为例如半导体芯片,且该被动元件为例如电阻、电容及电感。例如,该第二电子元件22通过多个如焊锡材料的导电凸块220以覆晶方式设于该线路层200上;或者,该第二电子元件22可通过多个焊线(图略)以打线方式电性连接该线路层200;抑或,该第二电子元件22可直接接触该线路层200。然而,有关该第二电子元件22电性连接该线路结构20的方式不限于上述。
此外,该第一电子元件21可通过一结合层28结合至该结合垫251,其中,该结合层28例如为薄膜(film)、环氧树脂(epoxy)或热介面材料(thermal interface material,简称TIM)。
又,该些导电柱250可通过如焊锡材的导电体23结合至该线路结构20的第一侧20a的线路层200上。
另外,该电子组件2a还可包含一包覆层24,其形成于该线路结构20的第二侧20b上以包覆该第二电子元件22。例如,形成该包覆层24的材质为聚酰亚胺(polyimide,简称PI)、干膜(dry film)、环氧树脂(epoxy)或封装材(molding compound),但不限于上述。
如图2C所示,形成一封装层26于该线路结构20的第一侧20a与该金属件25(该支撑板252)之间,使该封装层26包覆该第一电子元件21、导电体23与该些导电柱250。之后,移除该支撑板252,使该些导电柱250的顶面250a与该结合垫251外露出该封装层26,以形成本发明的电子封装件2。
于本实施例中,该封装层26具有相对的第一表面26a与第二表面26b,使该封装层26以其第二表面26b结合该线路结构20的第一侧20a,且该些导电柱250与该结合垫251嵌设于该封装层26的第一表面26a,并使该些导电柱250的顶面250a与该结合垫251外露出该封装层26的第一表面26a(例如,该些导电柱250的顶面250a与该结合垫251的表面齐平该封装层26的第一表面26a),以于该些导电柱250的外露表面(顶面)上形成有如焊球的焊锡材料(图略),以供接置如电路板的电子装置。
此外,形成该封装层26的材质为聚酰亚胺(PI)、干膜、环氧树脂或封装材,故该封装层26的材质与该包覆层24的材质可相同或不相同。
又,如图2C’所示的电子封装件2’,于移除该支撑板252后,可移除该封装层26的部分第一表面26a,使该些导电柱250凸出该封装层26的第一表面26a,以令该些导电柱250的顶面250a与部分侧面250c外露出该封装层26的第一表面26a。
另外,如图2C”所示的电子封装件2”,若该电子组件2a未事先形成包覆层24,则可于线路结构20的第一侧20a及第二侧20b上形成封装层26,26’,令封装层26包覆该第一电子元件21及令封装层26’包覆该第二电子元件22;或者,也可保留部分该支撑板252以作为该电性接触垫252’,其中,该电性接触垫252’连接至该导电柱250,且该电性接触垫252’的侧面252c外露出该封装层26的侧表面26c。应可理解地,也可依需求,使该些导电柱250的侧面250c及该电性接触垫252’的侧面252c外露出该封装层26的侧表面26c。
本发明的制法中,先制作该金属件25,再形成该封装层26,并使该导电柱250外露出该封装层26以作为电性接点,故无需配合该电子封装件2,2’,2”的尺寸而使用特定尺寸的模压模具,也就是使用共用模压模具形成该封装层26即可,因而能降低生产成本。
此外,通过该结合垫251的设计,以传导该第一电子元件21的热量,故能提升该电子封装件2,2’,2”的散热效果。
图3A至图3C为本发明的电子封装件3的制法的第二实施例的剖面示意图。本实施例与第一实施例的差异在于制程步骤顺序,故以下仅说明相异处,而不再赘述相同处。
如图3A所示,首先于金属件25的结合垫251上通过结合层28结合第一电子元件21,且于该金属件25的支撑板25上形成该封装层26以包覆该第一电子元件21与该金属件25的导电柱250。
于本实施例中,以压合方式形成该封装层26,使该封装层26覆盖该第一电子元件21与该些导电柱250的端部250b。
如图3B所示,形成一线路结构30于该封装层26上。
于本实施例中,于该封装层26上直接进行扇出型重布线路层的制作以形成该线路结构30,使该线路结构30于制作该线路层300时,可将部分线路(即导电盲孔)延伸至该封装层26中以作为金属柱的导电体33,俾供电性连接该线路层300、该些导电柱250与该第一电子元件21。应可理解地,若该些导电柱250的端部250b不低于该封装层26的第二表面26b(也就是,该些导电柱250的端部250b可齐平该封装层26的第二表面26b),则该线路层200无需延伸入该封装层26中,即可电性连接该些导电柱250与该第一电子元件21。
如图3C所示,接置多个第二电子元件22于该线路结构30的第二侧30b上,且形成包覆层24于该线路结构30的第二侧30b上以包覆该第二电子元件22,再移除该支撑板252,以形成本发明的电子封装件3。
因此,本发明的电子封装件3,通过先制作该金属件25,再形成该封装层26,并使该导电柱250外露出该封装层26以作为电性接点,故无需配合该电子封装件3的尺寸而使用特定尺寸的模压模具,也就是使用共用模压模具形成该封装层26即可,因而能降低生产成本。
此外,通过该结合垫251的设计,以传导该第一电子元件21的热量,故能提升该电子封装件3的散热效果。。
图4A及图4B为本发明的电子封装件4,4’的第三实施例的剖面示意图。本实施例与第一实施例的差异在于金属件25的加工,故以下仅说明相异处,而不再赘述相同处。
如图4A所示,该结合垫251作为散热片,其凸出该封装层26的第一表面26a。
如图4B所示,该第一电子元件21未结合至该结合垫251,因而省略使用该结合层28,且于该些导电柱250的外露表面(顶面)上形成有如焊球的焊锡材料40,俾供接置如电路板的电子装置。
图5A及图5B为本发明的电子封装件5,5’的第四实施例的剖面示意图。本实施例与第一实施例的差异在于导电体的构造,故以下仅说明相异处,而不再赘述相同处。
如图5A所示,该导电体23,53由金属柱与焊锡材所构成。
于本实施例中,于图2B的制程前,先将金属柱的导电体53形成于该线路结构20的第一侧20a的线路层200上,再将焊锡材的导电体23形成于该金属柱上,以于图2B的制程中,将焊锡材的导电体23结合该导电柱250。
此外,如图5B所示,该些导电柱250与该结合垫251也可凸出该封装层26的第一表面26a。
本发明还提供一种电子封装件2,2’,2”,3,4,4’,5,5’,其包括:一线路结构20,30、多个导电柱250、多个导电体23,33,53、至少一第一电子元件21以及一封装层26,26’。
所述的线路结构20,30具有相对的第一侧20a,30a与第二侧20b,30b。
所述的导电柱250设于该线路结构20,30的第一侧20a,30a上。
所述的导电体23,33,53对应设于各该导电柱250上以位于各该导电柱250与该线路结构20,30的第一侧20a,30a之间,使该些导电柱250通过该些导电体23,33,53电性连接该线路结构20,30。
所述的第一电子元件21设于该线路结构20,30的第一侧20a,30a上并电性连接该线路结构20,30。
所述的封装层26形成于该线路结构20,30的第一侧20a,30a上以包覆该些导电柱250、该些导电体23,33,53与该第一电子元件21。
于一实施例中,所述的电子封装件2,2’,2”,3,4,5,5’还包括一结合该第一电子元件21且外露于该封装层26的结合垫251。
于一实施例中,该线路结构20,30的第二侧20b,30b设有第二电子元件22。
于一实施例中,该导电柱250的顶面250a外露出该封装层26的第一表面26a、或该导电柱250的顶面250a与部分侧面250c外露出该封装层26的第一表面26a。
于一实施例中,该导电柱250的侧面250c外露出该封装层26的侧表面26c。
于一实施例中,所述的电子封装件2”还包括至少一嵌设于该封装层26中以结合该导电柱250的电性接触垫252’。例如,该电性接触垫252’的侧面252c外露出该封装层26的侧表面26c。
于一实施例中,该导电体23,33,53为焊锡材、金属柱或其二者组合。
综上所述,本发明的电子封装件及其制法,通过包含有支撑板、结合垫及导电柱的该金属件的设计,以令电子元件及线路结构接置于该结合垫及导电柱上,再于该支撑板上形成该封装层,故无需配合该电子封装件的尺寸而使用特定尺寸的模压模具,也就是使用共用模压模具形成该封装层即可,因而能降低生产成本。
此外,通过该结合垫的设计,以传导该第一电子元件的热量,故能提升该电子封装件的散热效果。
上述实施例用以例示性说明本发明的原理及其功效,而非用于限制本发明。任何所属领域技术人员均可在不违背本发明的精神及范畴下,对上述实施例进行修改。因此本发明的权利保护范围,应如权利要求书所列。

Claims (20)

1.一种电子封装件,其特征为,该电子封装件包括:
线路结构,其具有相对的第一侧与第二侧;
多个导电柱,其设于该线路结构的第一侧上;
多个导电体,其对应设于各该导电柱上以位于各该导电柱与该线路结构的第一侧之间,使所述导电柱通过所述导电体电性连接该线路结构;
至少一第一电子元件,其设于该线路结构的第一侧上并电性连接该线路结构;
至少一第二电子元件,其设于该线路结构的第二侧上并电性连接该线路结构;以及
封装层,其形成于该线路结构的第一侧上以包覆所述导电柱、所述导电体与该第一电子元件。
2.根据权利要求1所述的电子封装件,其特征为,该电子封装件还包括结合于该第一电子元件上的结合垫。
3.根据权利要求1所述的电子封装件,其特征为,该电子封装件还包括形成于该线路结构的第二侧上以包覆该第二电子元件的包覆层。
4.根据权利要求1所述的电子封装件,其特征为,该导电柱的顶面外露出该封装层。
5.根据权利要求4所述的电子封装件,其特征为,该导电柱的部分侧面也外露出该封装层。
6.根据权利要求1所述的电子封装件,其特征为,该封装层还形成于该线路结构的第二侧上以包覆该第二电子元件。
7.根据权利要求1所述的电子封装件,其特征为,该电子封装件还包括结合于该导电柱上的电性接触垫。
8.根据权利要求7所述的电子封装件,其特征为,该电性接触垫外露出该封装层。
9.根据权利要求1所述的电子封装件,其特征为,该导电体为焊锡材、金属柱或其二者组合。
10.一种电子封装件的制法,其特征为包括:
提供一金属件,该金属件包含有一支撑板及多个设于该支撑板上的导电柱;
将具有相对的第一侧与第二侧的线路结构以该第一侧结合至所述导电柱上,使所述导电柱通过导电体电性连接该线路结构,其中,该线路结构的第一侧与第二侧上分别接置有至少一第一电子元件与至少一第二电子元件,并以封装层包覆所述导电柱、所述导电体与该第一电子元件;以及
移除该支撑板。
11.根据权利要求10所述的电子封装件的制法,其特征为,该金属件还包含有用以结合该第一电子元件的结合垫。
12.根据权利要求10所述的电子封装件的制法,其特征为,该制法包括形成包覆层于该线路结构的第二侧上以包覆该第二电子元件。
13.根据权利要求10所述的电子封装件的制法,其特征为,该导电柱的顶面外露出该封装层。
14.根据权利要求13所述的电子封装件的制法,其特征为,该导电柱的部分侧面也外露出该封装层。
15.根据权利要求10所述的电子封装件的制法,其特征为,该封装层还形成于该线路结构的第二侧上以包覆该第二电子元件。
16.根据权利要求10所述的电子封装件的制法,其特征为,该制法还包括保留部分该支撑板以作为电性接触垫,其中,该电性接触垫连结至该导电柱。
17.根据权利要求16所述的电子封装件的制法,其特征为,该电性接触垫外露出该封装层。
18.根据权利要求10所述的电子封装件的制法,其特征为,该线路结构的第一侧第二侧先接置有该第一电子元件与第二电子元件,接着将该线路结构的第一侧接置于该导电柱上,再于该线路结构的第一侧与该支撑板间形成包覆该导电柱与该第一电子元件的封装层,之后移除该支撑板。
19.根据权利要求10所述的电子封装件的制法,其特征为,该第一电子元件先接置于该支撑板上,接着于该支撑板上形成包覆该导电柱及该第一电子元件的封装层,然后于该封装层上形成电性连接该导电柱与该第一电子元件的该线路结构,再于该线路结构上接置该第二电子元件,之后移除该支撑板。
20.根据权利要求10所述的电子封装件的制法,其特征为,该导电体为焊锡材、金属柱或其二者组合。
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Publication number Priority date Publication date Assignee Title
EP3449502B1 (en) 2016-04-26 2021-06-30 Linear Technology LLC Mechanically-compliant and electrically and thermally conductive leadframes for component-on-package circuits
US10497635B2 (en) 2018-03-27 2019-12-03 Linear Technology Holding Llc Stacked circuit package with molded base having laser drilled openings for upper package
US11410977B2 (en) 2018-11-13 2022-08-09 Analog Devices International Unlimited Company Electronic module for high power applications
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US11844178B2 (en) 2020-06-02 2023-12-12 Analog Devices International Unlimited Company Electronic component
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733419A (zh) * 2013-12-20 2015-06-24 乾坤科技股份有限公司 三维空间封装结构及其制造方法
CN106328632A (zh) * 2015-07-03 2017-01-11 矽品精密工业股份有限公司 电子封装件及其制法
CN106449588A (zh) * 2015-08-05 2017-02-22 联发科技股份有限公司 半导体封装、半导体设备及半导体封装的制造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101651362B1 (ko) * 2015-05-22 2016-08-25 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조 방법 및 이를 이용한 반도체 패키지
KR20170085833A (ko) * 2016-01-15 2017-07-25 삼성전기주식회사 전자 부품 패키지 및 그 제조방법
KR101799668B1 (ko) * 2016-04-07 2017-11-20 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제조 방법
US11569176B2 (en) * 2017-03-21 2023-01-31 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device and method of manufacturing thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104733419A (zh) * 2013-12-20 2015-06-24 乾坤科技股份有限公司 三维空间封装结构及其制造方法
CN106328632A (zh) * 2015-07-03 2017-01-11 矽品精密工业股份有限公司 电子封装件及其制法
CN106449588A (zh) * 2015-08-05 2017-02-22 联发科技股份有限公司 半导体封装、半导体设备及半导体封装的制造方法

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