CN105448936A - 一种阵列基板及其制作方法、显示装置 - Google Patents

一种阵列基板及其制作方法、显示装置 Download PDF

Info

Publication number
CN105448936A
CN105448936A CN201610006819.8A CN201610006819A CN105448936A CN 105448936 A CN105448936 A CN 105448936A CN 201610006819 A CN201610006819 A CN 201610006819A CN 105448936 A CN105448936 A CN 105448936A
Authority
CN
China
Prior art keywords
active layer
array base
insulating barrier
base palte
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610006819.8A
Other languages
English (en)
Other versions
CN105448936B (zh
Inventor
林子锦
赵海生
彭志龙
孙东江
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Beijing BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN201610006819.8A priority Critical patent/CN105448936B/zh
Publication of CN105448936A publication Critical patent/CN105448936A/zh
Priority to US15/537,209 priority patent/US20170373099A1/en
Priority to PCT/CN2016/093240 priority patent/WO2017118004A1/zh
Application granted granted Critical
Publication of CN105448936B publication Critical patent/CN105448936B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Nonlinear Science (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明公开了一种阵列基板及其制作方法、显示装置，主要内容包括：在有源层的一表面设置有栅绝缘层，另外一表面设置有阻隔绝缘层，从而，能够很好的将有源层与相邻其他第一导电层隔绝，进而，避免了有源层的残留物搭接任一第一导电层，尤其有效避免了有源层的残留物搭接像素电极与数据线的情况，从而，解决了搭接所造成的TFT电学不良的问题。同时，由于增加了阻隔绝缘层，且该膜层的厚度可适当调整，从而，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，因而，在膜层表面的坡度角较小的情况下，能够使得后续膜层更好的沉积，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。

Description

一种阵列基板及其制作方法、显示装置
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法、显示装置。
背景技术
现有技术中，有源层(半导体层)的制备工艺可以同时沉积SiNx、a-Si、N+a-Si，然后对沉积的混合膜层进行构图工艺，形成图案化的有源层。
然而，在具体的制备工艺过程中，由于制备环境、设备或其他异常原因，不可避免会导致混合膜层上附着尘埃、碎屑等异物，这些异物可在沉积过程中附着，也可在涂胶过程或在刻蚀的时候附着。在进行干刻工艺的时候，由于混合膜层的某些位置处有异物，导致干刻所用的气体无法与膜层接触反应，致使膜层出现残留物，进而，如图1所示，在后续制作源漏极11以及像素电极12的时候，当有源层13的残留物a足够大，就有可能会导致该残留物a在数据线14与像素电极12之间建立电连接，参照图1所示，这种电连接容易造成TFT电学性工艺不良。
发明内容
本发明实施例提供一种阵列基板及其制作方法、显示装置，用以解决现有技术中存在由于有源层的残留物与导电层接触而造成TFT电学性工艺不良的问题。
本发明实施例采用以下技术方案：
一种阵列基板，包括：栅绝缘层，有源层，与所述有源层接触的源漏极，第一导电层，还包括：阻隔绝缘层；
其中，所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有镂空结构；所述阻隔绝缘层用于阻隔所述有源层的残留物与任一第一导电层的接触。
该阵列基板中的阻隔绝缘层，可以有效阻隔所述有源层的残留物分别连接所述数据线和所述像素电极，避免TFT电学性工艺不良。而且，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。
可选地，所述阻隔绝缘层在所述像素电极所在区域具有镂空结构。
该结构可以提升阵列基板的透过率。
可选地，所述第一导电层包括数据线、像素电极、栅线、公共电极中的任意一种。
该阻隔绝缘层可以避免有源层的残留物与多种类型的第一导电层的搭接。
可选地，所述阵列基板为底栅结构阵列基板；
其中，所述栅绝缘层位于所述栅线之上且覆盖所述阵列基板；
所述有源层位于所述栅绝缘层之上；
所述阻隔绝缘层位于所述有源层之上或与所述有源层齐平设置，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出所述有源层；
所述源漏极位于所述绝缘阻隔层之上，且与暴露出的有源层相接触。
针对底栅结构阵列基板，可以有效阻隔有源层的残留物分别连接数据线和像素电极等第一导电层，避免TFT电学性工艺不良。
可选地，所述阵列基板为顶栅结构阵列基板；
其中，所述阻隔绝缘层位于所述源漏极之上，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出所述源漏极；
所述有源层位于所述阻隔绝缘层之上，且与暴露出的所述源漏极相接触；
所述栅绝缘层位于所述有源层之上且覆盖所述阵列基板；
所述栅线位于所述栅绝缘层之上。
针对顶栅结构阵列基板，可以有效阻隔有源层的残留物分别连接数据线和像素电极等第一导电层，避免TFT电学性工艺不良。
可选地，所述阻隔绝缘层的材质包括；树脂。
可选地，所述阻隔绝缘层的材质为感光树脂。
该材质可以有效阻隔所述有源层的残留物分别连接所述数据线和所述像素电极，避免TFT电学性工艺不良。而且，还可以简化制作工艺流程。
一种阵列基板的制作方法，包括：形成栅绝缘层，形成第一图案化的有源层，形成与所述有源层接触的第二图案化的源漏极，第三图案化的第一导电层，还包括：形成第四图案化的阻隔绝缘层；
其中，所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有镂空结构；所述阻隔绝缘层用于阻隔所述有源层的残留物至少搭接任一第一导电层。
通过该方法形成阻隔绝缘层，可以有效阻隔所述有源层的残留物分别连接所述数据线和所述像素电极，避免TFT电学性工艺不良。而且，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。
可选地，所述阵列基板为底栅结构阵列基板，则所述阵列基板的制作方法包括：
在栅极之上形成覆盖所述阵列基板的栅绝缘层；
在所述栅绝缘层之上形成第一图案化的有源层；
在所述有源层之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出有源层；
在所述阻隔绝缘层之上形成第二图案化的源漏极，以使得所述源漏极与暴露出的有源层相接触。
针对底栅结构阵列基板，可以有效阻隔有源层的残留物分别连接数据线和像素电极等第一导电层，避免TFT电学性工艺不良。
可选地，所述阵列基板为顶栅结构阵列基板，则所述阵列基板的制作方法包括：
在第二图案化的源漏极之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出所述源漏极；
在所述阻隔绝缘层之上形成第一图案化的有源层，以使得所述有源层与暴露出的源漏极相接触；
在所述有源层之上形成覆盖所述阵列基板的栅绝缘层；
在所述栅绝缘层之上形成栅线。
针对顶栅结构阵列基板，可以有效阻隔有源层的残留物分别连接数据线和像素电极等第一导电层，避免TFT电学性工艺不良。
一种显示装置，包括所述的阵列基板。
在本发明实施例中，有源层的一表面设置有栅绝缘层，另一表面设置有阻隔绝缘层，该阻隔绝缘层可以有效阻隔所述有源层的残留物分别连接所述数据线和所述像素电极，避免TFT电学性工艺不良。而且，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为现有技术中有源层的残留物与数据线以及像素电极搭接的示意图；
图2(a)为本发明所涉及的阵列基板为底栅结构阵列基板的结构示意图之一；
图2(b)为本发明所涉及的阵列基板为底栅结构阵列基板的结构示意图之二；
图3为本发明所涉及的阵列基板为顶栅结构阵列基板的结构示意图；
图4为本发明实施例提供的底栅结阵列基板的制作方法的步骤流程图；
图5为本发明实施例提供的顶栅结阵列基板的制作方法的步骤流程图。
具体实施方式
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步地详细描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其它实施例，都属于本发明保护的范围。
下面通过具体的实施例对本发明所涉及的技术方案进行详细的描述，本发明包括但并不限于以下实施例。
本发明提供了一种阵列基板，该阵列基板主要包括：栅绝缘层，有源层，与所述有源层接触的源漏极，第一导电层，此外，该阵列基板还包括：阻隔绝缘层；其中，该栅绝缘层位于有源层的一表面，阻隔绝缘层位于有源层的另一表面，且阻隔绝缘层至少在有源层与源漏极的接触区域具有镂空结构；阻隔绝缘层用于阻隔有源层的残留物与任一第一导电层的接触。该阵列基板的结构中，除有源层的一表面设置有栅绝缘层之外，另外一表面(除有源层与源漏极的接触区域外)还设置有阻隔绝缘层，从而，能够很好的将有源层与相邻其他第一导电层隔绝，进而，避免了有源层的残留物搭接任一第一导电层，尤其有效避免了有源层的残留物搭接像素电极与数据线的情况，从而，解决了搭接所造成的TFT电学不良的问题。同时，由于增加了阻隔绝缘层，且该膜层的厚度可适当调整，从而，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，因而，在膜层表面的坡度角较小的情况下，能够使得后续膜层更好的沉积，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。
其中，本发明实施例中所涉及的第一导电层包括数据线、像素电极、栅线、公共电极中的任意一种。
可选地，该阻隔绝缘层在所述像素电极所在区域具有镂空结构。从而，在保证阻隔绝缘层能够较好的阻隔有源层的残留物与其他第一导电层搭接，同时，还能够通过在像素电极所在区域形成的镂空结构提升整个阵列基板的透过率。
以下通过具体的实例对本发明所涉及的几种方案进行详细介绍。
首先，如图2(a)所示，为本发明所涉及的阵列基板为底栅结构阵列基板的一种结构示意图，该阵列基板中，栅线22位于衬底基板21之上，栅绝缘层23位于栅线22之上且覆盖阵列基板，有源层24位于栅绝缘层23之上，阻隔绝缘层25位于有源层24之上，阻隔绝缘层25在有源层24与源漏极26的接触区域S通过镂空结构暴露出有源层24(假设形成的有源层24存在残留物a)，源漏极26位于阻隔绝缘层25之上，且与暴露出的有源层24相接触。此外，像素电极27与源漏极26搭接接触，且阻隔绝缘层25阻隔了像素电极27与下方可能存在的残留物a的搭接。其中，在该结构中，阻隔绝缘层25在有源层24与源漏极26的接触区域S呈现出的镂空结构具体为过孔，源漏极26分别通过过孔与下层的有源层24接触，从而保证薄膜晶体管特性。
此外，如图2(b)所示，为本发明所涉及的阵列基板为底栅结构阵列基板的另一种结构示意图，该阵列基板与图2(a)的阵列基板的结构类似，区别在于：阻隔绝缘层25与有源层24齐平设置，阻隔绝缘层25在有源层24与源漏极26的接触区域S通过镂空结构暴露出有源层24，使得源漏极26分别与有源层24接触，从而保证薄膜晶体管特性。
其次，如图3所示，为本发明所涉及的阵列基板为顶栅结构阵列基板的一种结构示意图，该阵列基板中，源漏极32位于衬底基板31之上，阻隔绝缘层33位于源漏极32之上，阻隔绝缘层33在有源层34与源漏极32的接触区域S通过镂空结构暴露出源漏极32；有源层34位于阻隔绝缘层33之上，且与暴露出的源漏极32相接触；栅绝缘层35位于有源层34之上且覆盖阵列基板；栅线36位于栅绝缘层35之上。此外，在源漏极32的同一膜层，还设置有像素电极37，且与源漏极32搭接接触。
在上述三种阵列基板的结构膜层中，若在形成有源层时，尤其是在沉积过程或刻蚀过程中，膜层表面附着有尘埃或碎屑等异物，则会导致形成的有源层在其他本应该被刻蚀掉的区域保留有残留物，而本发明通过在有源层(底栅结构)或源漏极(顶栅结构)之上形成阻隔绝缘层，该阻隔绝缘层在有源层与源漏极的接触区域保留有镂空结构，从而，保证TFT有效性；同时，该阻隔绝缘层的存在有效阻隔了有源层与相邻其他膜层的接触，进而，避免了有源层的残留物搭接任一第一导电层，尤其有效避免了有源层的残留物搭接像素电极(其中，该像素电极位于源漏极之上或之下，且像素电极与漏极相搭接，鉴于阻隔绝缘层的存在，阻隔了残留物与像素电极搭接)与数据线的情况，从而，解决了搭接结构所造成的TFT电学不良的问题。同时，由于增加了阻隔绝缘层，且该膜层的厚度可适当调整，从而，降低了膜层形成有源层后整个阵列基板的膜层表面的高度差，提升了膜层表面的平整性，因而，在膜层表面的坡度角较小的情况下，能够使得后续膜层更好的沉积，减少因膜层表面高度差较大或坡度角较大而造成的膜层断裂现象。
可选地，在本发明实施例中，阻隔绝缘层的材质选择为树脂。由于树脂材料具有较好的绝缘性，能够很好的阻隔有源层的残留物与其他第一导电层的搭接。
进一步，阻隔绝缘层的材质为感光树脂。由于感光树脂在光照情况下能够很好的分解，因此，在对该阻隔绝缘层进行图案化时，只需对相应的区域进行曝光、显影即可溶解，得到所需的图案。从而，简化了工艺流程，避免了使用其他不感光的材质而需要光刻胶的参与而造成的工艺流程繁琐的问题。
与上述阵列基板属于同一发明构思，本发明还提供了一种阵列基板的制作方法，下面以具体的实施例进行描述。
本发明实施例提供的一种阵列基板的制作方法主要包括以下步骤，需要说明的是，以下步骤并不体现明显的制作顺序：形成栅绝缘层；形成第一图案化的有源层；形成与所述有源层接触的第二图案化的源漏极，第三图案化的第一导电层；此外，还包括：形成第四图案化的阻隔绝缘层，其中，栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有镂空结构；所述阻隔绝缘层用于阻隔所述有源层的残留物至少搭接任一第一导电层。
需要说明的是，本发明以下实施例提到的构图工艺至少包括光刻胶涂覆或滴注、曝光、显影、光刻刻蚀等步骤。
下面根据阵列基板的类型分别对本发明所涉及的阵列基板的制作方法进行具体介绍。
可选地，该阵列基板为底栅结构阵列基板，结合图4所示本发明实施例提供的底栅结阵列基板的制作方法的步骤流程图，该方法主要包括以下步骤：
步骤41：在栅极之上形成覆盖阵列基板的栅绝缘层。
其实，在该步骤41之前，还包括在衬底基板上形成栅极的步骤，其形成过程与现有技术类似，在此不作描述。具体地，该步骤41中可采用物理沉积方式或化学沉积方式在整个阵列基板上沉积一层或多层绝缘层形成栅绝缘层，该栅绝缘层覆盖住栅极以及阵列基板。形成栅极绝缘层的方法不限，栅极绝缘层的材料不限。
步骤42：在栅绝缘层之上形成第一图案化的有源层。
具体地，首先，在形成有所述栅极和栅极绝缘的阵列基板之上采用化学气相沉积法或热蒸镀等方法沉积一半导体层，其中，该半导体层中一般由先后顺序依次沉积SiNx，a-Si，N+a-Si，然后，在形成有所述半导体层的阵列基板上形成一层设定厚度的光刻胶层，此时光刻胶层覆盖整个用于形成有源层的半导体层；通过第一掩模板对光刻胶层进行曝光和显影，保留待形成的有源层正上方的光刻胶，其余位置的光刻胶完全去除，然后，对暴露出的半导体层进行刻蚀，最后将保留的光刻胶剥离，暴露出保留的半导体层作为第一图案化的有源层。其中，本发明所涉及的光刻胶可以为正性光刻胶也可以为负性光刻胶。
步骤43：在有源层之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，其中，阻隔绝缘层在有源层与源漏极的接触区域通过镂空结构暴露出有源层。
基于上述步骤42形成的有源层，考虑到在形成有源层的过程中可能会有残留物，为了避免残留物与其他第一导电层的搭接而导致TFT电性不良的问题，该步骤43在形成第一图案化的有源层之上，利用物理气相沉积或化学气相沉积工艺沉积一层或多层绝缘层，并利用构图工艺形成第五图案化的阻隔绝缘层，该阻隔绝缘层在有源层与源漏极的接触区域通过镂空结构暴露出有源层。
可选地，在利用构图工艺形成第五图案化的阻隔绝缘层时，可根据绝缘材料的类型选择以下方式之一进行：
方式一：
若此时绝缘层为非感光树脂，针对沉积有绝缘层的阵列基板，在该绝缘层之上形成一层设定厚度的光刻胶(例如为正性光刻胶)，利用第五图案化的掩膜板对绝缘层中对应有源层区域的光刻胶进行曝光，之后，对经过曝光处理的阵列基板进行显影处理，将经过曝光处理的光刻胶剥离，对剥离光刻胶的区域处的绝缘层进行刻蚀处理，并剥离对应有源层区域的光刻胶，暴露出有源层，形成第五图案化的阻隔绝缘层。
方式二：
若此时绝缘层为感光树脂，针对沉积有绝缘层的阵列基板，不需要在该绝缘层之上形成一层设定厚度的光刻胶，直接利用第五图案化的掩膜板对绝缘层中对应有源层区域的感光树脂进行曝光，之后，对经过曝光处理的阵列基板进行显影处理，将经过曝光处理的感光树脂溶解掉，最终暴露出有源层，形成第五图案化的阻隔绝缘层。
综上，两种方式都可以形成所需图案化的阻隔绝缘层，然而，方式二中利用感光树脂的方案更为便捷，不需要涂布光刻胶以及对光刻胶的剥离处理，从而，简化了制备流程。
步骤44：在阻隔绝缘层之上形成第二图案化的源漏极，以使得源漏极与暴露出的有源层相接触。
之后，在形成有第五图案化的阻隔绝缘层之上，形成互不接触且均通过过孔或暴露出的有源层表面与有源层连接的源漏极。
可选地，所述阵列基板为顶栅结构阵列基板，结合图5所示本发明实施例提供的顶栅结阵列基板的制作方法的步骤流程图，该方法主要包括以下步骤：
步骤51：在第二图案化的源漏极之上沉积绝缘材料，利用构图工艺形成第六图案化的阻隔绝缘层，其中，隔绝缘层在有源层与源漏极的接触区域通过镂空结构暴露出源漏极。
可选地，在该步骤51之前，还包括在衬底基板上形成第二图案化的源漏极的步骤，该源漏极的形成与现有技术类似，源漏极材料也与现有技术相同。
具体地，在第二图案化的源漏极之上利用上述沉积工艺沉积绝缘材料，并利用与步骤43类似的构图工艺形成第六图案化的阻隔绝缘层，该阻隔绝缘层在有源层与源漏极的接触区域通过镂空结构暴露出源漏极。例如，结合图3所示的结构，利用第六图案化的掩膜板，在绝缘层上对应有源层的区域形成具有两个过孔的镂空结构，从而，通过这两个过孔分别暴露出源极和漏极，即源漏极。
步骤52：在阻隔绝缘层之上形成第一图案化的有源层，以使得有源层与暴露出的源漏极相接触。
基于步骤51形成的具有两个过孔的阻隔绝缘层，沉积一半导体层，该半导体层在两个过孔的位置分别与源漏极接触，然后，对该半导体层进行构图工艺形成第一图案化的有源层。该步骤与步骤42类似。由此可见，即使在该步骤中形成有源层的残留物，鉴于阻隔绝缘层的存在，也不会造成该残留物与像素电极或其他的第一导电层搭接，从而，很好的保证了TFT的电学良性。
步骤53：在有源层之上形成覆盖所述阵列基板的栅绝缘层。
步骤54：在栅绝缘层之上形成栅线。
需要说明的是，在本发明实施例中，仅示出了必要的膜层结构，其中，有源层的残留物可能会在数据线与像素电极之间建立连接，即搭接数据线与像素电极，此外，还有可能会在数据线与公共电极之间建立连接，以及其他的第一导电层，例如：栅线等，本发明并不一一列举搭接所发生的具***置。
另外，在制备阵列基板的过程中，像素电极与源漏极的制备顺序可以互换，本发明并不对此进行具体限定。
综上，以上两种制备方案均示出了主要的工艺流程，其实，还包括一些其他膜层的制备，本发明在此不作描述。
同时，在本发明实例中，还提供了一种显示装置，该显示装置主要包括上述实施例中的各类阵列基板，其中，所述显示装置可以为液晶面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本发明的限制。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。

Claims (11)

1.一种阵列基板，包括：栅绝缘层，有源层，与所述有源层接触的源漏极，第一导电层，其特征在于，还包括：阻隔绝缘层；
其中，所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有镂空结构；所述阻隔绝缘层用于阻隔所述有源层在所述镂空结构所在区域之外的残留物与所述第一导电层的接触。
2.如权利要求1所述的阵列基板，其特征在于，所述阻隔绝缘层在所述像素电极所在区域具有镂空结构。
3.如权利要求1或2所述的阵列基板，其特征在于，所述第一导电层包括数据线、像素电极、栅线以及公共电极中任意一种。
4.如权利要求3所述的阵列基板，其特征在于，所述阵列基板为底栅结构阵列基板；
其中，所述栅绝缘层位于所述栅线之上且覆盖所述阵列基板；
所述有源层位于所述栅绝缘层之上；
所述阻隔绝缘层位于所述有源层之上或与所述有源层齐平设置，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出所述有源层；
所述源漏极位于所述绝缘阻隔层之上，且与暴露出的有源层相接触。
5.如权利要求3所述的阵列基板，其特征在于，所述阵列基板为顶栅结构阵列基板；
其中，所述阻隔绝缘层位于所述源漏极之上，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出所述源漏极；
所述有源层位于所述阻隔绝缘层之上，且与暴露出的所述源漏极相接触；
所述栅绝缘层位于所述有源层之上且覆盖所述阵列基板；
所述栅线位于所述栅绝缘层之上。
6.如权利要求1或2所述的阵列基板，其特征在于，所述阻隔绝缘层的材质包括：树脂。
7.如权利要求5所述的阵列基板，其特征在于，所述阻隔绝缘层的材质为感光树脂。
8.一种阵列基板的制作方法，包括：形成栅绝缘层，形成第一图案化的有源层，形成与所述有源层接触的第二图案化的源漏极，第三图案化的第一导电层，其特征在于，还包括：形成第四图案化的阻隔绝缘层；
其中，所述栅绝缘层位于所述有源层的一表面，所述阻隔绝缘层位于所述有源层的另一表面，且所述阻隔绝缘层至少在所述有源层与所述源漏极的接触区域具有镂空结构；所述阻隔绝缘层用于阻隔所述有源层的残留物至少搭接任一导电层。
9.如权利要求8所述的方法，其特征在于，所述阵列基板为底栅结构阵列基板，则所述阵列基板的制作方法包括：
在栅极之上形成覆盖所述阵列基板的栅绝缘层；
在所述栅绝缘层之上形成第一图案化的有源层；
在所述有源层之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出有源层；
在所述阻隔绝缘层之上形成第二图案化的源漏极，以使得所述源漏极与暴露出的有源层相接触。
10.如权利要求8所述的方法，其特征在于，所述阵列基板为顶栅结构阵列基板，则所述阵列基板的制作方法包括：
在第二图案化的源漏极之上沉积绝缘材料，利用构图工艺形成第五图案化的阻隔绝缘层，其中，所述阻隔绝缘层在所述有源层与所述源漏极的接触区域通过镂空结构暴露出所述源漏极；
在所述阻隔绝缘层之上形成第一图案化的有源层，以使得所述有源层与暴露出的源漏极相接触；
在所述有源层之上形成覆盖所述阵列基板的栅绝缘层；
在所述栅绝缘层之上形成栅线。
11.一种显示装置，其特征在于，包括权利要求1-7任一项所述的阵列基板。
CN201610006819.8A 2016-01-04 2016-01-04 一种阵列基板及其制作方法、显示装置 Expired - Fee Related CN105448936B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
CN201610006819.8A CN105448936B (zh) 2016-01-04 2016-01-04 一种阵列基板及其制作方法、显示装置
US15/537,209 US20170373099A1 (en) 2016-01-04 2016-08-04 Array substrate, manufacturing method thereof and display device
PCT/CN2016/093240 WO2017118004A1 (zh) 2016-01-04 2016-08-04 阵列基板及其制作方法以及显示装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610006819.8A CN105448936B (zh) 2016-01-04 2016-01-04 一种阵列基板及其制作方法、显示装置

Publications (2)

Publication Number Publication Date
CN105448936A true CN105448936A (zh) 2016-03-30
CN105448936B CN105448936B (zh) 2019-07-23

Family

ID=55558949

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610006819.8A Expired - Fee Related CN105448936B (zh) 2016-01-04 2016-01-04 一种阵列基板及其制作方法、显示装置

Country Status (3)

Country Link
US (1) US20170373099A1 (zh)
CN (1) CN105448936B (zh)
WO (1) WO2017118004A1 (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017118004A1 (zh) * 2016-01-04 2017-07-13 京东方科技集团股份有限公司 阵列基板及其制作方法以及显示装置
CN109300915A (zh) * 2018-09-30 2019-02-01 厦门天马微电子有限公司 一种阵列基板、显示面板和显示装置
CN110416257A (zh) * 2018-07-13 2019-11-05 广东聚华印刷显示技术有限公司 显示面板背板结构、其制备方法及顶发射型显示面板
CN110828485A (zh) * 2019-11-19 2020-02-21 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100258805A1 (en) * 2009-04-10 2010-10-14 Toppan Printing Co., Ltd. Thin Film Transistor and Image Display Unit
US20130075766A1 (en) * 2011-09-22 2013-03-28 Che-Chia Chang Thin film transistor device and pixel structure and driving circuit of a display panel
CN103579219A (zh) * 2012-07-27 2014-02-12 北京京东方光电科技有限公司 一种平板阵列基板、传感器及平板阵列基板的制造方法
JP2014039010A (ja) * 2012-07-19 2014-02-27 Jsr Corp 半導体素子、感放射線性樹脂組成物、硬化膜および表示素子
CN103681488A (zh) * 2013-12-16 2014-03-26 合肥京东方光电科技有限公司 阵列基板及其制作方法，显示装置
CN103928400A (zh) * 2014-03-31 2014-07-16 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2776360B2 (ja) * 1996-02-28 1998-07-16 日本電気株式会社 薄膜トランジスタアレイ基板の製造方法
CN100517075C (zh) * 2006-03-09 2009-07-22 北京京东方光电科技有限公司 一种薄膜晶体管液晶显示器的阵列基板的制作方法
TWI534905B (zh) * 2010-12-10 2016-05-21 半導體能源研究所股份有限公司 顯示裝置及顯示裝置之製造方法
US20160204134A1 (en) * 2015-01-13 2016-07-14 Shenzhen China Star Optoelectronics Technology Co. Ltd. An Array Substrate Manufacturing Method, An Array Substrate And A Display Panel
CN105448936B (zh) * 2016-01-04 2019-07-23 京东方科技集团股份有限公司 一种阵列基板及其制作方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100258805A1 (en) * 2009-04-10 2010-10-14 Toppan Printing Co., Ltd. Thin Film Transistor and Image Display Unit
US20130075766A1 (en) * 2011-09-22 2013-03-28 Che-Chia Chang Thin film transistor device and pixel structure and driving circuit of a display panel
JP2014039010A (ja) * 2012-07-19 2014-02-27 Jsr Corp 半導体素子、感放射線性樹脂組成物、硬化膜および表示素子
CN103579219A (zh) * 2012-07-27 2014-02-12 北京京东方光电科技有限公司 一种平板阵列基板、传感器及平板阵列基板的制造方法
CN103681488A (zh) * 2013-12-16 2014-03-26 合肥京东方光电科技有限公司 阵列基板及其制作方法，显示装置
CN103928400A (zh) * 2014-03-31 2014-07-16 京东方科技集团股份有限公司 阵列基板及其制作方法、显示装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017118004A1 (zh) * 2016-01-04 2017-07-13 京东方科技集团股份有限公司 阵列基板及其制作方法以及显示装置
CN110416257A (zh) * 2018-07-13 2019-11-05 广东聚华印刷显示技术有限公司 显示面板背板结构、其制备方法及顶发射型显示面板
CN109300915A (zh) * 2018-09-30 2019-02-01 厦门天马微电子有限公司 一种阵列基板、显示面板和显示装置
CN110828485A (zh) * 2019-11-19 2020-02-21 京东方科技集团股份有限公司 一种显示基板及其制备方法、显示装置

Also Published As

Publication number Publication date
US20170373099A1 (en) 2017-12-28
CN105448936B (zh) 2019-07-23
WO2017118004A1 (zh) 2017-07-13

Similar Documents

Publication Publication Date Title
US11257957B2 (en) Thin film transistor, method of fabricating the same, array substrate and display device
CN100421017C (zh) 薄膜晶体管阵列基板及其制造方法
CN101677058B (zh) 薄膜构造体的制造方法
CN105161505A (zh) 一种阵列基板及其制作方法、显示面板
CN105161495B (zh) 一种阵列基板及其制作方法、显示面板
CN102655155A (zh) 阵列基板及其制造方法和显示装置
US20170271368A1 (en) Display substrate, manufacturing method for the same, and display device
CN105097839B (zh) 一种绝缘层、阵列基板及其制作方法、显示装置
CN102842587B (zh) 阵列基板及其制作方法、显示装置
CN107230661A (zh) 一种阵列基板及其制备方法、显示装置
CN105448936A (zh) 一种阵列基板及其制作方法、显示装置
JP2012003266A (ja) マザーボード及びアレイ基板の製造方法
CN103928400A (zh) 阵列基板及其制作方法、显示装置
CN104465510A (zh) 一种阵列基板及其制作方法和显示面板
CN104241296B (zh) 一种阵列基板及其制作方法和显示装置
CN104133313A (zh) 阵列基板及其制备方法、液晶显示装置
CN103424925B (zh) 一种阵列基板及其制造方法、显示装置
CN107195635A (zh) 薄膜晶体管阵列基板及其制备方法
CN103489874A (zh) 阵列基板及其制备方法、显示装置
CN103681514A (zh) 阵列基板及其制作方法、显示装置
CN105529274A (zh) 薄膜晶体管的制作方法、阵列基板和显示装置
CN106873278A (zh) 阵列基板及其制作方法、显示装置
CN104617049A (zh) 一种阵列基板及其制作方法、显示装置
CN106129071A (zh) 一种阵列基板的制作方法及相应装置
US10818798B2 (en) Display panel, array substrate, thin film transistor and method for manufacturing the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190723

Termination date: 20210104

CF01 Termination of patent right due to non-payment of annual fee