CN105428251A - 半导体堆叠封装方法 - Google Patents
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 109
- 229910052751 metal Inorganic materials 0.000 claims abstract description 109
- 239000004033 plastic Substances 0.000 claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 43
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 20
- 238000012856 packing Methods 0.000 claims description 18
- 239000003223 protective agent Substances 0.000 claims description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 11
- 238000003466 welding Methods 0.000 description 7
- 238000010992 reflux Methods 0.000 description 5
- 239000000945 filler Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052809 inorganic oxide Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000009972 noncorrosive effect Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- MEYZYGMYMLNUHJ-UHFFFAOYSA-N tunicamycin Natural products CC(C)CCCCCCCCCC=CC(=O)NC1C(O)C(O)C(CC(O)C2OC(C(O)C2O)N3C=CC(=O)NC3=O)OC1OC4OC(CO)C(O)C(O)C4NC(=O)C MEYZYGMYMLNUHJ-UHFFFAOYSA-N 0.000 description 1
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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Abstract
本发明提供一种半导体堆叠封装方法,包括:在基板上表面形成金属柱凸点,金属柱凸点的上表面高于待装载的第一芯片的上表面;将第一芯片倒装于基板的上表面;在基板上表面形成第一塑封层,第一塑封层露出金属柱凸点的顶部;将第二芯片的功能区连接至金属柱凸点;在第一塑封层的上表面形成第二塑封层,第二塑封层包覆第二芯片;在基板的下表面形成焊球或者可焊接膜层。本发明通过在基板上形成金属柱凸点实现互联,能够实现窄间距、高密度、大电流、低导通电阻等性能优势;在基板上形成金属柱凸点,能够简化封装工艺,减少回流次数,降低由于回流造成的基板涨缩等工艺风险;可以整条基板制作,提高生产效率,降低生产成本。
Description
技术领域
本发明涉及半导体制造技术方法领域,尤其是半导体堆叠封装方法。
背景技术
现有半导体堆叠封装技术中,常用锡球作为叠层的连接载体。锡球尺寸一般比较大,这样要求的间距也会大一些,以常规尺寸250微米锡球为例,间距通常需要350微米以上。这样在点阵密集时候,必须扩大封装体尺寸来满足要求。
发明内容
鉴于现有技术中的上述缺陷或不足,本发明提供了一种半导体堆叠封装方法。
本发明提供一种半导体堆叠封装方法,包括:
在基板上表面形成金属柱凸点,所述金属柱凸点的上表面高于待装载的第一芯片的上表面;
将所述第一芯片倒装于所述基板的上表面;
在所述基板上表面形成第一塑封层,所述第一塑封层露出所述金属柱凸点的顶部;
将第二芯片的功能区连接至所述金属柱凸点;
在所述第一塑封层的上表面形成第二塑封层,所述第二塑封层包覆所述第二芯片;
在所述基板的下表面形成焊球或者可焊接膜层。
相比于现有技术,本发明的有益效果为:
本发明提供的一种半导体堆叠封装方法,通过在基板上形成金属柱凸点实现互联,解除了现有封装技术中锡球互联的体积等限制问题,能够实现窄间距、高密度、大电流、低导通电阻等性能优势;在基板上形成金属柱凸点,能够简化封装工艺,减少回流次数,降低由于回流造成的基板涨缩等工艺风险;可以整条基板制作,提高生产效率,降低生产成本。
附图说明
通过阅读参照以下附图所作的对非限制性实施例所作的详细描述,本申请的其它特征、目的和优点将会变得更明显:
图1为本发明提供的半导体堆叠封装方法的流程示意图;
图2-图9为本发明提供的半导体堆叠封装方法的过程示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释相关发明,而非对该发明的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与发明相关的部分。
需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
参照图1,本发明提供了一种半导体堆叠封装方法,包括步骤:
S1:在基板上表面形成金属柱凸点,金属柱凸点的上表面高于待装载的第一芯片的上表面;
S2:将第一芯片倒装于基板上表面;
S3:在基板上表面形成第一塑封层,第一塑封层露出金属柱凸点的顶部;
S4:将第二芯片的功能区连接至金属柱凸点;
S5:在第一塑封层的上表面形成第二塑封层,第二塑封层包覆第二芯片;
S6:在基板的下表面形成焊球或者可焊接膜层。
实施步骤S1,如图2所示,在基板1的上表面形成金属柱凸点2,本申请中金属柱凸点的高度根据后续待装载的第一芯片的厚度而定。在基板的上表面形成金属柱凸点之前,先在基板的上表面布线以及形成焊盘,整条基板上形成多个图形,每个图形所在的区域分别对应形成半导体堆叠封装。在后续的封装中,基板上表面连接第一芯片;金属柱凸点位于每个图形边缘的焊盘上,代替现有技术中的锡球以连接后续待装载的第二芯片。
接着实施步骤S2,如图3所示,将第一芯片3倒装于基板1的上表面,金属柱凸点2的上表面高于第一芯片3的上表面。
作为一种可选的实施方式,如图2-图3所示,本申请中金属柱凸点2包括第一金属柱21以及设置于第一金属柱21上表面的第二金属柱22。
可选的,第一金属柱21的高度大于第二金属柱22的高度,且第一金属柱21的上表面不低于第一芯片3的上表面,这样的设置确保通过金属柱凸点连接第二芯片时,实现窄间距、高密度封装的同时能够有效地保证封装结构的物理稳定性。当然,在实际封装中,在保证整个封装的稳定性以及电气连接性能基础上,第一金属柱的上表面若稍微低于第一芯片的上表面的方式也可以实施。
进一步地,第一金属柱21的横截面不小于第二金属柱22的横截面。
进一步地,第二金属柱22的上表面为平面,即金属柱凸点2为平头凸点,用以避免接下来的模塑底部填充时塑封料流入,而影响金属柱凸点后续封装的焊接性能。
一般,凸点材料为具有高导电和高熔点的金属材料,如铜、锡。优选地,本申请中第一金属柱21优选为铜柱或者铜合金柱,第二金属柱22为锡柱或锡合金柱。
在后续的封装中,第二芯片的功能区倒装连接至金属柱凸点的表面时第二金属柱的顶部回流焊接。本发明中第一金属柱的高度大于第二金属柱,且第一金属柱的上表面不低于第一芯片的上表面,一方面有利于保证封装的稳定性,另一方面有利于保证良好的电性能以及第二芯片与金属柱凸点的表面相连接时的焊接性能。
本申请中在基板的上表面形成金属柱凸点实现互联,能够解除现有封装技术中锡球互联的体积等限制问题;并且使用两层不同材料的金属柱相连形成金属柱凸点相对于锡球有更好的电性能;此外,与第二芯片连接的第二金属柱为锡柱或锡合金柱,以确保第二芯片与金属柱凸点表面回流焊接的性能。
实施步骤S3,参照图4,在基板1上表面形成第一塑封层4,第一塑封层4露出金属柱凸点2的顶部,金属柱凸点2的高度高于第一塑封层4的高度是为了接下来的步骤中与第二芯片进行连接时使用。
本申请中,芯片的封装采用模塑底部填充技术,将第一芯片以塑封底填料固定于基板上并且包封在第一塑封层内部。
作为一种可选的实施方式,如图4-图5所示,在基板上表面形成第一塑封层4,第一塑封层4包覆第一芯片3和金属柱凸点2,第一塑封层4的上表面高于金属柱凸点2的上表面;对第一塑封层4的上表面进行打磨或蚀刻,露出第二金属柱22的部分高度,即锡柱或锡合金柱的顶部。
或者,如图5所示,在基板1上表面形成第一塑封层4,第一塑封层4填充于第一芯片3、金属柱凸点2以及基板1之间且包覆第一芯片3,即在形成第一塑封层4时就露出金属柱凸点2的顶部,无需对第一塑封层进行研磨或者等离子刻蚀等方式露出金属柱凸点的顶层;第一塑封层4的上表面高于第一芯片3的上表面且低于金属柱凸点2的上表面,即露出锡柱或锡合金柱的部分高度。
进一步地,实施步骤S4,如图6所示,将第二芯片5的功能区连接至金属柱凸点。其中,第二芯片的功能区为第二芯片的凸点;以倒装的方式将第二芯片的凸点与金属柱凸点对应连接,第二金属柱22的顶部回流焊接,通过金属柱凸点2形成互联,并且第二金属柱22设置在第一金属柱21的表面,第一金属柱设置于基板上,降低了由于回流造成的基板涨缩等工艺风险。
进一步地,实施步骤S5,参照图7,在第一塑封层4的上表面形成第二塑封层6,第二塑封层6包覆第二芯片5。
当然,第二芯片的封装也采用模塑底部填充技术,将第二芯片以塑封底填料包封在第二塑封层内部。将第一芯片3倒装连接在基板1上,采用模塑底部填充技术将其包封住,将第二芯片5倒装连接于金属柱凸点上,采用模塑底部填充技术将其包封住,上述填充并封装第一芯片和第二芯片的胶为一种塑封底填料,主要成分可为环氧树脂,包裹所述芯片,对填充胶进行加热固化,即可达到加固的目的,有保证了焊接工艺的电气安全性。
模塑底部填充技术是将成型化合物填充芯片的间隙并同时完成塑封,使得在芯片底部填充和成型一步完成,减少了制造的时间,并且提高了机械稳定性;模塑底部填充技术能够降低成本,提高可靠性。
作为一种可选的实施方式,在基板上表面形成金属柱凸点之后,还在金属柱凸点上表面镀锡保护剂;将第二芯片的功能区连接至金属柱凸点之前,去除金属柱凸点上表面的锡保护剂。
进一步地,锡保护剂为有机或无机保焊膜。在所述金属柱凸点上表面生成一层有机或者无机氧化膜,这层膜具有防氧化,耐热,耐湿的特性,可以保护金属柱凸点上表面在常态下不生锈,为后续的工艺打下良好的基础,同时,在后续的焊接高温中,所述氧化膜很容易被助焊剂所清除,露出干净的金属柱凸点上表面并且在很短的时间内与熔融的焊锡结合成为牢固的焊点。
接着,实施步骤S6,在基板的下表面形成焊球或者可焊接膜层。如图8所示,在基板1下表面形成了焊球7,在基板下表面形成焊球为了便于以后焊接于印刷电路板上,除了布置焊球之外,还可以形成可焊接膜层,效果与焊球类似。
基板上设置有多个图形区域,以方便在整条基板同时制作多个封装体。最后,对半导体和基板焊接形成的封装进行切割、包装等工艺,如图9所示为本发明堆叠封装结构的示意图。通过第一塑封层4将第一芯片3封装固定于基板1上,通过第二塑封层6将第二芯片5封装固定,第二芯片5的凸点连接金属柱凸点的顶部以实现互联。
本发明提供的方法中通过在基板上形成金属柱凸点实现互联,解决了现有半导体堆叠中锡球互联的体积等限制问题,在第一金属柱(铜柱或铜合金柱)上表面设置第二金属柱(锡柱或锡合金柱)形成金属柱凸点,相比于单纯的锡球互联具有更好的电性能,能够实现窄间距、高密度、大电流、低导通电阻等性能优势;在基板上形成金属柱凸点,能够简化封装工艺,减少回流次数,降低由于回流造成的基板涨缩等工艺风险;可以整条基板制作,提高生产效率,降低生产成本;此外,通过塑封底填料将第一芯片和第二芯片固定并包裹,减少了传统半导体堆叠封装中封装体翘曲的问题。
以上描述仅为本申请的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解,本申请中所涉及的发明范围,并不限于上述技术特征的特定组合而成的技术方案,同时也应涵盖在不脱离所述发明构思的情况下,由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本申请中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
Claims (10)
1.一种半导体堆叠封装方法,其特征在于,包括:
在基板上表面形成金属柱凸点,所述金属柱凸点的上表面高于待装载的第一芯片的上表面;
将所述第一芯片倒装于所述基板的上表面;
在所述基板上表面形成第一塑封层,所述第一塑封层露出所述金属柱凸点的顶部;
将第二芯片的功能区连接至所述金属柱凸点;
在所述第一塑封层的上表面形成第二塑封层,所述第二塑封层包覆所述第二芯片;
在所述基板的下表面形成焊球或者可焊接膜层。
2.根据权利要求1所述的半导体堆叠封装方法,其特征在于,
所述金属柱凸点包括第一金属柱以及设置于所述第一金属柱上表面的第二金属柱。
3.根据权利要求2所述的半导体堆叠封装方法,其特征在于,
所述第一金属柱的高度大于所述第二金属柱的高度,且所述第一金属柱的上表面不低于所述第一芯片的上表面。
4.根据权利要求2所述的半导体堆叠封装方法,其特征在于,
所述第一金属柱的横截面不小于所述第二金属柱的横截面。
5.根据权利要求2所述的半导体堆叠封装方法,其特征在于,所述第二金属柱的上表面为平面。
6.根据权利要求2所述的半导体堆叠封装方法,其特征在于,所述第一金属柱为铜柱或铜合金柱,所述第二金属柱为锡柱或锡合金柱。
7.根据权利要求2所述的半导体堆叠封装方法,其特征在于,
在所述基板上表面形成第一塑封层,所述第一塑封层包覆所述第一芯片和所述金属柱凸点,所述第一塑封层的上表面高于所述金属柱凸点的上表面;
对所述第一塑封层的上表面进行打磨或蚀刻,露出所述第二金属柱的部分高度。
8.根据权利要求1所述的半导体堆叠封装方法,其特征在于,
所述第二芯片的功能区为所述第二芯片的凸点;
将第二芯片的功能区连接至所述金属柱凸点包括:以倒装的方式将所述第二芯片的凸点与所述金属柱凸点对应连接。
9.根据权利要求1-8任一所述的半导体堆叠封装方法,其特征在于,
在基板上表面形成金属柱凸点之后,还在所述金属柱凸点的上表面镀锡保护剂;
将第二芯片的功能区连接至所述金属柱凸点之前,去除所述金属柱凸点上表面的所述锡保护剂。
10.根据权利要求9所述的半导体堆叠封装方法,其特征在于,所述锡保护剂为有机或无机保焊膜。
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107123602A (zh) * | 2017-06-12 | 2017-09-01 | 江阴长电先进封装有限公司 | 一种指纹识别芯片的封装结构及其制造方法 |
CN109119346A (zh) * | 2018-08-16 | 2019-01-01 | 嘉盛半导体(苏州)有限公司 | 晶圆级芯片的封装方法及结构 |
CN111584478A (zh) * | 2020-05-22 | 2020-08-25 | 甬矽电子(宁波)股份有限公司 | 一种叠层芯片封装结构和叠层芯片封装方法 |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101924087A (zh) * | 2009-06-09 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | 一种倒装芯片凸块结构及其制作工艺 |
CN103325751A (zh) * | 2013-06-09 | 2013-09-25 | 华进半导体封装先导技术研发中心有限公司 | 台阶型微凸点结构及其制备方法 |
CN103489842A (zh) * | 2013-09-29 | 2014-01-01 | 南通富士通微电子股份有限公司 | 半导体封装结构 |
CN103762185A (zh) * | 2013-12-20 | 2014-04-30 | 南通富士通微电子股份有限公司 | 半导体叠层封装方法 |
CN104051443A (zh) * | 2014-06-30 | 2014-09-17 | 江苏长电科技股份有限公司 | 新型高密度可堆叠封装结构及制作方法 |
CN104659004A (zh) * | 2014-12-30 | 2015-05-27 | 华天科技(西安)有限公司 | 一种PoP封装结构及其制造方法 |
CN104867908A (zh) * | 2014-02-21 | 2015-08-26 | 南茂科技股份有限公司 | 倒装芯片堆叠封装 |
CN104952828A (zh) * | 2014-03-25 | 2015-09-30 | 恒劲科技股份有限公司 | 覆晶堆叠封装结构及其制作方法 |
-
2015
- 2015-12-16 CN CN201510947251.5A patent/CN105428251A/zh active Pending
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101924087A (zh) * | 2009-06-09 | 2010-12-22 | 中芯国际集成电路制造(上海)有限公司 | 一种倒装芯片凸块结构及其制作工艺 |
CN103325751A (zh) * | 2013-06-09 | 2013-09-25 | 华进半导体封装先导技术研发中心有限公司 | 台阶型微凸点结构及其制备方法 |
CN103489842A (zh) * | 2013-09-29 | 2014-01-01 | 南通富士通微电子股份有限公司 | 半导体封装结构 |
CN103762185A (zh) * | 2013-12-20 | 2014-04-30 | 南通富士通微电子股份有限公司 | 半导体叠层封装方法 |
CN104867908A (zh) * | 2014-02-21 | 2015-08-26 | 南茂科技股份有限公司 | 倒装芯片堆叠封装 |
CN104952828A (zh) * | 2014-03-25 | 2015-09-30 | 恒劲科技股份有限公司 | 覆晶堆叠封装结构及其制作方法 |
CN104051443A (zh) * | 2014-06-30 | 2014-09-17 | 江苏长电科技股份有限公司 | 新型高密度可堆叠封装结构及制作方法 |
CN104659004A (zh) * | 2014-12-30 | 2015-05-27 | 华天科技(西安)有限公司 | 一种PoP封装结构及其制造方法 |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107123602A (zh) * | 2017-06-12 | 2017-09-01 | 江阴长电先进封装有限公司 | 一种指纹识别芯片的封装结构及其制造方法 |
CN107123602B (zh) * | 2017-06-12 | 2019-06-21 | 江阴长电先进封装有限公司 | 一种指纹识别芯片的封装结构及其制造方法 |
CN109119346A (zh) * | 2018-08-16 | 2019-01-01 | 嘉盛半导体(苏州)有限公司 | 晶圆级芯片的封装方法及结构 |
CN109119346B (zh) * | 2018-08-16 | 2021-07-23 | 嘉盛半导体(苏州)有限公司 | 晶圆级芯片的封装方法及结构 |
CN111584478A (zh) * | 2020-05-22 | 2020-08-25 | 甬矽电子(宁波)股份有限公司 | 一种叠层芯片封装结构和叠层芯片封装方法 |
CN111584478B (zh) * | 2020-05-22 | 2022-02-18 | 甬矽电子(宁波)股份有限公司 | 一种叠层芯片封装结构和叠层芯片封装方法 |
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