CN105161465A - 晶圆级芯片封装方法 - Google Patents

晶圆级芯片封装方法 Download PDF

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Publication number
CN105161465A
CN105161465A CN201510486611.6A CN201510486611A CN105161465A CN 105161465 A CN105161465 A CN 105161465A CN 201510486611 A CN201510486611 A CN 201510486611A CN 105161465 A CN105161465 A CN 105161465A
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China
Prior art keywords
dielectric layer
semiconductor chip
layer
wafer stage
encapsulation method
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CN201510486611.6A
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English (en)
Inventor
林正忠
仇月东
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SJ Semiconductor Jiangyin Corp
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SJ Semiconductor Jiangyin Corp
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Publication date
Application filed by SJ Semiconductor Jiangyin Corp filed Critical SJ Semiconductor Jiangyin Corp
Priority to CN201510486611.6A priority Critical patent/CN105161465A/zh
Publication of CN105161465A publication Critical patent/CN105161465A/zh
Priority to PCT/CN2016/082846 priority patent/WO2017024846A1/zh
Priority to US15/752,180 priority patent/US10290515B2/en
Pending legal-status Critical Current

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Abstract

本发明提供一种晶圆级芯片封装方法，包括：1）提供一载体，于所述载体的表面形成粘合层；2）于所述粘合层表面形成介质层；3）将半导体芯片正面朝下地附着于所述介质层表面；4）采用注塑工艺对各半导体芯片进行封装；5）分离所述粘合层及介质层，以去除所述载体及粘合层；6）基于所述介质层对所述半导体芯片形成重新布线层；7）于所述重新布线层上进行植球回流工艺，形成微凸点。本发明通过在粘合层与半导体芯片之间制作介质层，避免了粘合层与半导体芯片直接粘合而造成半导体芯片被污染的问题。通过本发明的封装方法，可以将封装过程中半导体芯片被污染的情况得到极大的控制，从而提高半导体芯片的成品率及电性能。

Description

晶圆级芯片封装方法
技术领域
本发明属于半导体制造领域，特别是涉及一种晶圆级芯片封装方法。
背景技术
随着集成电路制造业的快速发展，人们对集成电路的封装技术的要求也不断提高，现有的封装技术包括球栅阵列封装(BGA)、芯片尺寸封装(CSP)、圆片级封装(WLP)、三维封装(3D)和***封装(SiP)等。其中，圆片级封装(WLP)由于其出色的优点逐渐被大部分的半导体制造者所采用，它的全部或大部分工艺步骤是在已完成前工序的硅圆片上完成的，最后将圆片直接切割成分离的独立器件。圆片级封装(WLP)具有其独特的优点：①封装加工效率高，可以多个圆片同时加工；②具有倒装芯片封装的优点，即轻、薄、短、小；③与前工序相比，只是增加了引脚重新布线(RDL)和凸点制作两个工序，其余全部是传统工艺；④减少了传统封装中的多次测试。因此世界上各大型IC封装公司纷纷投入这类WLP的研究、开发和生产。WLP的不足是目前引脚数较低，还没有标准化和成本较高。WLP所涉及的关键技术除了前工序所必须的金属淀积技术、光刻技术、蚀刻技术等以外，还包括重新布线(RDL)技术和凸点制作技术。通常芯片上的引出端焊盘是排到在管芯周边的方形铝层，为了使WLP适应了SMT二级封装较宽的焊盘节距，需将这些焊盘重新分布，使这些焊盘由芯片周边排列改为芯片有源面上阵列排布，这就需要重新布线(RDL)技术。
重新布线层(RDL)是倒装芯片组件中芯片与封装之间的接口界面。重新布线层是一个额外的金属层，由核心金属顶部走线组成，用于将裸片的I/O焊盘向外绑定到诸如凸点焊盘等其它位置。凸点通常以栅格图案布置，每个凸点都浇铸有两个焊盘(一个在顶部，一个在底部)，它们分别连接重新布线层和封装基板。
现有的扇出型芯片封装技术，通常是将半导体芯片直接粘贴于贴膜上，然后将半导体芯片转移至支撑衬底或支架上。半导体芯片转移后，需要将所述贴膜进行移除，然而，在贴膜移除的同时，贴膜上的粘合胶容易残留在半导体芯片表面，对半导体芯片造成污染，从而影响。
为了克服上述缺陷，现有的一种解决方案是，先直接于硅支撑衬底表面制作重新布线层，然后在半导体芯片表面制作焊接凸点，对准后将半导体芯片封装于所述硅支撑衬底表面，最后减薄所述硅支撑衬底。这种工艺的优点是可以避免贴膜的粘合胶对半导体芯片的污染。但是，由于重新布线层制作于硅支撑衬底上，半导体芯片的封装需要非常高的对准精度，以保证电性能，因而这种工艺的实现难度较高，容易造成成品率的下降。
鉴于以上原因，提供一种能有效避免半导体芯片污染的晶圆级芯片封装方法实属必要。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种晶圆级芯片封装方法，用于解决现有技术中半导体芯片封装过程中容易被污染的问题。
为实现上述目的及其他相关目的，本发明提供一种晶圆级芯片封装方法，所述晶圆级芯片封装方法包括步骤：1)提供一载体，于所述载体的表面形成粘合层；2)于所述粘合层表面形成介质层；3)将半导体芯片正面朝下地附着于所述介质层表面；4)采用注塑工艺对各半导体芯片进行封装；5)分离所述粘合层及介质层，以去除所述载体及粘合层；6)基于所述介质层对所述半导体芯片形成重新布线层；7)于所述重新布线层上进行植球回流工艺，形成微凸点。
作为本发明的晶圆级芯片封装方法的一种优选方案，所述半导体芯片为扇出型半导体芯片。
作为本发明的晶圆级芯片封装方法的一种优选方案，所述载体包括玻璃、半导体、金属及刚性的聚合物中的一种。
作为本发明的晶圆级芯片封装方法的一种优选方案，所述粘合层与介质层所采用的材料不同，并且所述粘合层与介质层能实现完全分离。
作为本发明的晶圆级芯片封装方法的一种优选方案，所述介质层与半导体芯片之间具有足够的附着力以将各半导体芯片固定于所述介质层表面。
作为本发明的晶圆级芯片封装方法的一种优选方案，所述粘合层包括胶带、通过旋涂工艺制作的粘合胶或环氧树脂中的一种，所述介质层包括二氧化硅及氮化硅中的一种。
作为本发明的晶圆级芯片封装方法的一种优选方案，步骤4)的注塑工艺采用的封装材料包括硅胶以及环氧树脂中的一种。
作为本发明的晶圆级芯片封装方法的一种优选方案，步骤6)包括以下步骤：6-1)采用光刻工艺及刻蚀工艺于所述介质层中形成与半导体芯片电性引出所对应的通孔；6-2)于各通孔中填充金属导体，形成连接通孔；6-3)于所述介质层表面形成于所述连接通孔对应连接的重新布线层。
进一步地，步骤6-3)包括以下步骤：6-3a)于所述介质层表面制作光刻胶图形；6-3b)基于所述光刻胶图形于所述介质层表面沉积或溅射种子层；6-3c)基于所述种子层电镀金属导体形成金属连线；6-3d)去除所述光刻胶图形，以形成重新布线层。
如上所述，本发明的晶圆级芯片封装方法，具有以下有益效果：本发明通过在粘合层与半导体芯片之间制作介质层，避免了粘合层与半导体芯片直接粘合而造成半导体芯片被污染的问题。通过本发明的封装方法，可以将封装过程中半导体芯片被污染的情况得到极大的控制，从而提高半导体芯片的成品率及电性能。本发明步骤简单，可以有效提高产品的良率及性能，在半导体制造领域具有广泛的应用前景。
附图说明
图1显示为本发明的晶圆级芯片封装方法的步骤流程示意图。
图2～图8显示为本发明的晶圆级芯片封装方法各步骤所呈现的结构示意图。
元件标号说明
11载体
12粘合层
13介质层
14半导体芯片
15封装材料
16重新布线层
17微凸点
S11～S17步骤1)～步骤7)
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
请参阅图1～图8。需要说明的是，本实施例中所提供的图示仅以示意方式说明本发明的基本构想，遂图示中仅显示与本发明中有关的组件而非按照实际实施时的组件数目、形状及尺寸绘制，其实际实施时各组件的型态、数量及比例可为一种随意的改变，且其组件布局型态也可能更为复杂。
如图1～图8所示，本实施例提供一种晶圆级芯片封装方法，所述晶圆级芯片封装方法包括步骤：
如图1及图2所示，首先进行步骤1)S11，提供一载体11，于所述载体11的表面形成粘合层12；
所述载体11可以为后续制作粘合层12以及介质层13提供刚性的结构或基体，例如，所述载体11可以选用为具有适当形状的玻璃、半导体、金属及刚性的聚合物中的一种。在本实施例中，所述载体11选用为玻璃。
所述粘合层12最好选用具有光洁表面的粘合材料制成，并且能够在其表面制作介质层13，其必须与介质层13具有一定的结合力，以保证介质层13在后续工艺中不会产生自动脱落等情况，另外，其与载体11可以具有较强的结合力，一般来说，其与载体11的结合力需要大于与介质层13的结合力，所述粘合层12在后续的工艺中用于介质层13与载体11之间的分离层。作为示例，所述粘合层12可以选用为胶带、通过旋涂工艺制作的粘合胶或环氧树脂中的一种。在本实施例中，所述粘合层12选用为胶带。
如图1及图3所示，然后进行步骤2)S12，于所述粘合层12表面形成介质层13。
作为示例，所述粘合层12与介质层13所采用的材料不同，并且所述粘合层12与介质层13能实现完全分离，另外，所述介质层13与半导体芯片14之间必须具有足够的附着力以将各半导体芯片14固定于所述介质层13表面。
作为示例，所述介质层13包括二氧化硅及氮化硅中的一种。在本实施例中，所述介质层13为二氧化硅，其可以通过如气相沉积等方法制作于所述粘合层12上。当然，其他的介质层13也同样适用，并不限于此处所列举的示例。
如图1及图4所示，接着进行步骤3)S13，将半导体芯片14正面朝下地附着于所述介质层13表面。
在本实施例中，所述半导体芯片14为扇出型半导体芯片14。当然，在其它的实施例中，本发明的封装方法也可以用于安装如存储器件、显示器件、输入组件、分立元件、电源、稳压器等器件，且并不限定于此处所列举的几种示例。
作为示例，所述半导体芯片14的数量可以为1个至1个晶圆所能承载的半导体芯片14数量，在本实施例中，所述半导体芯片14的数量为1个晶圆所能承载的半导体芯片14数量。
如图1及图5所示，然后进行步骤4)S14，采用注塑工艺对各半导体芯片14进行封装。
作为示例，所述注塑工艺采用的封装材料15包括硅胶以及环氧树脂中的一种。在本实施例中，所述封装材料15为硅胶。通过注塑工艺后的半导体芯片14可以被进一步地固定在硅胶以及介质层13之间，大大增强其稳定性。
如图1及图6所示，然后进行步骤5)S15，分离所述粘合层12及介质层13，以去除所述载体11及粘合层12。
在本实施例中，可以采用撕裂的方式将所述粘合层12及介质层13进行分离，以去除所述载体11及粘合层12。相比于传统的减薄工艺，如研磨、腐蚀等来说，本发明的分离方法非常简单，易于操作，可以大大降低工艺成本。
如图1及图7所示，接着进行步骤6)S16，基于所述介质层13对所述半导体芯片14形成重新布线层16。
作为示例，具体包括以下步骤：
步骤6-1)，采用光刻工艺及刻蚀工艺于所述介质层13中形成与半导体芯片14电性引出所对应的通孔。
步骤6-2)，于各通孔中填充金属导体，形成连接通孔。
作为示例，所述金属导体包括Cu、Al等金属材料，可以通过如沉积、电镀等工艺填充于所述通孔中，形成连接通孔。在本实施例中，所述金属导体为Cu。
步骤6-3)，于所述介质层13表面形成于所述连接通孔对应连接的重新布线层16。
在本实施例中，步骤6-3)具体包括以下步骤：
步骤6-3a)，于所述介质层13表面制作光刻胶图形。
步骤6-3b)，基于所述光刻胶图形于所述介质层13表面沉积或溅射种子层。在本实施例中，所述种子层为Ti/Cu层。
步骤6-3c)，基于所述种子层电镀金属导体形成金属连线。
步骤6-3d)，去除所述光刻胶图形，以形成重新布线层16。
如图1及图8所示，最后进行步骤7)S17，于所述重新布线层16上进行植球回流工艺，形成微凸点17。
具体地，在对应于每个连接通孔的位置形成如金锡合金等导体材料，然后通过植球回流工艺，形成微凸点17，用于与后续的支撑结构实现电连接及引出。
如上所述，本发明提供一种晶圆级芯片封装方法，所述晶圆级芯片封装方法包括步骤：1)提供一载体11，于所述载体11的表面形成粘合层12；2)于所述粘合层12表面形成介质层13；3)将半导体芯片14正面朝下地附着于所述介质层13表面；4)采用注塑工艺对各半导体芯片14进行封装；5)分离所述粘合层12及介质层13，以去除所述载体11及粘合层12；6)基于所述介质层13对所述半导体芯片14形成重新布线层16。本发明通过在粘合层12与半导体芯片14之间制作介质层13，避免了粘合层12与半导体芯片14直接粘合而造成半导体芯片14被污染的问题。通过本发明的封装方法，可以将封装过程中半导体芯片14被污染的情况得到极大的控制，从而提高半导体芯片14的成品率及电性能。本发明步骤简单，可以有效提高产品的良率及性能，在半导体制造领域具有广泛的应用前景。本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (10)

1.一种晶圆级芯片封装方法，其特征在于，所述晶圆级芯片封装方法包括步骤：
1)提供一载体，于所述载体的表面形成粘合层；
2)于所述粘合层表面形成介质层；
3)将半导体芯片正面朝下地附着于所述介质层表面；
4)采用注塑工艺对各半导体芯片进行封装；
5)分离所述粘合层及介质层，以去除所述载体及粘合层；
6)基于所述介质层对所述半导体芯片形成重新布线层。
2.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：还包括步骤7)，于所述重新布线层上进行植球回流工艺，形成微凸点。
3.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：所述半导体芯片为扇出型半导体芯片。
4.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：所述载体包括玻璃、半导体、金属及刚性的聚合物中的一种。
5.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：所述粘合层与介质层所采用的材料不同，并且所述粘合层与介质层能实现完全分离。
6.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：所述介质层与半导体芯片之间具有足够的附着力以将各半导体芯片固定于所述介质层表面。
7.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：所述粘合层包括胶带、通过旋涂工艺制作的粘合胶或环氧树脂中的一种，所述介质层包括二氧化硅及氮化硅中的一种。
8.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：步骤4)的注塑工艺采用的封装材料包括硅胶以及环氧树脂中的一种。
9.根据权利要求1所述的晶圆级芯片封装方法，其特征在于：步骤6)包括以下步骤：
6-1)采用光刻工艺及刻蚀工艺于所述介质层中形成与半导体芯片电性引出所对应的通孔；
6-2)于各通孔中填充金属导体，形成连接通孔；
6-3)于所述介质层表面形成于所述连接通孔对应连接的重新布线层。
10.根据权利要求9所述的晶圆级芯片封装方法，其特征在于：步骤6-3)包括以下步骤：
6-3a)于所述介质层表面制作光刻胶图形；
6-3b)基于所述光刻胶图形于所述介质层表面沉积或溅射种子层；
6-3c)基于所述种子层电镀金属导体形成金属连线；
6-3d)去除所述光刻胶图形，以形成重新布线层。
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