CN105070746B - 用于横向双扩散金属氧化物半导体场效应晶体管的直通硅通孔处理技术 - Google Patents

用于横向双扩散金属氧化物半导体场效应晶体管的直通硅通孔处理技术 Download PDF

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CN105070746B
CN105070746B CN201510516801.8A CN201510516801A CN105070746B CN 105070746 B CN105070746 B CN 105070746B CN 201510516801 A CN201510516801 A CN 201510516801A CN 105070746 B CN105070746 B CN 105070746B
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semiconductor layer
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CN105070746A (zh
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雪克·玛力卡勒强斯瓦密
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Alpha and Omega Semiconductor Cayman Ltd
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Abstract

本发明提出了一种形成在半导体衬底上的场效应管，栅极、源极和漏极区形成在半导体衬底上，所述的栅极区具有一个横向栅极通道。多个空间分离的沟槽都带有一个导电插头，并与所述的栅极、源极和漏极区电连接，所述的沟槽从所述的半导体衬底表面开始，延伸到可控的深度。沟槽接头将源极区和本体区短接。源极接头与所述的源极区电连接，漏极接头与所述的漏极区电连接，所述的源极和漏极接头设置在所述的栅极通道对边上。

Description

用于横向双扩散金属氧化物半导体场效应晶体管的直通硅通 孔处理技术
本案是分案申请
原案发明名称：用于横向双扩散金属氧化物半导体场效应晶体管的直通硅通孔处理技术
原案申请号：201210129637.1
原案申请日：2012年4月20日。
技术领域
本发明主要涉及高压半导体器件及其制备工艺，尤其是横向双扩散金属氧化物半导体（LDMOS）晶体管，更确切地说是源极在器件背面的垂直分立LDMOS。之所以将该器件称为“垂直”，是由于其源极在底部，漏极在顶部（或反之亦然）。“横向”是指器件的平面栅极。
背景技术
由于横向双扩散金属氧化物半导体（LDMOS）晶体管具有高击穿电压以及可以与低压器件的补充金属-氧化物-半导体（CMOS）技术兼容的特点，因此常用于高压器件（例如20至500伏，甚至更高）。一般来说，LDMOS晶体管包括一个平面多晶硅栅极、一个形成在P-型本体区中的N+源极区以及一个N+漏极区。通道由N漏极漂流区形成在多晶硅栅极下方的本体区中，N+漏极区与该通道分离。众所周知，通过增大N漂流区的长度，可以相应地提高LDMOS晶体管的击穿电压。
典型的LDMOS晶体管用于高频器件，例如无线电射频和/或微波功率放大器。它们通常用在功率放大器中，用于需要高输出功率的基站，相应的漏源击穿电压通常在60伏以上。因此，需要使LDMOS晶体管能够在高频下工作，同时保持相同的高压作业。
在有些情况下，需要将LDMOS晶体管制成垂直器件。使源极路由到晶片底部，用于更好的封装可选件非常有利，例如降低源极上的电感。但是，将LDMOS晶体管的源极路由到衬底，并且不使电阻增大很多，是很困难的。
因此，有必要提出改良型的LDMOS晶体管。
发明内容
本发明提出了一种形成在半导体衬底上的场效应晶体管，半导体衬底上具有栅极、源极和漏极区，栅极区具有一个横向栅极通道。配置多个空间分离的沟槽或直通半导体通孔（TSV），以降低底部源极的电阻，它们都具有一个导电插头，导电插头与栅极、源极和漏极区电连接。在源极区附近形成一个接触沟槽，接触沟槽短接源极区和本体区。源极接头与源极区电连接；漏极接头与漏极区电连接，源极和漏极接头设置在横向栅极通道的对立边上。
一种场效应晶体管，该场效应晶体管包括：
一个半导体衬底，在该衬底上形成带有栅极、源极和漏极区，所述的栅极区具有一个横向栅极通道；
一个或多个带有导电插头的沟槽，导电插头与所述的栅极、源极和漏极区电连接，其中所述的一个或多个沟槽从所述的衬底背面延伸到可控的深度；
一个与所述的源极区电连接的源极接头；
一个与所述的漏极区电连接的漏极接头，所述的源极和漏极接头设置在所述的栅极通道的对边上；以及
一个栅极接头。
其中一个或多个沟槽含有一个接触沟槽，将所述的源极区短接至所述的源极接头。
其中一个或多个沟槽含有多个空间分离的沟槽。
其中所述的沟槽接头设置在所述的源极和漏极接头之间。
其中所述的半导体衬底具有第一和第二对边，所述的栅极、源极和漏极区形成在所述的第一对边上，所述的一个或多个沟槽从所述的横向栅极通道开始延伸，穿过所述的衬底，在形成在所述的第二对边上的一个或多个开口中截止。
其中所述的栅极、源极和漏极区还包括一个形成在所述的衬底上的层，该层的第一部分具有第一导电类型，第二部分具有与所述的第一导电类型相反的第二导电类型，所述的栅极通道包括所述的层。
其中所述的栅极、源极和漏极区还包括第一半导体层，形成在所述的衬底上，设置在所述的第一半导体层第二半导体层上方，所述的第一半导体层、第二半导体层以及所述的衬底具有第一导电类型，其中所述的第一半导体层的掺杂浓度高于所述的第二半导体层的掺杂类型。
其中所述的多个空间分离的沟槽从所述的衬底的所述的底面开始延伸，在所述的第一半导体层中截止。
其中所述的第二半导体层含有第一导电类型的第一部分，以及与第一导电类型相反的第二导电类型的第二部分，其中所述的源极区形成在所述的第一部分顶部，所述的漏极区形成在所述的第二部分顶部。
其中所述的沟槽接头将所述的源极区短接至所述的第一部分。
其中所述的一个或多个沟槽从所述的衬底所述的表面开始，延伸到所述的源极区。
其中所述的第一半导体层含有高掺杂浓度的第一部分以及低掺杂浓度的第二部分，其中肖特基接头形成在所述的第二区域和所述的导电插头的交叉处。
其中所述的栅极、源极和漏极区还包括一个形成在所述的衬底上的第一半导体层，所述的第一半导体层和所述的衬底具有第一导电类型，设置在所述的第一半导体层第二半导体层上方，所述的第二半导体层具有多个不同导电类型的区域，限定超级结结构与所述的栅极、源极和漏极区电连接。
其中所述的栅极、源极和漏极区还包括一个形成在所述的衬底上的第一半导体层，所述的第一半导体层和所述的衬底具有第一导电类型，设置在所述的第一半导体层第二半导体层上方，所述的第二半导体层具有多个不同导电类型的区域，所述的多个区域中的第一区设置在第二和第三区之间，其导电类型与所述的第一半导体层相同，与所述的第二和第三区相反。
其中所述的栅极、源极和漏极区还包括一个形成在所述的衬底上的第一半导体层，所述的半导体层和所述的衬底具有第一导电类型，设置在所述的第一半导体层第二半导体层上方，所述的第二半导体层具有多个不同导电类型的区域，所述的多个区域中的第一区设置在第二和第三区之间，其导电类型与所述的第一半导体层相同，与所述的第二和第三区相反，所述的第二区设置在所述的第一区和所述的第一半导体层之间。
其中所述的栅极、源极和漏极区还包括一个形成在所述的衬底上的第一半导体层，所述的第一半导体层和所述的衬底具有第一导电类型，设置在所述的第一半导体层第二半导体层上方，所述的第二半导体层具有多个不同导电类型的区域，限定超级结结构与所述的栅极、源极和漏极区电连接，每个所述的区域都从所述的第一半导体层开始，朝着所述的源极接头延伸。
一种场效应晶体管，该场效应晶体管包括：
一个半导体衬底，具有第一和第二对边，并且栅极、源极和漏极区形成在所述的第一对边上，所述的栅极区具有一个横向栅极通道；
一个或多个沟槽，从所述的横向栅极通道开始延伸，穿过所述的衬底，在形成在所述的第二对边上的一个或多个开口中截止；
设置在所述的一个或多个沟槽中的导电材料，覆盖着所述的第二对边，限定第一接头，与所述的漏极和源极区的其中之一电连接；
一个额外的接头，与所述的漏极和源极区的其中之一电连接；以及
一个栅极接头。
其中一个或多个沟槽含有一个接触沟槽，将所述的源极区短接至所述的衬底。
一种制备场效应晶体管的方法，所述的方法包括：
在半导体衬底的第一边上，制备多个限定栅极、源极和漏极区的材料层，所述的栅极区具有一个横向栅极通道；
由所述的半导体衬底所述的第一边对面的第二边，制备一个或多个沟槽，从一个或多个孔开始，朝着所述的半导体衬底的所述的第一边，延伸到可控的深度；并且
用导电材料填充所述的一个或多个沟槽中的多个沟槽，形成一个与所述的源极区和所述的漏极区的其中之一电连接的第一接头。
其中制备一个或多个沟槽包括制备一个接触沟槽，从所述的半导体衬底的第二边，延伸到所述的源极区。
该方法还包括制备第一导电类型的衬底，制备还包括在所述的半导体衬底上，制备一层半导体材料层，该层的第一部分具有第一导电类型，第二部分具有与第一导电类型相反的第二导电类型，所述的栅极通道包括所述的层。
该方法还包括制备第一导电类型的衬底，制备还包括在所述的半导体衬底上，制备一层具有第一导电类型的半导体材料，在所述的第一半导体层上方，制备第二半导体层，所述的第二半导体层具有多个不同导电类型的区域，限定的超级结结构与所述的栅极、源极和漏极区电连接。
该方法还包括制备第一导电类型的衬底，制备还包括在所述的半导体衬底上，制备一层具有第一导电类型的半导体材料，在所述的第一半导体层上方，制备第二半导体层，所述的第二半导体层具有多个不同导电类型的区域，所述的多个区域中的第一区设置在第二和第三区之间，其导电类型与所述的第一半导体层相同，与所述的第二和第三区相反。
附图说明
图1表示依据本发明的一个实施例，一种晶体管的剖面图；
图2表示图1所示的晶体管的制备方法的流程图；
图3表示依据本发明的第二实施例，一种晶体管的剖面图；
图4表示图3所示的晶体管的制备方法的流程图；
图5表示依据第三实施例，一种晶体管的剖面图；
图5A-5C表示依据本发明的第三实施例，一种可选晶体管的剖面图；
图6表示依据本发明的第四实施例，一种晶体管的剖面图；
图7表示依据本发明的第五实施例，一种晶体管的剖面图；
图8表示依据本发明的第六实施例，一种晶体管的剖面图；
图9表示使用本发明带有底部源极的LDMOS的单晶片和双晶片衬垫转换器的俯视图；
图10表示使用本发明带有底部源极的LDMOS的可选单晶片衬垫和双晶片衬垫转换器的俯视图；
图11A表示使用本发明带有底部源极的LDMOS的第二可选单晶片衬垫转换器的俯视图；以及
图11B表示图11A所示的单晶片衬垫转换器的侧视图。
具体实施方式
参见图1和图2，LDMOS 10形成在P-型衬底12上，外延层16形成在它上面。如同步骤151所述，P-型掩埋层（PBL）14形成在P-型衬底12和外延层16的交界处。如同步骤153所述，外延层16生长在PBL层上方。外延层可以为N-型或P-型。晶体管10的有源区形成在外延层16中。PBL 14的制备可以通过标准的掩埋层植入工艺，或还可选择利用步阶外延工艺。也就是说，重掺杂的P-型外延层可以生长在衬底12上方，作为PBL 14.还可选择，通过深植入制备PBL 14。当外延层16的厚度在几微米至10微米的范围内时，PBL 层14的厚度约为几微米。尤其是对于漏极击穿电压BV dss约为20V至60V的LDMOS来说，外延层16的范围为几微米至5微米。
如同步骤155所述，栅极氧化层18形成在外延层16上方，如同步骤156所述，利用标准的设置和仿制技术，平面栅极20形成在栅极氧化层上方。通常，栅极氧化层由二氧化硅制成，栅极20由多晶硅制成。但是，除了多晶硅之外，栅极20还可以由导电材料制成。P-型本体区22利用标准工艺，形成在外延层16中，以便从PBL 14延伸到栅极氧化物18，构成一个弓形区，临近N-漂流区24，并与其空间分离，如同步骤157所述，在下文中还将详细介绍。在现有的实施例中，制备的P-型本体区22可以穿过P –型植入物，自对准到多晶硅栅极20的边缘，然后热退火。如同步骤159所述，随着P-型本体区22的形成，漏极漂流区24利用标准工艺，形成在外延层16中。通过植入适合的掺杂物（在本例中为N-型掺杂物），然后热退火。制备漏极漂流区24，还可选择，在形成栅极氧化层18和/或多晶硅栅极20之前，制备P-型本体区22和漏极漂流区24。因此，外延层16的区域23依然没有植入掺杂物。
利用标准工艺制备源极和漏极区26和28，例如通过植入合适的掺杂物，然后热驱动，如同步骤161所述，使源极区26和漏极区28具有所需的导电性。多晶硅栅极20用于源极26进行自对齐的植入工艺。
利用标准的刻蚀工艺制备沟槽32，并用金属等导电材料填充，以形成沟槽接头32。确切地说，Ti-TiN的薄势垒金属层首先形成在沟槽32的底部和侧壁，这可以通过溅镀，随后进行钨（W）的化学气相设置（CVD），以及Ti-Ti-AlCu的溅镀来完成。沟槽接头32将源极区26和本体区22短接在一起，并短接至PBL 14。晶体管中可以含有P+本体接触区30，以便为P本体区22和PBL 14提供良好的欧姆接触。为此，可以在填充沟槽32之前，热退火之后，进行P-型掺杂物带角度的离子植入，如同步骤163和165所述，为P+区30提供合适的掺杂浓度。N+源极区26的重掺杂浓度很大，使P+植入本体接头不会明显地补偿掺杂源极区。
制备电介质层34，以覆盖多晶硅栅极20、栅极氧化层18以及沟槽接头32，如同步骤167所述。电介质层34包括含有硼酸的硅玻璃（BPSG）、掺杂的氧化物或化学气相设置形成的氧化物，其厚度约为1微米。接触开口36形成在电介质层34中，通过刻蚀电介质层34，使漏极区28裸露出来。用钨、铜之类的导电材料填充接触开口36，以形成导电插头38。与沟槽32类似，Ti-TiN的薄势垒金属层首先形成在接触开口36的底部和侧壁，这可以通过溅镀，随后进行钨（W）的化学气相设置（CVD），以及Ti-Ti-AlCu的溅镀来完成。如同步骤169所述，形成插头38设置金属等导电材料之后，继续制备漏极接头40。
如同步骤171所述，多个深沟槽或TSV 42、43和44形成于衬底12的背面46，衬底12设置在漏极接头40对面。利用标准的刻蚀工艺，通过从衬底12的边缘46开始刻蚀，制备沟槽42、43和44，使沟槽43和44分别从孔48和49开始延伸，它们位于边缘46中，并在PBL层14中截止；沟槽42从孔50开始延伸，在P+接头30或PBL 14中截止，或直接延伸到沟槽接头32。还可选择，通过TSV激光从背面46钻孔，形成沟槽42、43和44，然后清洗沟槽或各向同性的干刻蚀。用钨、铜以及类似的导电材料或TSV金属，填充沟槽42、43和44，形成插头51、52和53，连接到覆盖着背面46的导电材料，构成源极接头54，如同步骤173所述。作为示例，沟槽42、43和44及其导电填充物，可以作为部分直通硅通孔（TSV）（或更普遍地称为直通半导体通孔），穿过衬底12刻蚀。
凭借这种结构，晶体管10形成一个具有平面栅极的栅极区。栅极20在外延层16的表面附近的P-本体区22中，限定了一个横向通道。来自N+源极区26的电子流在水平方向上穿过P-本体区22中的横向通道，流入漏极漂流区24中。沟槽接头32将N+源极区26短接至P-本体区22以及PBL 14上。通过从N+源极区26，在垂直方向上穿过沟槽接头32，延伸到PBL 14中的通路，电子连接在源极区26和源极接头54之间，然后横向穿过PBL 14，向下穿过导电插头51、52、53，一直到源极接头54。尤其是插头51、52和53降低了源极电阻，提高了晶体管效率。必须使临近插头51、52和53之间的间距最小，同时不会破坏晶体管10的结构完整性。因此，临近插头51、52和53之间的间距取决于多种因素，包括制备晶体管10的材料以及尺寸等。此外，PBL 14可以与漏极漂流区24一起提供减小的表面场（RESURF）效应，提高了晶体管10的击穿电压。
参见图1和图3，所示的晶体管110具有与晶体管10相似的特性，同时省去了沟槽43和44以及插头52和53。因此，可选件114, 116, 118, 120, 122, 126, 128, 130, 134,136, 138 和140与可选件14, 16, 18, 20, 22, 26, 28, 30, 34, 36, 38 和40相同，并且制备方法也相同。
参见图1、3和4，所述的制备晶体管110的步骤251-263、267和269与步骤151-163、167和169相同。但是，如同步骤262所述，从外延层的顶面下，晶体管110的沟槽接头132形成得较深，至少部分填充到衬底112中。此外，如同步骤271所述，用背部研磨工艺处理衬底112，从其背面除去坚固的部分，使沟槽接头142的底部裸露出来。步骤271之后，衬底112的厚度小于50微米。还可选择，在背部研磨工艺之后，从背面形成沟槽142，完全穿过衬底112，并在钝化层134中截止——但是，从背面很难完全对准。用钨、铜等类似材料，填充沟槽142，形成沟槽接头132。如同步骤273所述，沟槽接头132连接到源极接头154，源极接头154覆盖半导体衬底112的背面。
参见图1和5，用晶体管210表示晶体管10的另一个实施例。除了晶体管10的PBL层14用形成在衬底212上的层214代替之外，晶体管210的其他部分都与晶体管10相同，层214分成两个不同的区域215和217，每个区域都有导电类型不同的掺杂物。区域215的掺杂物浓度和导电类型与晶体管10的PBL层14相同。但是，区域217为N-型掺杂物的轻掺杂，或者是N-型外延层216本身。区域217的掺杂浓度是为了在轻掺杂的N-型区域217接触金属插头252和253的地方，形成肖特基接头219。与晶体管10中普通的P-N结体二极管相比，这种结构增强了晶体管210的反向传导二极管的反向恢复。
参见图3、5和5A，用晶体管211表示晶体管110的一个可选实施例，晶体管211含有与图5类似的集成肖特基接头219。除了用分成两个不同区域215和217的层代替晶体管110的PBL层114，每个区域都具有导电类型不同的掺杂物之外，晶体管211的其他部分都与晶体管110相同。区域215的掺杂物浓度和导电类型与晶体管110的PBL层114相同。但是，区域217为N-型掺杂物的轻掺杂，或者是N-型外延层116本身。区域217的掺杂浓度是为了在轻掺杂的N-型区域217接触金属插头252和253的地方，形成肖特基接头219。
参见图3、5A和5B，用晶体管213表示晶体管210的一种可选结构，晶体管213为集成与图5类似的肖特基接头219的CMOS。除了晶体管213为N+漏极NMOS之外，其他都与晶体管211类似。如图5B所示，晶体管213包括一个N+源极126、一个N+漏极128，形成在P井116中，平面栅极121形成在P井116上方，并与栅极氧化物119绝缘。
参见图3、5A和5C，用晶体管215表示晶体管210的一种可选结构，晶体管215为集成与图5类型的肖特基接头219的LDD NMOS。除了晶体管213为轻掺杂的漏极（LDD）NMOS之外，其他都与晶体管211类似。如图5B所示，晶体管213包括一个N+源极126、一个N+漏极128以及一个轻掺杂的N漂流漏极129，形成在P阱116中，平面栅极121形成在P井116上方，并于栅极氧化物119绝缘。
参见图1和6，晶体管310表示晶体管10的另一个实施例。因此，可选件336和340与可选件36和40基本相同，并且可以用相同的方法制备。晶体管310中除了晶体管10中的外延层16的漂流区24带有超级结结构之外，其他都与晶体管10基本相同。为此，晶体管310的外延层316含有多个交替的N-型和P-型掺杂区360、361和362。区域360和362带有相同的导电类型，区域361带有相反的导电类型。在一个实施例中，区域360和362带有N-型导电类型，并且连接到漏极电压，区域361带有P-型导电类型，并且经由P-本体区322连接到源极电压。但是，应明确的是，区域360和362可能带有P-型导电类型，区域361可能带有N-型导电类型。利用人们熟知的技术，通过适当掺杂物的多能量植入，区域360-362可能带有所需的导电类型。此外，在另一个实施例中，区域360和362可以自对准到栅极320。从P-本体区322开始延伸的区域361，通过带角度的植入以及随后的热退火，可以将掺杂物驱入合适的位置。当晶体管断开时，漏极和源极处于不同的电压，从而通过超级结区域361，将超级结区域360和362反向偏置。区域360-362耗尽，会影响器件的大击穿电压。当晶体管接通时，栅极激活了将源极连接到漏极的通道，使超级结区域360-362大致处于相同的电压，并且不会耗尽。
还可选择，制备一个栅极-漏极金属屏蔽，使栅极320避开漏极电极。接触沟槽332连接到栅极-漏极屏蔽部分366，其中级间导电层368延伸在上方，并与栅极320重叠。栅极-漏极屏蔽部分366靠近漏极漂流区324，但与钝化材料分开。钝化层364将栅极-漏极金属屏蔽与栅极电极320绝缘。PBL 314为单独的RESURF效应提供漏极漂流区324，以提高晶体管310的击穿电压。
参见图1和7，依据另一个实施例，晶体管410中除了对应沟槽42的沟槽442一直从源极接头454延伸到源极区426之外，其他都与晶体管10相同。确切地说，可选件414, 416,418, 420, 422, 424, 426, 428, 434, 436, 440, 443, 444, 446, 452, 453和454与可选件14, 16, 18, 20, 22, 24, 26, 28, 34, 36, 40, 43, 44, 46, 52, 53和54相同，并且可以用相同的方法制备。因此，深沟槽以及两个深度不同的插头形成在晶体管衬底中。某些插头，例如452和453仅仅部分穿过半导体材料，也就是说从底面446到PBL 414。其他插头，例如451，可以从底面446开始，一直延伸到晶片顶部的源极426和钝化物434。
如同上述图2所示，晶体管410的制备方法与晶体管10类似。唯一的不同在于，在制备沟槽插头时，即步骤171处，沟槽442完全对准到接触源极和本体区，并且一直延伸到钝化层，而沟槽443和444仅部分穿过衬底412的半导体材料，延伸到PBL 414。
参见图1和8，在另一个实施例中，晶体管510（即带有底部漏极的LDMOS）含有多个沟槽542-544，形成在衬底512中，并用导电材料或TSV金属填充，以构成与底部漏极接头540相连接（也可选择相互集成）的插头。晶体管510含有一个N-型衬底512，其中N-型掩埋层（NBL）514形成在上面。外延层516形成在NBL514上，晶体管510的有源区就形成在NBL 514中。外延层可以为N-型或P-型。可以利用标准的掩埋层植入工艺，或者也可选择用步阶外延工艺，制备NBL 514；也就是说，可以在衬底512上方生长一个层，作为NBL 514。外延层516可以生长在NBL 514上方。
利用标准的设置和制图技术，栅极氧化层518形成在外延层516上方，多晶硅栅极520形成在栅极氧化层上方。但是，除了多晶硅之外，也可以用其他的导电材料制备栅极520。利用标准工艺，在外延层516中制备P-型本体区522。在本实施例中，所形成的P-型本体区522穿过P-型植入物，自对准到多晶硅栅极520的边缘。在其他实施例中，在制备过程中，可以利用低压P-势阱（LVPW）制备P-型本体区522。因此，P-型本体区522可以在形成栅极氧化层518和/或多晶硅栅极520之前制备。随着P-型本体区522的形成，N-型漏极漂流区524就利用标准工艺形成在外延层516中。通过适当的掺杂物（例如N-型掺杂物）植入，以及热退火，制备漏极漂流区524。
利用植入适当的掺杂物，以及热退火，制备源极和漏极区526和528，为源极区526和漏极区528提供合适的导电类型和掺杂浓度。多晶硅栅极520的存在，使源极区526的自对准植入工艺成为可能。
制备电绝缘钝化层534，以覆盖多晶硅栅极520、栅极氧化层518。在钝化层534中，形成第一和第二沟槽535和536。沟槽535使一部分P-本体522和源极区526裸露出来。沟槽536靠近漏极漂流区524，但与钝化材料分开。用钨、铜、金等类似的导电材料填充沟槽535和536，分别形成导电插头537和538，然后用源极接头539覆盖。导电插头538使栅极-漏极金属与栅极电极520隔开。还可选择，无需分离导电插头材料，源极接头539的材料也填充在沟槽535和536中。
多个深沟槽542、543和544形成在衬底512的边缘546上，边缘546设置在源极接头539对面。依照上述沟槽42、43和44的制备方法，利用标准的刻蚀工艺或激光钻孔制备沟槽。如上所述，沟槽542、543和544分别从孔547、548和550开始延伸，位于衬底512的边缘546处，并在NBL 层514中截止。用钨、铜等类似的导电材料或TVS金属，填充沟槽542、543和544，以形成插头551、552和553，用导电材料覆盖这些插头，构成漏极接头540。
超级结结构形成在外延层516中，外延层516含有多个交替的N-型和P-型掺杂区560-571。区域560-571都从NBL 514开始延伸，并在N-漂流区524和N漏极区528附近截止。当剥去N和P立柱时，交替的N-型和P-型掺杂区560-571可以是圆柱形立柱，并且在第三维度上连接到P-本体区。配置超级结，以展开来自P-型本体区的电场，或减小表面电场。
图9所示的俯视图，表示传统的双晶片衬垫转换器，以及利用本发明所述的底部源极MOSFET的单一晶片衬垫转换器。按照惯例，含有底部漏极的标准的高端（HS）和低端（LS）垂直MOSFET，位于一个封装内的两个单独的晶片衬垫上。如图9所示，控制器和集成的高端MOSFET 602电连接并且真实连接到晶片衬垫606上，底部漏极低端MOSFET 604电连接并且真实连接到晶片衬垫608上。在功率转换器封装中，高端源极和低端漏极通常相互连接，构成一个开关，低端源极接地，这可以通过另外的结合引线（图中没有表示出）来完成。另外的结合引线增加了寄生电感，双晶片衬垫606和608在转换器封装中需要更多的空间。利用本发明所述的底部源极低端MOSFET 610，集成高端MOSFET 602和底部源极低端MOSFET 610的控制器，可以安装在一个单独的晶片衬垫612中。
还可选择，图10所示的俯视图，表示利用本发明所述的底部源极MOSFET的另一个单一晶片衬垫转换器。如图10所示，底部漏极高端MOSFET 702电连接并且真实连接到晶片衬垫706上，控制器703电连接并且真实连接到晶片衬垫707上，底部漏极低端MOSFET 704电连接并且真实连接到晶片衬垫708上。利用本发明所述的底部源极低端MOSFET，控制器、低端MOSFET和高端MOSFET可以安装在单一的晶片衬垫712上。
本发明所述的底部源极MOSFET在一个转换器封装中，既可以用于高端MOSFET，也可以用于低端MOSFET。图11A-11B表示一个单独的衬垫转换器封装的俯视图和侧视图。在本结构中，底部源极高端MOSFET 802堆栈在底部源极低端MOSFET 804的顶部漏极上方，底部源极低端MOSFET 804与控制器一起，电连接并且真实连接到单独的晶片衬垫806上。
单独的晶片衬垫功率转换器可用于各种不同的使用高端和低端器件的器件，例如功率转换电路、无线电放大电路、射频（RF）放大电路以及运算放大器（op-amp）输出级。
应理解上述说明仅是本发明的示例，以及其他在本发明意图和范围内的修正，不应认为是本发明范围的局限。例如，尽管说明的是N-通道器件，但是本领域的技术人员应明确，本发明也可用于P-通道器件，例如通过转换半导体区域的导电类型。因此，本发明的范围应由所附的权利要求书及其全部等价内容限定。

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1.一种场效应晶体管，其特征在于，该场效应晶体管包括：
一个半导体衬底，具有第一和第二对边，并且栅极、源极和漏极区形成在所述的第一对边上，所述的栅极区具有一个横向栅极通道；
所述的半导体衬底包括一衬底层上的第一半导体层，设置在所述的第一半导体层上方的第二半导体层，所述的第一半导体层和第二半导体层具有第一导电类型，其中所述的第一半导体层的掺杂浓度高于所述的第二半导体层的掺杂浓度；
一个与所述的漏极区电连接的漏极接头形成在所述的第一对边上；一个与所述的源极区电连接的源极接头形成在所述的第二对边上；
一个或多个带有导电插头的沟槽，导电插头与所述的源极区电连接，其中所述的一个或多个沟槽从所述的第二对边延伸到第一半导体层的深度截止，其中所述的多个沟槽含有多个空间分离的沟槽，一个接触沟槽，将所述的源极区电连接至所述的源极接头。
2.如权利要求1所述的晶体管，其特征在于，其中所述的第二半导体层含有第一导电类型的第一部分，以及与第一导电类型相反的第二导电类型的第二部分，其中所述的源极区形成在所述的第一部分顶部，所述的漏极区形成在所述的第二部分顶部。
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Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102010020884B4 (de) * 2010-05-18 2018-03-15 Infineon Technologies Ag Halbleiterbauelement
US8399924B2 (en) 2010-06-17 2013-03-19 Texas Instruments Incorporated High voltage transistor using diluted drain
JP5917060B2 (ja) * 2011-09-21 2016-05-11 ラピスセミコンダクタ株式会社 半導体装置
US8759913B2 (en) * 2012-05-15 2014-06-24 Richtek Technology Corporation Double diffused drain metal oxide semiconductor device and manufacturing method thereof
CN103855210A (zh) * 2012-12-03 2014-06-11 上海华虹宏力半导体制造有限公司 射频横向双扩散场效应晶体管及其制造方法
US8860136B2 (en) * 2012-12-03 2014-10-14 Infineon Technologies Ag Semiconductor device and method of manufacturing a semiconductor device
US8951867B2 (en) * 2012-12-21 2015-02-10 Alpha And Omega Semiconductor Incorporated High density trench-based power MOSFETs with self-aligned active contacts and method for making such devices
CN103151368A (zh) * 2013-02-05 2013-06-12 京东方科技集团股份有限公司 一种阵列基板及oled显示装置
US10199459B2 (en) 2013-07-19 2019-02-05 Great Wall Semiconductor Corporation Superjunction with surrounding lightly doped drain region
US9299774B2 (en) * 2013-07-19 2016-03-29 Great Wall Semiconductor Corporation Device structure and methods of forming superjunction lateral power MOSFET with surrounding LDD
CN109638065A (zh) * 2013-09-27 2019-04-16 世界先进积体电路股份有限公司 横向双扩散金属氧化物半导体装置及其制造方法
US8987820B1 (en) * 2013-10-11 2015-03-24 Vanguard International Semiconductor Corporation Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same
EP2913847B1 (en) * 2014-02-28 2018-04-18 LFoundry S.r.l. Method of fabricating a semiconductor device and semiconductor product
CN103943677B (zh) * 2014-04-16 2016-08-17 中国科学院半导体研究所 一种芯片尺寸级氮化镓基晶体管及其制备方法
CN104183499B (zh) * 2014-08-13 2017-06-16 武汉新芯集成电路制造有限公司 半导体器件及其制备方法
CN104392993A (zh) * 2014-12-08 2015-03-04 江苏博普电子科技有限责任公司 一种基于高阻硅衬底的ldmos mmic芯片
CN104716187B (zh) * 2015-02-15 2018-02-06 上海华虹宏力半导体制造有限公司 射频ldmos器件及工艺方法
CN106409676A (zh) * 2015-07-29 2017-02-15 中芯国际集成电路制造(北京)有限公司 半导体结构及其制造方法
JP6550674B2 (ja) * 2015-08-13 2019-07-31 ローム株式会社 半導体装置
CN108028280B (zh) * 2015-09-25 2023-04-04 英特尔公司 制作背侧金属的接触部的卷绕源极/漏极方法
EP3151283A1 (en) * 2015-09-29 2017-04-05 Nexperia B.V. Vertical dmos bjt semiconductor device
CN105914192B (zh) * 2015-12-25 2019-02-01 苏州捷芯威半导体有限公司 基于级联电路的半导体封装结构
JP6706330B2 (ja) * 2016-01-18 2020-06-03 日本テキサス・インスツルメンツ合同会社 金属充填ディープソースコンタクトを備えたパワーｍｏｓｆｅｔ
US10050025B2 (en) * 2016-02-09 2018-08-14 Texas Instruments Incorporated Power converter monolithically integrating transistors, carrier, and components
US10229993B2 (en) * 2016-03-14 2019-03-12 Maxin Integrated Products, Inc. LDMOS transistors including resurf layers and stepped-gates, and associated systems and methods
US9741849B1 (en) * 2016-04-08 2017-08-22 Globalfoundries Singapore Pte. Ltd. Integrated circuits resistant to electrostatic discharge and methods for producing the same
US10199475B2 (en) * 2016-05-24 2019-02-05 Maxim Integrated Products, Inc. LDMOS transistors and associated systems and methods
US10978869B2 (en) 2016-08-23 2021-04-13 Alpha And Omega Semiconductor Incorporated USB type-C load switch ESD protection
CN106876464A (zh) * 2016-12-29 2017-06-20 西安电子科技大学 一种横向双扩散金属氧化物半导体场效应管
TWI658568B (zh) * 2017-01-03 2019-05-01 Leadtrend Technology Corporation 高壓半導體元件以及同步整流控制器
US10083897B2 (en) * 2017-02-20 2018-09-25 Silanna Asia Pte Ltd Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
CN113330578A (zh) * 2019-01-21 2021-08-31 日产自动车株式会社 半导体装置及其制造方法
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US11004789B2 (en) * 2019-09-30 2021-05-11 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device including back side power supply circuit
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
US12021033B2 (en) 2020-05-15 2024-06-25 Taiwan Semiconductor Manufacturing Ltd. Integrated circuit device having active region coupled to metal layers on opposite sides of substrate, and method
CN112151599B (zh) * 2020-09-27 2022-07-19 杰华特微电子股份有限公司 半导体功率器件的制造方法
CN116508135B (zh) 2020-12-04 2024-06-04 安普莱西娅有限责任公司 具有自对准体和混合源的ldmos
US20240153876A1 (en) * 2022-11-03 2024-05-09 Globalfoundries Singapore Pte. Ltd. Transistors having backside contact structures

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5236854A (en) * 1989-12-11 1993-08-17 Yukio Higaki Compound semiconductor device and method for fabrication thereof
JPH0897375A (ja) * 1994-07-26 1996-04-12 Toshiba Corp マイクロ波集積回路装置及びその製造方法
US6285177B1 (en) 2000-05-08 2001-09-04 Impala Linear Corporation Short-circuit current-limit circuit
US6650165B1 (en) 2002-05-02 2003-11-18 Micrel, Incorporated Localized electrostatic discharge protection for integrated circuit input/output pads
US6521923B1 (en) * 2002-05-25 2003-02-18 Sirenza Microdevices, Inc. Microwave field effect transistor structure on silicon carbide substrate
US6583476B1 (en) 2002-06-28 2003-06-24 Micrel, Inc. Electrostatic discharge protection for integrated semiconductor devices using channel stop field plates
US6696731B2 (en) 2002-07-26 2004-02-24 Micrel, Inc. ESD protection device for enhancing reliability and for providing control of ESD trigger voltage
US6815800B2 (en) 2002-12-09 2004-11-09 Micrel, Inc. Bipolar junction transistor with reduced parasitic bipolar conduction
US6864537B1 (en) 2003-01-03 2005-03-08 Micrel, Incorporated Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US6861711B2 (en) 2003-01-03 2005-03-01 Micrel, Incorporated Thick gate oxide transistor and electrostatic discharge protection utilizing thick gate oxide transistors
US6888710B2 (en) 2003-01-03 2005-05-03 Micrel, Incorporated Insulated gate bipolar transistor and electrostatic discharge cell protection utilizing insulated gate bipolar transistors
US7838875B1 (en) * 2003-01-22 2010-11-23 Tsang Dean Z Metal transistor device
US7087973B2 (en) 2003-04-01 2006-08-08 Micrel, Incorporated Ballast resistors for transistor devices
US6818950B1 (en) 2003-05-13 2004-11-16 Micrel, Inc. Increasing switching speed of geometric construction gate MOSFET structures
US6825531B1 (en) 2003-07-11 2004-11-30 Micrel, Incorporated Lateral DMOS transistor with a self-aligned drain region
US20050036251A1 (en) 2003-08-12 2005-02-17 Micrel, Incorporated Electrostatic discharge protection for trim-diodes
US20050275027A1 (en) 2003-09-09 2005-12-15 Micrel, Incorporated ESD protection for integrated circuits
US7119399B2 (en) * 2004-02-27 2006-10-10 Infineon Technologies Ag LDMOS transistor
US7145211B2 (en) 2004-07-13 2006-12-05 Micrel, Incorporated Seal ring for mixed circuitry semiconductor devices
US7087959B2 (en) * 2004-08-18 2006-08-08 Agere Systems Inc. Metal-oxide-semiconductor device having an enhanced shielding structure
US7439580B2 (en) * 2004-09-02 2008-10-21 International Rectifier Corporation Top drain MOSgated device and process of manufacture therefor
US7608907B2 (en) 2005-01-06 2009-10-27 Micrel, Inc. LDMOS gate controlled schottky diode
US7064407B1 (en) 2005-02-04 2006-06-20 Micrel, Inc. JFET controlled schottky barrier diode
US7420247B2 (en) * 2005-08-12 2008-09-02 Cicion Semiconductor Device Corp. Power LDMOS transistor
US8218276B2 (en) 2006-05-31 2012-07-10 Alpha and Omega Semiconductor Inc. Transient voltage suppressor (TVS) with improved clamping voltage
US7666723B2 (en) * 2007-02-22 2010-02-23 International Business Machines Corporation Methods of forming wiring to transistor and related transistor
US8003525B2 (en) * 2007-06-29 2011-08-23 Fujitsu Limited Semiconductor device and method of manufacturing the same
US20090115018A1 (en) 2007-11-01 2009-05-07 Alpha & Omega Semiconductor, Ltd Transient voltage suppressor manufactured in silicon on oxide (SOI) layer
US8143654B1 (en) * 2008-01-16 2012-03-27 Triquint Semiconductor, Inc. Monolithic microwave integrated circuit with diamond layer
US7851314B2 (en) 2008-04-30 2010-12-14 Alpha And Omega Semiconductor Incorporated Short channel lateral MOSFET and method
US7919817B2 (en) 2008-05-16 2011-04-05 Alpha & Omega Semiconductor Ltd. Electrostatic discharge (ESD) protection applying high voltage lightly doped drain (LDD) CMOS technologies

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US8816476B2 (en) 2014-08-26
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