CN105027282A - 启用通孔的层叠封装 - Google Patents

启用通孔的层叠封装 Download PDF

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Publication number
CN105027282A
CN105027282A CN201480012349.5A CN201480012349A CN105027282A CN 105027282 A CN105027282 A CN 105027282A CN 201480012349 A CN201480012349 A CN 201480012349A CN 105027282 A CN105027282 A CN 105027282A
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China
Prior art keywords
package
packaging
package die
base plate
mediator
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CN201480012349.5A
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English (en)
Inventor
D·J·利斯
V·拉马钱德兰
J·S·李
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN105027282A publication Critical patent/CN105027282A/zh
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Abstract

启用通孔的层叠封装电路包括第一封装(316)，第一封装(316)包括具有多个穿基板通孔(TSV)(322)的第一封装管芯(310)。TSV被配置成承载用于至少一个第二封装管芯(315)的输入/输出信令。

Description

启用通孔的层叠封装
相关申请的交叉引用
本申请要求于2013年3月8日提交的美国非临时申请No.13/791,223的优先权，其全部内容通过援引纳入于此。
技术领域
本申请涉及集成电路封装，尤其涉及其中底层封装包括穿基板通孔(TSV)的层叠封装(PoP)结构。
背景技术
层叠封装(PoP)结构已被开发用于其中必须保留电路板空间的应用，诸如蜂窝电话和其他便携式设备。顶部封装通常是存储器封装，而底部封装一般是处理器封装。与诸如堆叠式管芯电路之类的其他办法相比，PoP技术已被证明是非常流行的。例如，制造商可容易地在PoP电路中替换不同的存储器封装而非绑定到特定存储器，这降低了成本。此外，顶部和底部封装可独立地测试。相反，堆叠式管芯设计中的劣质管芯要求丢弃剩余的良好管芯。
尽管使用PoP结构的集成电路的封装非常流行，但在此封装工艺中保留了挑战，诸如减小顶部封装与底部封装之间的互连跨距(pitch)。随着技术演进，顶部封装与底部封装之间的总线宽度相应地增大。但顶部基板与底部基板之间的球跨距或穿模通孔跨距仅可容纳特定数目的信号。为了解决小跨距的要求，已开发了嵌模PoP(MEP)。在MEP中，可在顶部封装和底部封装之间包括附加基板。例如，图1解说了MEP 100，其包括耦合至附加基板110的顶部封装105。以此方式，附加基板110可重新分布信号以辅助容纳来往于顶部封装105中的管芯的增大数目的信号。然而，即使使用附加基板110，还是保留了与互连120(诸如可被置于附加基板110与底部封装基板111之间的焊球或焊柱)的数目相关的限制，因为互连120必须被放置在底部封装管芯115之外。图2解说了互连120如何被安排在附加基板110面对底部管芯115的区域220周围的底部表面上。互连120由此被限于附加基板110在区域200之外的环状外部区域。互连120被类似地限于底部封装基板111的环状外部区域，这进而限制了能在顶部封装与底部封装之间交换的I/O信号的数目。相似的互连限制存在于其他常规PoP中。
因此，在本领域中需要改进的PoP架构以提供增大的密度。
概述
启用通孔的层叠封装(PoP)电路包括第一封装管芯，该第一封装管芯具有多个穿基板通孔(TSV)。TSV被配置成承载用于邻接的第二封装中的至少一个第二封装管芯的输入/输出信令。如本文所使用的，“输入/输出”信令包括由(诸)第二封装管芯接收的所有电子信号，包括功率和接地。类似地，“输入/输出信令”包括来自(诸)第二封装管芯的所有输出信号。
由于第一封装管芯中的TSV承载用于(诸)第二封装管芯的输入/输出信令，因此不需要第二封装基板与第一封装基板之间的穿模通孔柱或焊球互连来容纳输入/输出信令。这是非常有利的，因为第一封装基板随后可被调节大小为正好容纳第一封装管芯。相反，常规PoP底部封装基板要求实质上未被占据的第一封装基板区域以容纳至第二封装基板的互连。
尽管第一封装管芯可包括背部重分布层以增大用于到第二封装的输入/输出信令的路由选项，但包含TSV的中介体也可被安排在第二封装基板与第一封装管芯之间以辅助输入/输出信令的重分布。中介体可以是无源的或者可包括有源器件，类似于第一封装管芯中的那些器件。不论是否包括中介体，由于跨底部封装管芯的表面区域的TSV的高跨距密度，因而结果所得的启用TSV的PoP(TEP)可有利地容纳去往顶部封装的大量输入/输出信号。
附图简述
图1是现有技术的嵌模PoP(MEP)的剖面视图。
图2是图1的MEP中附加基板的面对底部封装的表面的平面图。
图3A是包括中介体的启用穿硅堆叠(TSS)的PoP(TEP)的剖面视图。
图3B是不具有中介体的TEP的剖面视图。
图4是图3A和3B的TEP中顶部封装基板的面对底部封装的表面的平面图。
图5是TEP底部封装在初始制造步骤期间的剖面视图。
图6是图5的TEP底部封装在后续制造步骤之后的剖面视图。
图7是图6的TEP底部封装在最终制造步骤之后的剖面视图。
图8是包括图7的TEP底部封装在内的完整TEP的剖面视图。
图9是包括多个中介体的TEP的剖面视图。
图10解说了根据本文所公开的实施例的纳入TEP的多个电子***。
详细描述
为了解决本领域中为(一个或多个)顶部封装管芯容纳增大数目的输入和输出信号的需要，提供了改进的层叠封装(PoP)结构，其不遭受常规PoP的封装到封装互连的限制。
综览
在本文所公开的改进的PoP中，第一封装管芯包括多个穿基板通孔(TSV)以容纳(一个或多个)第二封装管芯的输入和输出信令需求。第一封装管芯的整个区域由此可被用于与第二封装的互连。相反，常规PoP(诸如图1的MEP100)被限于第一封装管芯之外的区域，如以上所讨论的。
为了避免关于何为“顶部”对“底部”封装的任何模糊性，本文所公开的改进的PoP架构的底部封装被称为第一封装。类似地，顶部封装被称为第二封装。本文所公开的改进的PoP架构可为第二封装管芯容纳相当高数目的I/O信号，因为第一封装管芯区域随后通过其TSV可用于容纳这些I/O信号。另外，第一封装基板大小可被减小，因为第一封装基板基本没有表面区域必须要在容纳第一封装管芯的版图所必须的表面区域之外。相反，常规PoP需要第一封装基板上在第一封装管芯版图之外的环形外部区域以具有足够大小来容纳封装到封装互连。结果得到的第一封装基板的增大的大小增加了常规PoP变形的可能性。而本文所公开的改进的PoP可通过第一封装基板的减小的大小来有利地减小变形。此外，穿模通孔或用来形成常规封装到封装互连的其他技术对于所公开的改进的PoP而言不是必要的。
以下讨论在不失一般性的情况下将假定第一封装管芯是硅管芯，由此其包含的穿基板通孔是穿硅通孔。但将领会，本文所公开的封装概念和架构广泛适用于其他类型的半导体管芯。如封装领域中已知的，使用穿硅通孔来构造堆叠式器件的工艺被称为穿硅堆叠(TSS)工艺。本文所公开的结果所得的改进的PoP由此被标示为启用TSS的PoP(TEP)。TEP可包括中介体以提供其第一和第二封装之间的输入/输出(I/O)信令的增强型重分布。替换地，TEP可具有通过互连耦合在一起的第一和第二封装，而无需使用中介体。包含中介体的实施例将首先讨论，随后讨论直接耦合的实施例(无中介体)。
包括中介体的启用TSS的PoP
图3A解说了示例启用TSS的PoP(TEP)300。第二封装315包括如PoP技术中常规的第二封装基板320。第一封装316包括第一封装基板360，第一封装管芯310使用互连(诸如受控坍塌芯片连接(C4)倒装凸块309)安装在第一封装基板360上，其也是PoP技术中常规的。第一封装基板360和第二封装基板320各自可包括有机基板、半导体基板，诸如硅、玻璃、陶瓷、或其他合适的材料。无论使用何种材料来构造封装基板，关于MEP 100讨论的互连120对于容纳用于第二封装315中的多个第二封装管芯324的输入/输出(I/O)信令不是必要的。代替地，第一封装管芯310中的穿硅通孔322容纳用于第二封装管芯324的所有I/O信令。如本文所使用的，“输入/输出信令”包括由(诸)第二封装管芯接收的所有电子信号，包括功率和接地。类似地，“输入/输出信令”包括来自(诸)第二封装管芯的所有输出信号。TEP 300的替换实施例可包括单个第二封装管芯324，而非多个此类管芯。
本文所使用的术语“第一封装”和“第二封装”简单地标示PoP技术中已知的不同封装。关于此，图3A的第一封装316对应于“底部封装”，如该术语在PoP技术中使用的一样。类似地，第二封装315对应于“顶部封装”，如该术语在PoP技术中使用的一样。但对“顶部”或“底部”的引述不被约束到任何特定的参考系。换言之，底部封装不会简单地因为PoP被翻过来而成为顶部封装。
由于实质上第一封装管芯310的整个区域可被用于穿硅通孔322，因此避免了PoP技术中关于第二封装管芯I/O的互连限制。相反，现有技术PoP架构要求顶部封装基板和底部封装基板之间的互连以避开底部封装基板上由底部封装管芯占据的基板区域，诸如以上关于MEP 100讨论的。因此，与本文所公开的改进的PoP相比，现有技术PoP架构具有受限的信号密度，因为封装到封装互连不被限于放置在底部封装基板的***。
TEP 300包括具有穿基板通孔(TSV)321的中介体305，TSV 321通过对应的互连(诸如微凸块323)耦合至第一封装管芯310中的穿硅通孔322。中介体305可包括半导体基板，诸如硅、玻璃、或其他合适的材料。如果中介体305包括硅基板，则TSV 321是穿硅通孔。另一方面，如果中介体305包括玻璃，则TSV 332是穿玻璃通孔(TGV)。以下讨论在不失一般性的情况下将假定TSV 321是穿硅通孔。
中介体305允许至第二封装管芯324的I/O信令的附加重分布。替换地，中介体305中的穿硅通孔321可通过第一封装管芯310的背部上的背部重分布层(未图解)耦合至第一封装管芯的穿硅通孔322。第二封装基板320的下表面上的焊盘(未图解)通过互连(诸如凸块325)耦合至中介体穿硅通孔321。更一般地，第二封装基板320可被认为具有第一表面以及相反的第二表面。第二封装管芯324安装在第二封装基板320的第一表面上，而凸块325连接至第二封装基板320的相反的第二表面。
在TEP 300中，第二封装管芯324被线焊到第二封装基板320，尽管也可使用其他安装技术，诸如表面安装。线焊承载第二封装管芯324与第二封装基板320之间的I/O信令。进而，用于第二封装管芯324的I/O信令通过凸块325承载在第二封装基板320与中介体305之间。最终，用于第二封装管芯324的I/O信令通过中介体的穿硅通孔321和第一封装管芯的穿硅通孔322被承载在中介体305与第一封装管芯310之间。用于第二封装管芯324的I/O信令可源自或被传送至外部设备。此类外部设备I/O将通过第一封装管芯310中的穿硅通孔322、凸块309、第一封装基板360和第一封装基板360的下表面上的球361承载在中介体305与外部设备之间。在一些实施例中，中介体305可包括有源器件和/或无源组件。
如本文所使用的，“凸块”被用来标示诸如焊球或凸块之类的结构。另外，此术语将被理解为还包括诸如铜柱之类的结构。关于此，凸块325一般是指从第二封装基板320的底部表面上的焊盘耦合至中介体305上的穿硅通孔321的互连结构。
直接耦合的启用TSS的PoP(无中介体)
图3B解说了其中TEP 350不包括中介体的替换实施例。第二封装基板320的下表面上的焊盘上的凸块325由此将通过第一封装管芯焊盘(未图解)直接耦合至第一封装管芯的穿硅通孔322(或者通过背部重分布层耦合至穿硅通孔322。)与TEP 300相比，TEP 350需要较少的制造步骤。然而，中介体305实现了至第二封装管芯324的I/O信令的附加重分布。凸块325可包括互连，诸如铜柱(微凸块)、直接金属到金属焊接、或者坍塌芯片连接(C4)凸块或焊球。
无论是否包括中介体，凸块325不限于由第一封装管芯310占据的区域之外的环形区域，这与常规PoP(诸如MEP 100)形成直接对比。图4解说了第二封装基板320的下表面的平面图以示出凸块325可如何使用面对第一封装管芯310(对于无中介体实施例，诸如TEP 350)或中介体305(在包含中介体的实施例中，诸如TEP 300)的整个区域400。以此方式，与常规PoP实施例相比，可容纳显著更多的I/O信号。此外，由于第二封装基板320可跨面对第一封装管芯310(或中介体305)的整个表面区域400接纳凸块325，因此第二封装基板320和第一封装基板360的大小可相应地减小。相反，MEP 100将需要较大的基板大小，因为它必须将其互连120放置在底部管芯115之外。以此方式，本文所公开的TEP与类似的MEP相比将有利地具有较小变形，因为变形(尤其)取决于顶部和底部封装的基板的大小。
示例制造方法
用于包含中介体的TEP实施例的第一封装的制造现在将关于图5到8来讨论。该制造过程使用纳入穿硅通孔505的第一封装管芯500来不仅容纳第一封装管芯500与第二封装管芯之间的I/O信令，而且还容纳至(一个或多个)第二封装管芯的外部I/O信令。例如，穿硅通孔505可容适第二封装管芯的接地和功率需求。如图5所示，第一封装管芯500的有效表面501上的焊盘(未图解)通过倒装凸块510安装到第一封装基板520上的对应焊盘(同样出于解说清楚目的未示出)。然而，将领会，在替换实施例中，第一封装管芯500的有效表面取向可被颠倒。换言之，本文所公开的有利的启用TSS的PoP概念可被用于任何有效表面取向。随后可使用毛细管作用动作来施加底填剂515(诸如环氧树脂或其他聚合材料)。替换地，可在施加凸块510的同时预施加底填剂515。
制造有穿硅通孔的中介体600随后可被焊接到第一封装管芯500的背表面605，如图6中所示。出于解说清楚的目的，中介体600中的穿硅通孔未示出。凸块610响应于热压缩而将第一封装管芯500上的焊盘耦合至中介体600上的对应焊盘。替换地，可使用其他焊接技术来将中介体600焊接到第一封装管芯500，诸如回流焊接和超声波热焊。
随后可施加模制料(mold compound)715以完成TEP第一封装700，如图7中所示。中介体600的上表面被暴露于模制料715中，从而模制料715仅部分包住中介体600。以此方式，中介体600的被暴露表面上的焊盘(未图解)随后可如图8中所示地通过互连805焊接到第二封装800的第二封装基板810的下表面上的对应焊盘以完成包含中介体TEP 820的制造。
附加特征和实施例
如以上所讨论的，对于包括中介体的TEP实施例，该中介体可以是无源的或包含有源元件。关于此，有源的中介体包括可与以上讨论的第一封装管芯相当的另一管芯。可在第一封装内堆叠若干此类包含TSV的管芯。此外，可并行使用多个中介体，如图9关于TEP 900所示。具体而言，中介体905和中介体910两者均面对第一封装管芯915的背表面。关于此，中介体905和中介体910在单层中并行排列，这与被堆叠形成对比。
再次参照第一封装管芯310，第一封装管芯310可被认为包括用于承载用于至少一个第二封装管芯的输入/输出信令的装置。在一个实施例中，此类装置包括TSV 322。在替换实施例中，该装置可包括深扩散区，该深扩散区耦合在第一封装管芯310的背表面上的焊盘与第一封装管芯310的有效前表面上的有源电路***之间。
示例电子***
将领会，本文所公开的TEP结构可被纳入各式各样的电子***中。例如，如图10中所示，蜂窝电话1000、膝上型设备1005和平板PC 1010都可以包括根据本公开构造的TEP。其他示例性电子***(诸如音乐播放器、视频播放器、通信设备和个人计算机)也可以配置有根据本公开的TEP。
如本领域普通技术人员至此将会领会并取决于手头的具体应用的，可以在本公开的设备的材料、装置、配置和使用方法上做出许多修改、替换和变动而不会脱离本公开的精神和范围。有鉴于此，本公开的范围不应当被限定于本文中所解说和描述的特定实施例(因为其仅是藉其一些示例来解说和描述的)，而应当与所附权利要求及其功能等同方案完全相当。

Claims (28)

1.一种集成电路封装，包括：
第一封装，其包括第一封装基板和安装于所述第一封装基板上的第一封装管芯，其中所述第一封装管芯包括多个第一穿基板通孔(TSV)；以及
第二封装，其包括第二封装基板和安装于所述第二封装基板的第一表面上的至少一个第二封装管芯，所述第二封装基板具有相反的第二表面，所述第二表面具有附连于其上的多个第一互连，其中所述第一TSV被配置成通过所述第一互连耦合至所述至少一个第二封装管芯，以使得用于所述至少一个第二封装管芯的所述输入/输出信令由所述第一TSV传导。
2.如权利要求1所述的集成电路封装，其特征在于，进一步包括安排在所述第一封装管芯与所述第二封装基板之间的中介体，其中所述中介体包括通过多个第二互连耦合至所述第一TSV的多个第二TSV。
3.如权利要求2所述的集成电路封装，其特征在于，所述第一封装管芯包括硅管芯，并且所述第一TSV包括第一穿硅通孔，并且其中所述中介体包括硅基板且所述第二TSV包括第二穿硅通孔。
4.如权利要求1所述的集成电路封装，其特征在于，所述至少一个第二封装管芯包括多个第二封装管芯。
5.如权利要求4所述的集成电路封装，其特征在于，所述第二封装管芯被线焊到所述第二封装基板的所述第一表面。
6.如权利要求1所述的集成电路封装，其特征在于，所述第一封装管芯具有通过多个第二互连耦合至所述第一封装基板的第一表面的有效第一表面。
7.如权利要求6所述的集成电路封装，其特征在于，所述多个第二互连包括倒装互连。
8.如权利要求2所述的集成电路封装，其特征在于，所述中介体包括多个堆叠的中介体。
9.如权利要求2所述的集成电路封装，其特征在于，所述中介体包括在所述第二封装基板与所述第一封装管芯之间的单个层中并行排列的多个中介体。
10.如权利要求2所述的集成电路封装，其特征在于，所述中介体包括多个有源器件。
11.如权利要求6所述的集成电路封装，其特征在于，所述第一封装管芯包括所述第一封装管芯的相反的第二表面上的背部重分布层。
12.如权利要求1所述的集成电路封装，其特征在于，所述集成电路封装被纳入到蜂窝电话、膝上型设备、平板设备、音乐播放器、通信设备、计算机和视频播放器中的至少一者。
13.一种方法，包括：
将第一封装管芯安装到第一封装基板上，其中所述第一封装管芯包括多个第一穿基板通孔(TSV)，所述第一封装管芯具有面对所述第一封装基板的第一表面以及相反的背表面；以及
向所述第一封装管芯的所述背表面安装包括多个第二TSV的中介体，以使得所述多个第一TSV通过多个互连耦合至所述多个第二TSV，其中所述第一TSV和所述第二TSV被配置成传导用于至少一个第二封装管芯的输入/输出信令。
14.如权利要求13所述的方法，其特征在于，将所述第一封装管芯安装到第一封装基板上包括：将所述第一封装管芯的第一表面倒装地安装到所述第一封装基板的第一表面上。
15.如权利要求13所述的方法，其特征在于，安装所述中介体包括将所述中介体的第一表面通过所述多个互连热压缩焊接到所述第一封装管芯的所述背表面以形成第一封装。
16.如权利要求15所述的方法，其特征在于，进一步包括：将包括至少一个第二封装管芯的第二封装安装到所述第一封装上。
17.如权利要求15所述的方法，其特征在于，所述中介体包括玻璃，并且其中所述多个第二TSV包括多个穿玻璃通孔(TGV)。
18.一种用于层叠封装电路的第一封装，包括：
第一封装基板；以及
第一封装基板，其中所述第一封装管芯包括被配置成承载用于至少一个第二封装管芯的输入/输出信令的多个第一穿基板通孔(TSV)。
19.如权利要求17所述的底部封装，其特征在于，进一步包括：包括耦合至所述多个第一TSV的多个第二TSV的中介体。
20.如权利要求18所述的第一封装，其特征在于，所述中介体包括多个中介体。
21.一种集成电路封装，包括：
第一封装，其包括第一封装基板以及安装于所述第一封装基板上的第一封装管芯；以及
第二封装，其包括第二封装基板以及安装在所述第二封装基板的第一表面上的至少一个第二封装管芯，其中所述第一封装管芯包括用于承载用于所述至少一个第二封装管芯的输入/输出信令的装置。
22.如权利要求21所述的集成电路封装，其特征在于，所述装置包括多个穿基板通孔(TSV)。
23.如权利要求21所述的集成电路封装，其特征在于，所述装置包括多个暴露的深扩散区。
24.如权利要求21所述的集成电路封装，其特征在于，进一步包括：包括耦合在所述装置与所述第二封装基板之间的多个穿基板通孔的中介体。
25.如权利要求24所述的集成电路封装，其特征在于，所述中介体包括玻璃中介体，并且其中所述穿基板通孔是穿玻璃通孔。
26.如权利要求24所述的集成电路封装，其特征在于，所述中介体包括硅中介体，并且其中所述穿基板通孔是穿硅通孔。
27.如权利要求21所述的集成电路封装，其特征在于，所述至少一个第二封装管芯包括多个第二封装管芯。
28.如权利要求27所述的集成电路封装，其特征在于，所述多个第二封装管芯被线焊到所述第二封装基板的所述第一表面。
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