CN1047470C - 半导体器件 - Google Patents
半导体器件 Download PDFInfo
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- CN1047470C CN1047470C CN94190177A CN94190177A CN1047470C CN 1047470 C CN1047470 C CN 1047470C CN 94190177 A CN94190177 A CN 94190177A CN 94190177 A CN94190177 A CN 94190177A CN 1047470 C CN1047470 C CN 1047470C
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 179
- 239000000758 substrate Substances 0.000 claims abstract description 69
- 239000004020 conductor Substances 0.000 claims description 61
- 238000005452 bending Methods 0.000 claims description 3
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- 238000000034 method Methods 0.000 abstract description 12
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 9
- 239000004411 aluminium Substances 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
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- 230000002093 peripheral effect Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 150000001398 aluminium Chemical class 0.000 description 1
- 239000003518 caustics Substances 0.000 description 1
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
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Abstract
对于具有绝缘性的挠性基底的电路基板,将半导体芯片装配到其器件孔内。半导体芯片的凸起利用单点焊接法与导体图形中突出到器件孔内的引线部分连接。在电路基板上,在器件孔的四角部分具有与半导体芯片重合的基底的重叠部,同时,还具有将器件孔分割为4个洞的重叠部。在与这些重叠部重叠的半导体芯片的面上,具有不与导体图形连接、位于电路基板与半导体芯片之间以确保该处具有指定的间隙的假凸起。
Description
技术领域
本发明涉及半导体器件,特别是涉及具有适合于进行芯片尺寸比较大的半导体芯片实装的结构和适合于半导体芯片向多用于石英电子手表等的软性基板上实装的结构的半导体器件。
背景技术
将半导体芯片向电路基板上安装时,例如,如图7所示,在电路基板51上形成的导体图形52中,突出到器件孔53内的引线部分521与半导体芯片54的凸起541焊接后从器件孔53填充模塑材料55时,为了使半导体芯片54的边缘与导体图形52不短路,通常从下方对引线部分521进行成形加工。
但是,在这种安装结构中,由于将引线部分521弯折得较大,所以,存在半导体装置增厚了相当于该弯折部分的厚度的问题。另外,由于引线部分521的成形加工的数量越多,每根引线部分521的形状及位置的偏差越大,所以,实装大的半导体芯片54时,存在因成形加工的偏差而造成引线部分521与凸起541焊接不上的问题。并且,还存在由于半导体芯片54的尺寸越大,器件孔55越要增大,从而半导体装置的平面尺寸也就越大,所以,不能装配到像石英电子手表那样的要求小型化的电子仪器上那样的问题。
于是,人们针对安装大的半导体芯片54时的变形等问题从提高稳定性的目的出发,设想了通过设置与内部电路电绝缘的增加强度用的假凸起,增加与假凸起数一致的接合点个数,以提高半导体芯片与电路基板52的接合强度的方法。但是,在这种结构中,为了接合假凸起,也必须对它们进行成形加工,所以,由成形加工引起的上述问题仍然不能消除。
另外,作为适合于半导体器件的薄型化的实装结构,例如,有如图8所示的那样在对在半导体芯片61上形成的焊锡凸起62施加压力的状态下对它进行加热从而将焊锡凸起62与电路基板的导体图形64接合的结构。在这种实装结构中,由于在电路基板63上有与半导体芯片61的功能面重叠的部分,所以,也可以在该重叠部分形成导体图形64。因此,图形设计的自由度大,从而适合于半导体器件的薄型化。但是,由于焊锡凸起62的制造工序复杂,所以,存在制造成本高的问题。另外,在将半导体芯片安装到电路基板63上的工序中,在对半导体芯片61加热后,需要有冷却工序,因而制造半导体器件的周期长,所以,存在生产效率低,难于降低成本的问题。
在使用这种焊锡凸起62的安装结构中,为了防止电路基板63与半导体芯片61之间短路,提出了增厚焊锡凸起62或者形成假焊锡凸起的方法。但是,只要利用焊锡凸起,就存在上述制造上的问题。
为了解决这些问题,本发明旨在提供一种半导体器件,即使采用单点焊接法及同轴焊接法,也可以既能确保可靠性大于先有的安装结构,又可以实现薄型化和低成本化。另外,本发明还旨在提供可以提高图形设计的自由度的半导体器件。
本发明提供了一种半导体器件,具有在绝缘性的基底上形成导体图形的电路基板和装配到该电路基板的器件孔内的半导体芯片,上述导体图形中突出到上述器件孔内的引线部分与上述半导体芯片的凸起相连接,上述电路基板具有与上述半导体芯片重合的重叠部,在该重叠部和与其重叠的上述半导体芯片的面上至少在其中的一侧形成将上述引线部分与上述凸起连接的接合工序前后厚度不变化的衬垫部,该衬热部位于上述电路基板与上述半导体芯片之间,确保该处具有指定的间隙;一部分接合的引线框位于器件孔中,并且在接合期间直接对引线框加压;以及在弯曲的同时形成引线框。
例如,在与重叠部重叠的半导体芯片的面上,形成与导体图形不接触的作为位于电路基板与半导体芯片之间以确保指定间隙的衬垫部的假凸起。
即,利用经过接合工序不会被压扁仍保持原厚状态的假凸起,可在电路基板与半导体芯片之间自动地确保其间隙,所以,半导体芯片的边缘与导体图形之间不会发生短路。因此,不论采用单点焊接法还是同轴焊接法,对于引线部分都可以不进行成形加工。另外,也不必使用难于降低成本的焊锡凸起。所以,与先有的半导体器件相比,可靠性高、并且可以实现能获得薄型化和低成本化的半导体器件。而且,间隙的尺寸由预先设定的假凸起等衬垫部初始的厚度尺寸决定,所以,可靠性高。另外,由于假凸起可以与接合用的凸起同时形成,所以,不会提高半导体芯片的成本。
在本发明中,所谓“假”,是指电路上不需要,上述假凸起或者后面所述的假焊接区表示与半导体芯片内的电路是电绝缘的。另外,在本发明中,所谓“凸起”,是指从半导体芯片的功能面等突出的厚的电极,所谓“焊接区”是指不从半导体芯片的功能面突出的电极。
另外,除了假凸起和假焊接区以外,在电路基板的一侧,还可以将与其他电路不连接的、电路上不需要的假导体图形作为衬垫部。
在本发明中,在重叠部分,最好是导体图形与假凸起相重叠。因为假凸起与导体图形本身重叠,可以更可靠地确保半导体芯片的边缘与导体图形之间的间隙。
另外,在别的形态中,其特征是在与半导体芯片重叠的电路基板的重叠部分,形成与接合用的电极不接触的导体图形的凸起,作为位于电路基板与半导体芯片之间用以确保指定间隙的衬垫部。这时,借助于经过接合工序也不会被压扁的仍保持其原来厚度状态的导体图形的凸起,可以自动地确保电路基板与半导体芯片之间的间隙,所以,不论采用单点焊接法还是同轴焊接法,都不需要进行形成加工。
这时,在半导体芯片一侧形成作为接合用的电极的凸起,最好在与凸起重叠的位置形成不与其接合的假凸起。因为这样便可将间隙的尺寸扩大与假凸起的厚度对应的尺寸。
另外,也可以在半导体芯片一侧形成作为接合用电极的焊接区,而在与凸起重叠的位置形成与其不连接的假凸起。
在本发明中,当器件孔具有大致呈四角形的轮廓时,最好在其四个角部分形成重叠部,也可以在器件孔的各边部分形成重叠部。这样,在稳定状态下便可确保电路基板与半导体芯片之间的间隙。
另外,最好将重叠部形成到器件孔的内侧,利用该重叠部将器件孔分割为多个洞。这样,当将模塑材料注入器件孔内时,如果从各个洞注入,模塑材料容易均匀分布。特别是,最好使重叠部通过器件孔的大致中心位置将器件孔分割为多个洞,而且在与该大致中心位置对应部分重叠部形成贯通孔。这样,当注入模塑材料时,可以使空气从贯通孔排出。
另外,如果预先将器件孔分割为多个洞,则即使在半导体芯片的功能面一侧进行布线,也可以形成具有横跨该洞的跨接部的导体图形。这种跨接部由重叠部支持,处于被加固的状态,所以,强度很大。因此,既可以保证很高的可靠性,又可以提高配线图形设计的自由度。
图1是本发明第1实施例的半导体器件的结构平面图。
图2(a)是沿图1中Ⅰ-Ⅱ线的纵剖面图,图2(b)是沿图1中Ⅰ-Ⅲ线的纵剖面图。
图3(a)是本发明第1实施例的半导体器件的结构在焊接前的状态下示意的纵剖面图,图3(b)是本发明第1实施例的半导体器件的结构在焊接后的状态下示意的纵剖面图。
图4(a)是本发明第2实施例的半导体器件的结构在焊接前的状态下示意的纵剖面图,图4(b)是本发明第2实施例的半导体器件的结构在焊接后的状态下示意的纵剖面图。
图5(a)是本发明第3实施例的半导体器件的结构在焊接前的状态下示意的纵剖面图,图5(b)是本发明第3实施例的半导体器件的结构在焊接后的状态下示意的纵剖面图。
图6是作为本发明的另一个实施例,在第1实施例的半导体器件中采用同轴焊接法的接合工序的示意剖面图。
图7是先有的半导体器件的结构的纵剖面图。
图8是先有的另一个半导体器件的结构的纵剖面图。
下面,参照附图说明本发明实施例的半导体器件。第1实施例:
图1是本发明第1实施例的半导体器件的结构平面图,图2(a)是沿其Ⅰ-Ⅱ线的纵剖面图,图2(b)是沿其Ⅰ-Ⅲ线的纵剖面图。
在图1和图2(a),(b)中,本例的半导体器件1是作为模拟多功能电子表的电路块而使用的器件,具有电路基板2和装配着CPU的半导体芯片3。
半导体芯片3的功能面30的大小约为5mm×5mm,在其上面形成需要连接的36个凸起31 ,通常,在石英电子手表中使用的半导体芯片,其大小约为2mm×2mm,凸起的数量为10个,所以,本例的半导体芯片3与通常的半导体芯片相比,面积约为其6倍,连接点也为其2倍以上。
电路基板2由挠性基材21和导体图形22(引线)构成,挠性基材21由厚度约130μm的聚酰亚胺树脂制的带状材料构成;导体图形22与该基材21粘接成一体。导体图形22是粘接在基材21上的铜箔形成指定的图形的导电部件,在其表面镀一层厚度约1μm的金。
在电路基板2上,将与半导体芯片3的装配位置对应的部分的基底21除掉,形成轮廓呈四角形的器件孔23,将半导体芯片3与该器件孔23配合装置并固定。
对于该固定结构,将在后面介绍。但是,其结构是在导体图形22中,利用单点焊接法将突出到器件孔23的内侧的引线部分221与半导体芯片3的凸起31逐个连接好后,将模塑材料4填充到器件孔23的内部。引线部分221的宽度比其他导体图形22的宽度窄,容易与凸起31进行连接。这里,凸起31在与引线部分221连接时被压扁变薄,引线部分221的端部稍稍向下弯曲。
在具有这种接合结构的半导体器件1中,本例中是在器件孔23的四个角的区域A、B、C、D处形成与半导体芯片3的四角相互重合的电路基板2的重叠部211。另外,在与重叠部211相互重合的半导体芯片3的功能面30上的4个地方,分别形成假凸起32a(衬垫部)。该假凸起32a与导体图形2中扩大了其宽度的扩展部分20重叠。即使半导体芯片3的位置多少发生一些偏离,假凸起32a也能保证可靠地与导体图形2重叠。但是,假凸起32a不论与半导体芯片3内部的哪个电路都没有电气连接,所以,不会成为半导体器件1的误动作的原因。这里,假凸起32a虽然与导体图形2(引线部分221)重叠,但是没有连接,所以,假凸起32a与凸起31不同,没有被压扁,仍保持着初始的厚度。
另外,在器件孔23的内侧,也形成与半导体芯片3相互重合的电路基板2的重叠部212。重叠部212通过器件孔23的大致中央部分与各四边的大致中央附近连接。在与该重叠部212重叠的半导体芯片3的功能面30上的4个地方分别形成假凸起33b(衬垫部)。该假凸起33b也与半导体芯片3内部的不论哪个电路都没有电气连接。另外,假凸起33b不与导体图形22(引线部分221)连接,所以,与凸起31不同,不会被压扁,仍保持初始的厚度。
在这样构成的半导体器件1中,不使用焊锡凸起,所以,除了生产效率高外,如图2(a),(b)所示,依靠假凸起32(32a、32b)可以自动地在电路基板2与半导体芯片3之间确保与其厚度相当的间隙t1。因此,导体图形22与半导体芯片3的边缘之间不会发生短路。
而且,假凸起32的厚度在引线部分221与凸起31的焊接工序前后不发生变化,所以,间隙t1的尺寸由预先设定的假凸起32的初始厚度尺寸决定。另外,由于假凸起32与导体图形22重叠,所以,在导体图形22与半导体芯片3之间可以可靠地确保间隙t1。因此,半导体器件1的可靠性高。另外,由于假凸起32能够与连接用的凸起31同时形成,所以,半导体芯片3的成本不会提高。
如图3(a)示意的焊接工序前的纵剖面图所示的那样,在半导体芯片3的功能面30上,除电路上所需要的凸起31和为了确保间隙t1所需要的假凸起32外,还形成电路上不需要并且也不是用于确保同隙t1的独立的假凸起34、35。其中,独立的假凸起34位于器件孔23的形成区域;独立的假凸起35位于重叠部212的形成区域内。但是,由于不在这些地方形成导体图形22,所以,如图3(b)示意的接合工序后的纵剖面图所示的那样,不会与电路基板2一侧接触。但是,通过预先形成这些独立的假凸起34、35,例如当改变电路基板2上重叠部211、212的形成位置时,这些独立的假凸起34、35便可确保半导体芯片3与电路基板2之间具有指定的间隙t1。
本例的半导体器件1具有以下特征:
再回到图1,器件孔23处于由重叠部212分割为4个洞231、232、233、234的状态。因此,即使如导体图形22的跨接部222那样,是通过横跨器件孔23来形成的,该跨接部222只跨越一个洞232,利用重叠部212可以使它处于加固的状态。同样,导体图形22的跨接部223只跨越一个洞232,其前端一侧由重叠部212支持。所以,在与半导体芯片3的功能面30相对的位置上不仅可以自由地配线,而且在该处形成的导体图形的强度也大。同时,通过在器件孔23的内侧保留重叠部211、212,可以提高电路基板2的强度,所以,可以防止挠性电路基板2发生不必要的变形。
另外,由于在器件孔23的内周缘由重叠部211、212形成收口形状,所以,引线部分221可以面向图面向纵向和横向的任何一个方向突出。因此,例如,像引线221a那样,可以沿器件孔23的内周缘突出,于是,在靠近器件孔23的一边的中央附近的位置也可以形成向相互正交方向突出的引线部分221a、221b,如此等等,配线图形的设计自由度很大。因此,本例的半导体器件1的可靠性高,设计的自由度大,所以,具有广泛的用途。
此外,重叠部212形成为通过器件孔23的大致中央部分分割器件孔23,在与器件孔23的中央部分即与半导体芯片3的大致中央部分相当的部分,形成在重叠部212上的贯通孔230。因此,如以下说明的那样,具有在实装工序中生产效率高的优点。
下面,参照图3(a),(b)说明将半导体芯片3向电路基板2上实装的工序。
首先,如图3(a)所示,相对于电路基板2的器件孔23决定半导体芯片3的位置。在该状态下,使重叠部211与半导体芯片3相互重合。
在该状态下,对引线部分221施加超声波振动,将引线部分221与凸起31逐个连接。结果,便如图3(b)所示,引线部分221向下弯曲,同时凸起31成为压扁的状态。
与此相反,由于假凸起32与导体图形22不连接,所以,假凸起32在凸起31与引线部分221的接合工序前后厚度不变,仍维持初始的厚度。因此,在电路基板2与半导体芯片3之间可以确保与假凸起32的初始厚度相当的间隙t1。
然后,向器件孔23内填充模塑材料4。这里,由于器件孔23被分割为4个洞231、232、……。所以,从各个洞231、232、……注入模塑材料4。因此,模塑材料4的灌注平滑均匀。而且,在重叠部211、212中,在与器件孔23的中心部相当的区域,形成贯通孔230,当注入模塑材料4时,空气可以从贯通孔230排出,所以,模塑材料4的灌注非常平滑顺利。因此,实装工序的生产效率高。
在本例中,假凸起32与电路基板2的重叠部211中在该处形成的导体图形22重合,但是,当基底21的例性比较大并且不需要将导体图形22的厚度算在间隙t1的尺寸内时,也可以采用将假凸起32与重叠部211的基底21本身直接重叠的结构。第2实施例:
由于本实施例的半导体器件的基本结构与第1实施例的半导体装置相同,所以,对于具有共同的功能的部分标以相同的符号,并省略其详细说明。
图4(a)是在本例的半导体器件中,将半导体芯片装配到电路基板上之前的状态的示意纵剖面图,图4(b)是将半导体芯片装配到电路基板上之后的状态的示意纵剖面图。
在图4(a)中,在本例的半导体器件11中,和第1实施例的半导体器件一样,在半导体芯片3的功能面30上形成电路上所需要的凸起31(接合用电极)和电路上不需要的假凸起32(衬垫部)。在电路基板2一侧,形成器件孔23,导体图形22的引线部分221向其内侧突出。另外,在电路基板2上,有在将半导体芯片3相对于器件孔23确定好位置的状态下与半导体芯片3相重合的重叠部211,在该重叠部211上也形成导体图形22。
在本例中,在重叠部211上形成的导体图形22中,当将半导体芯片3相对于电路基板2定好位置时在与假凸起32重合的部分上形成从导体图形22突出的突起224(衬垫部)。该突起224是从假凸起32向电路基板2一侧转印的凸起。
因此,对引线部分221施加超声波振动,利用单点焊接法将引线部分221与凸起31进行连接时,如图4(b)所示,引线部分221向下弯曲,同时凸起31成为压扁状态。
与此相反,由于假凸起32与导体图形22(突起224)不连接,所以,假凸起32不变形,在引线部分221与凸起31的接合工序之后仍保持初始的厚度。同样,突起224也不变形,保持初始的厚度。于是,在电路基板2与半导体芯片3之间,可以确保尺寸与假凸起32的厚度加上突起224的厚度之和相当的间隙t2,所以,即使不进行成形加工,电路基板2与半导体芯片3的边缘之间也不会发生短路。而且,由于间隙t2的尺寸是由预先设定的假凸起32的厚度尺寸和突起224的厚度尺寸决定的,所以,没有必要将其尺寸设定到不需要的那么大。因此,即使在采用由单点焊接法进行连接的这一结构的半导体装置11中,也可以实现薄型化,并且可靠性高。
另外,由于假凸起32可以与焊接用的凸起31同时形成,所以,不会提高半导体芯片3的成本。
本例的半导体器件11的平面结构也和图1所示的第1实施例的半导体装置相同,所以,向器件孔23内填充模塑材料4时,可以从各个洞231、232……注入模塑材料4。而且,在注入模塑材料4时,可以从贯通孔230将空气排出。因此,注入的模塑材料4的灌注平滑均匀。
在本例中,导体图形22的突起224与半导体芯片3的假凸起32重叠,但是,当突起224足够厚时,也可以与涂了绝缘涂层的半导体芯片3的功能面30本身重叠。第3实施例:
由于本例的半导体器件的基本结构也和第1实施例的半导体器件相同,所以,对于具有共同的功能的部分标以相同的符号,并省略其详细说明。
图5(a)是在本例的半导体器件中将半导体芯片装配到电路基板上之前的状态的示意纵剖面图,图5(b)是将半导体芯片装配到电路基板上之后的状态的示意纵剖面图。
在图5(a)中,在本例的半导体器件12中,在电路基板一侧形成器件孔23,导体图形22的引线部分221向其内侧突出。该导体图形22是由镀金的导线构成。在本例中,在半导体芯片3上形成铝焊接区38,其中,只有铝焊接区38a(连接用电极)与引线部分221连接。该铝焊接区38a是电路上所需要的焊接区,铝焊接区38b与半导体芯片3的内部构成的任何电路都不进行电气连接,是电路上不需要的焊接区。这样,在本例中,由于不在半导体芯片3上形成凸起,所以,价格低廉。
在电路基板2上,有在将半导体芯片3相对于器件孔23定好位置的状态下与半导体芯片3重合的重叠部211,在该重叠部211上也形成导体图形22。在该导体图形22中,在与铝焊接区38b重叠的部分上形成比导体图形22的其他部分突出的突起225(衬垫部)。突起225是在利用腐蚀方法形成导体图形22时,对应该形成突起225的部分进行半腐蚀从而比其他部分厚的部分。并且使导体图形22位于半导体芯片3周围的部分变薄,使突起225也比该部分厚。
在这样构成的半导体器件12中,也对引线部分221施加超声波振动,利用单点焊接法将引线部分221与铝焊接区38a进行连接时,如图5(b)所示,引线部分221向下弯曲。但是,由于突起225不与半导体芯序3一侧连接,所以,突起225保持不变。于是,在电路基板2与半导体芯片3之间可以随保与突起225的初始厚度相当的间隙t3,所以,电路基板2与半导体芯片3的边缘之间不会发生短路。而且,由于突起225的厚度在引线部分221与铝焊接区38a的接合工序前后不变化,间隙t3的尺寸由初始设定的突起225的初始厚度决定,所以,可以不必将间隙t3的尺寸设定到不需要的那么大。因此,本例的半导体装置12可以实现薄型化,并且可靠性高。另外,由于突起225利用的是导体图形22的一部分,所以,不会提高电路基板2的成本。
另外,本例的半导体器件12的平面结构也与图1所示的第1实施例的半导体器件相同,所以,在向器件孔23内填充模塑材料4时,可以从各个洞231、232……注入模塑材料4。另外,在注入模塑材料4时,可从贯通孔230将空气排出。因此,模塑材料4的灌注平滑均匀。
在本例中,导体图形22的突起225与半导体芯片3的铝焊接区38b重叠,但是,只要是与半导体芯片3的电路绝缘的部分就可以,例如,也可以与涂了绝缘涂层的功能面30本身重叠。其他实施例:
除了上述实施例以外,也可以在电路基板上形成与半导体芯片重合的重叠部,只要在该重叠部或者与其重合的半导体芯片的面上形成在导体图形与凸起的接合工序前后厚度不变化的衬垫部就可以,例如,可以是构成电路基板的基底本身的突起或者从半导体芯片的功能面本身突出的绝缘性突起。
另外,不仅是使用单点焊接法,使用同轴焊接法也可以获得同样的效果。这里,使用同轴焊接法时,同轴焊接用的连接工具的下端结构示意地示于图6,使连接工具T的下面不是平面,为了避开重叠部211、212和导体图形的跨接部222、223,可以使用形成凹部T1的连接工具T。
如上所述,在本发明的半导体器件中,在电路基板一侧形成与装配到器件孔内的半导体芯片重合的重叠部,在该重叠部与半导体芯片之间,借助于在半导体芯片一侧形成的假凸起或者在重叠部的导体图形上形成的突起等衬垫部,处于确保指定的间隙的状态,因此,按照本发明,使用单点焊接法等方法时,即使不对电路基板的引线部分进行成形加工,由于可以在重叠部与半导体芯片之间确保指定的间隙,所以,既可以使半导体器件实现薄型化,又可以防止在半导体边缘发生短路,可靠性很高。而且,由于可以省去成形加工,所以,可以提高生产效率。另外,由于在重叠部形或导体图形,从而可以在与半导体芯片的功能面相对的区域进行布线,所以,图形设计的自由度大,半导体芯片的通用性也很高。
在半导体芯片一侧形成假凸起、在电路基板的重叠部形成导体图形的突起时,在电路基板与半导体芯片之可也可以很容易地形成宽度与半导体芯片一侧形成的假凸起和突起的厚度之和相当的间隙。
在器件孔的四角部分有重叠部分时,即使是芯片尺寸大的半导体芯片,也可以确保均匀的间隙。另外,在器件孔的各边部分形成重叠部时,即使是芯片尺寸大的半导体芯片,也可以确保更均匀的间隙。
器件孔被重叠部分割为多个洞时,可以从各个洞注入模塑材料,所以,模塑材料的灌注平滑均匀,而且,即使在导体图形上设置跨越分割的洞的跨接部,由于该跨接部由重叠部所加固,所以,既可以保持很高的可靠性,又可以提高电路图形的设计自由度。
在通过器件孔的大致中心位置的重叠部形成贯通孔时,由于在注入模塑材料时可以从贯通孔将空气排出,所以,模塑材料的灌注平滑均匀。
Claims (11)
1.一种半导体器件,具有在绝缘性的基底上形成导体图形的电路基板和装配到该电路基板的器件孔内的半导体芯片,上述导体图形中突出到上述器件孔内的引线部分与上述半导体芯片的凸起相连接,该半导体器件的特征在于:
上述电路基板具有与上述半导体芯片重合的重叠部,在该重叠部和与其重叠的上述半导体芯片的面上至少在其中的一侧形成将上述引线部分与上述凸起连接的接合工序前后厚度不变化的衬垫部,该衬垫部位于上述电路基板与上述半导体芯片之间,确保该处具有指定的间隙;
一部分接合的引线框位于器件孔中,并且在接合期间直接对引线框加压;以及
在弯曲的同时形成引线框。
2.按权利要求1所述的半导体器件的特征在于:上述衬垫部是在与上述重叠部重叠的上述半导体芯片的面上与上述导体图形不连接,并且位于上述电路基板与上述半导体芯片之间以确保该处具有指定的间隙的假凸起。
3.按权利要求2所述的半导体器件的特征在于:在上述重叠部,上述导体图形与上述假凸起重叠。
4.按权利要求1所述的半导体器件的特征在于:上述衬垫部是在上述重叠部一侧、与上述连接用电极不连接并且位于上述电路基板与上述半导体芯片之间以确保该处具有指定的间隙的上述导体图形的突起。
5.按权利要求4所述的半导体器件的特征在于:上述半导体芯片具有作为上述连接用电极的凸起,在与上述突起重叠的位置,具有与其不连接的假凸起。
6.按权利要求4所述的半导体器件的特征在于:上述半导体芯片具有作为上述连接用电极的焊盘,在与上述突起重叠的位置,具有与其不连接的假焊接区。
7.按权利要求1~6的任一项所述的半导体器件的特征在于:上述器件孔具有大致呈四角形的轮廓,在其四角部分有上述重叠部。
8.按权利要求7所述的半导体器件的特征在于:上述重叠部也位于上述器件孔的各边部分。
9.按权利要求1-6或8的任一项所述的半导体器件的特征在于:上述重叠部形成到上述器件孔的内侧,将上述器件孔分割为多个洞。
10.按权利要求9所述的半导体器件的特征在于:上述重叠部通过上述器件孔的大致中心位置,将上述器件孔分割为多个洞,在与该大致中心位置对应的部分,在上述重叠部形成贯通孔。
11.按权利要求10所述的半导体器件的特征在于:上述导体图形具有横跨上述洞的跨接部。
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JP82207/93 | 1993-04-08 | ||
JP08220793A JP3269171B2 (ja) | 1993-04-08 | 1993-04-08 | 半導体装置およびそれを有した時計 |
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CN1104415A CN1104415A (zh) | 1995-06-28 |
CN1047470C true CN1047470C (zh) | 1999-12-15 |
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EP (1) | EP0645806B1 (zh) |
JP (1) | JP3269171B2 (zh) |
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CN (1) | CN1047470C (zh) |
DE (1) | DE69433543T2 (zh) |
HK (1) | HK1014612A1 (zh) |
TW (1) | TW301793B (zh) |
WO (1) | WO1994024698A1 (zh) |
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- 1994-04-04 US US08/351,383 patent/US5563445A/en not_active Expired - Lifetime
- 1994-04-04 EP EP94910595A patent/EP0645806B1/en not_active Expired - Lifetime
- 1994-04-04 CN CN94190177A patent/CN1047470C/zh not_active Expired - Lifetime
- 1994-04-04 KR KR1019940704091A patent/KR100296834B1/ko not_active IP Right Cessation
- 1994-04-04 DE DE69433543T patent/DE69433543T2/de not_active Expired - Lifetime
- 1994-04-04 WO PCT/JP1994/000551 patent/WO1994024698A1/ja active IP Right Grant
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EP0645806A1 (en) | 1995-03-29 |
JPH06295939A (ja) | 1994-10-21 |
HK1014612A1 (en) | 1999-09-30 |
KR100296834B1 (ko) | 2001-10-24 |
WO1994024698A1 (en) | 1994-10-27 |
EP0645806B1 (en) | 2004-02-11 |
DE69433543T2 (de) | 2004-12-23 |
US5563445A (en) | 1996-10-08 |
KR950701769A (ko) | 1995-04-28 |
TW301793B (zh) | 1997-04-01 |
DE69433543D1 (de) | 2004-03-18 |
JP3269171B2 (ja) | 2002-03-25 |
EP0645806A4 (en) | 1995-10-11 |
CN1104415A (zh) | 1995-06-28 |
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