CN104716089A - Method for conducting non-electric metal deposition on metal layer and application - Google Patents
Method for conducting non-electric metal deposition on metal layer and application Download PDFInfo
- Publication number
- CN104716089A CN104716089A CN201510071406.3A CN201510071406A CN104716089A CN 104716089 A CN104716089 A CN 104716089A CN 201510071406 A CN201510071406 A CN 201510071406A CN 104716089 A CN104716089 A CN 104716089A
- Authority
- CN
- China
- Prior art keywords
- metal
- solution
- wafer
- palladium
- complex
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Abstract
The invention discloses a method for conducting non-electric metal deposition on a metal layer in the integrated circuit wafer manufacturing process and application. The method includes the steps that the metal layer is activated through an activation solution, and oxide of the metal layer is removed and/or the metal surface is etched through the solution; an alkali composition of a non-ammonia type nitrogen complex containing sensitizing metal makes contact with an activation wafer so as to sensitize the metal layer; the catalyzed wafer is deposited through non-electric metal. The metal is selected from Ti, W, Ti/W alloy and/or aluminum and aluminum alloy. The thickness of a shielding layer during metallization treatment can not affected; the metallized wafer does not need to be further treated after being immersed in a complex solution, and the situation that defected wafers are generated due to deposition in the regions not needed by a device can be avoided; the process is simple, condition controllability is high, and high-quality wafers can be manufactured and are suitable for large-scale industrial application.
Description
Technical field
The present invention relates to a kind of in manufacture integrated circuit (IC) wafer, carry out electroless metal deposition on the metal layer method and application.
Background technology
Making integrated circuit on silicon will use series of steps to make finished wafer.In part preparation method, wafer is deposited layer of silicon dioxide (SiO
2), and this SiO
2or suitable medium is etched, to form passage or circuit path on wafer, this passage is at SiO substantially
2on layer formed and extending to the path of silicon layer.Then circuit path is filled with conducting metal, with the circuit formed.Known, integrated circuit is produced and is strict and difficulty, because processing method must be highly reliable and product wafer is zero-fault substantially.
Existing wafer metallization scheme is previously coated with made of Al-Cu alloy TiW or other suitable barrier layer/adhesive layer using sputtering or evaporation, with filling vias and completing circuit in path.This technology produce the circuit that is less than 2-2.5 micron live width and the aspect ratio of fully filling Gao Yukuan be greater than 1 passage in there is serious shortcoming.In high aspect ratio situation, the seam produced by bad filling and space not only produce the discontinuity of electricity and high aisle resistance, and in subsequent process steps, cause carrying secretly of impurity, and this often can cause integrity problem again.Metallization scheme of the present invention is attempted to eliminate these problems and is used chemical vapour deposition (CVD) or sputtering Al-Cu as electric circuit metal, but the deposition of metal such as aluminium relates to many difficulties, and also needs are very careful.Also studied the application of directed sputtering, but controlled very difficult especially under small size and high aspect ratio situation.
Consider from electrical property, the metallization of wafer requires to use various metal such as nickel or preferably use copper, but these metals and particularly copper have many shortcomings, such as, tend to be diffused in silicon by metal barrier layer or adhesive layer.Etching copper is also very difficult to produce the meticulous line circuit figure required, and runs into for the CVD process of deposited copper the many complicated factors relating to selectivity and treatment temperature.Therefore, adopt low temperature wet processing technique such as electroless deposition of copper to be very useful, the method less expensive uses with being easy to.
The method of electronic device is prepared in U.S. Patent No. 5 with electroless deposition of copper, 308,796 (Feldman etc.) and being write by common inventor Cecilia Mak, at MRSBULLETIN/August1994, Vol.XIX, provide in the relevant article that what No.8,55-62 page was delivered is entitled as " electroless deposition of copper on metal and metal silicide " (Electroless copper deposition onmetals and metal silicides).Patent and article all draw this as a reference.Usually that the circuitous pattern that depicts of the silicon dioxide on etched silicon wafer first deposits skim catalysis material, particularly palladium.The palladium on adjacent silicon surface is changed into Pd through annealing
2si, and at SiO
2on Pd do not react.Then remove unreacted Pd with selective etch, only leave Pd in the bottom of passage
2si, this material covers silicon face.Electroless deposition of copper is subsequently only at catalysis Pd
2occur in Si region.Unfortunately, this method still has shortcoming, because whole wafer must coated with palladium layers, then this palladium layers must be stayed containing Pd by optionally etching away
2the required circuit region of Si.This is a difficult job, and except except required region, on wafer, remaining palladium can cause harmful sedimentary deposit and cause defective wafer by the space in passage and other deposition problems.Then etching solution must through liquid waste processing, and with Recover palladium, this brings again inevitable treatment and disposal problem.
In the above-mentioned article of Mak, the another kind provided becomes graphic scheme to be the selectivity CVD of thin layer tungsten film relying on channel bottom.The tungsten hexafluoride of deposition is reduced into tungsten metal by the silicon of the exposure of channel bottom, and this metallic film is used as crystal nucleation layer and the diffusion-barrier coating of follow-up electroless deposition of copper.But notice, the method, during seeding step, has the possibility forming defect like channel below tungsten layer, and the tungsten film possibility hole formed by Si reduction completely too much can not as diffusion-barrier coating.
At present, preferred technology of preparing forms tungsten alloy film such as TiW film by CVD in channel bottom, and make channel metal by CVD technology.One method be adopt CVD technology noble metal normally gold to apply TiW; this layer gold is as the oxidation protection of further interconnect metallization and low resistance contact; but; this technology is still very dissatisfied, therefore expects more effective technology to make to have the channel metal of tungsten alloy or other metal barrier layer.
Electroless deposition is by electronation at catalytic surface chemical deposition metal or metal mixture, and the composition of electroless metal deposition and method are to draw this U.S. Patent No. 3011920 as a reference open.If be inertia for the substrate of plated metal--it is non-catalytic for namely depositing metal, then common deposition process comprises preliminary treatment to promote clean and bonding, substrate catalysis is made with suitable deposited catalyst process, to make surface in catalytic to accelerate the ensuing electroless metal deposition of this technology before deposition.
For in electroless deposition methods commercial catalyst comprise by the Bivalent Tin of molar excess substantially and the product of palladium ion in hydrochloric acid solution.Product is considered to tin palladium colloid.Can think, the tetravalent tin of oxidation is combined with palladium ion with unreacted Bivalent Tin, formation protectiveness, may be the palladium of polymerization or the complex of palladium-ashbury metal, and unreacted divalent tin ion is as antioxidant.
The U.S. Patent No. 3904792 of drawing this reference discloses the improvement to colloidal tin palladium chtalyst.In that patent, provide a kind of catalyst, than acid low disclosed in above-mentioned U.S. Patent No. 3011920, wherein a part of hydrochloric acid soluble metal halogenation ackd salt replaces, obtain having pH close to 3.5 more stable catalyst.
In the art, the known catalyst formed by the product by Bivalent Tin and precious metal ion, processing sequence generally comprises the catalysis of substrate, logical common acid such as fluoboric acid or perchloric acid to the acceleration of Catalytic Layer, and the step such as electroless metal deposition.Known accelerating step is for activating palladium catalyst, the initiation of enhanced deposition reaction, and reduction all covers required sedimentation time to for deposition region.
But unfortunately, general electroless deposition methods can not be used to depositing silicon wafer, and because they lack selectivity, so that this catalyst is by whole for catalysis wafer, unless removed from unwanted region by catalyst, otherwise unwanted deposition will produce defective part.
For simplicity, description below will for silicon wafer integrated circuit and tungsten-bast alloy, particularly TiW alloy is used as the metallization barrier layer for electroless deposition, but people familiar with the art should understand and the present invention be directed to sensitization for carrying out other metal and the metal alloy of electroless metal deposition thereon, these metals can be used for manufacturing the circuit of integrated circuit or other type or require metallized product.Such as, aluminium is commonly used as conductor layer, and this layer is metallized to provide finished product.The controlled unstability chip connection pads that chip connection pads is such as called C4 pad is made in a kind of application of aluminium.C4 pad is the micro-cave supporting C4 solder ball chip being connected to substrate such as film-substrate.Draw this for referencial use in U.S. Patent No. 5243140 give typical C4 pad.
Summary of the invention
Consider problem and the shortcoming of prior art, the object of this invention is to provide a kind of method of catalytic metal and metal alloy, for carrying out electroless metal deposition thereon.
A further object of the present invention is to provide a kind of method for metallising for electroless metal deposition such as copper on metal and metal alloy, to prepare integrated circuit (IC) wafer.
For realizing aforementioned invention object, the technical solution used in the present invention comprises:
Manufacturing a method of carrying out electroless metal deposition in integrated circuit (IC) wafer on the metal layer, the method comprises:
With activated solution activated metal layer, this solution removing metal layer thing and/or etching metal surface;
Contact with activated wafer with the alkaline compositions of the non-ammonia type nitrogen complex containing sensitization metal, with sensitization metal level; With
The wafer of electroless metal deposition catalysis.
Further, described metal is selected from Ti, W, Ti/W alloy and/or Al and Alalloy.
Further, described activated solution is acid or alkaline and comprises a kind of complexant, to form complex with the metal that can be removed during activation step.
As one embodiment of the present invention, described metal is Ti, W, Ti/W alloy, and described activated solution is alkaline.
Further, described activated solution also includes chelating agent if EDTA is with chelated mineral impurity, and described metal impurities comprise iron, cobalt, nickel and copper.Described activated solution contains fluorine ion as complexant.Described sensitization metal comprises palladium, and the pH of described sensitized solution controls at about 9-13, and be preferably 11-12, described complex is palladium-ethylene diamine complex, and wherein palladium is to the mol ratio of ethylenediamine about 3: 1-5: 1
As another embodiment of the present invention, when described metal level is aluminum or aluminum alloy, activated solution is in acid.Be preferably the acidic etchant containing HF and/or HCl.
Further, described sensitization composition is non-ammonia type palladium nitrogen complex, and the pH of described sensitized solution is about 10.5-11, and described complex is palladium-ethylene diamine complex.
A kind of integrated circuit (IC) wafer manufactured by said method.
Compared with prior art, advantage of the present invention comprises: during metalized of the present invention, the thickness of barrier layer can not be influenced; After immersion palladium complex solution, metallized wafer does not need further process, can not cause defective wafer owing to there is deposition in the unwanted region of device; Technique of the present invention is simple, and condition controllability is high, can prepare high-quality wafer, is applicable to large-scale industrial application.
Embodiment
In view of deficiency of the prior art, inventor, through studying for a long period of time and putting into practice in a large number, is proposed technical scheme of the present invention.To be further explained this technical scheme, its implementation process and principle etc. as follows.
According to the inventive method, the silicon wafer be preferably metallized comprises the silicon substrate with silicon dioxide or other dielectric layer.Passage in silicon dioxide layer or other path diffuse metal layer such as tungsten-bast alloy adopts such as CVD method to provide as TiW, and this layer must metallize, and passage is filled the circuit provided required by integrated circuit (IC) wafer.
Usually, deposited on silicon wafers has the silicon dioxide layer of thick about 1-5 μm, and this layer through being etched into the form of passage or other path, and extends to silicon layer from silicon dioxide layer, with provide requirement circuitous pattern.Metal level typically tungsten-bast alloy as diffusion layer, barrier layer and/or adhesive layer, and by the deposition techniques of such as chemical vapour deposition (CVD) on the silicon layer of circuit pathways (passage) bottom.The general about 200-1000 dust of thickness of tungsten-bast alloy, but very wide change can be had.The metal or alloy example that can be used as barrier layer/adhesive layer comprises TiW, W, Cr, Al and Ta.
Key character of the present invention is that the thickness of barrier layer during metalized can not be influenced, such as thickness reduces, otherwise the barrier characteristics of metal will be reduced so that cause such as follow-up electroless metal deposition spread in silicon by barrier layer and cause defective wafer.
Initial step of the present invention is according to the metal for deposition, activated metal barrier layer if desired.No matter be what metal barrier layer, activation is particularly preferred, and this step alloy such as TiW is necessary, and because it forms oxide or other film from the teeth outwards, be perhaps unwanted to other alloy, this depends on their physics and/or chemical property.If need activation, activated solution is roughly a kind of solution that can remove oxide layer and/or dissolving (etching) metal, cleans and oxide-free surface to be formed.Solution can be acid or alkaline, to depositing SiO
2the preferred alkaline solution of the silicon wafer with Ti/W barrier layer, to aluminium barrier layer wafer preferred acidic solution.Preferred alkaline activation solution contains the fluorine ion provided by the solution of salt such as 0.5-3% (weight) or higher NaF, and other activator comprises the difluoride of ammonium and sodium.Acidic etchant can contain such as HF or HBF
4.Preferred use chelating such as EDTA, it measures about 1g/l or higher.Other chelating can be selected from material such as lactic acid widely, and malic acid contains the material of anion such as acetate, citrate, ethanol acid group, pyrophosphate etc. with those.Activated solution is generally in temperatures as high 80 DEG C or more relative superiority or inferiority use, and be preferably 25-50 DEG C for aluminium, soak time is 10-60 second or longer.
Best not rinsing wafer after activation step, and the wafer of activation is directly proceeded to palladium sensitization displacement complex solution from activation step.
Sensitized solution is commonly referred to as substitutional solution, and can contain any catalytic metal such as palladium and nickel, and preferred palladium.Think that catalytic metal such as palladium is the form in complex in theory, and preferably complex is nitrogen complex (non-amine complex) such as particularly preferably ethylenediamine palladium complex, as at " noble metal Science and Technology " (Precious Metals Scienceand Technology), Benner, Suzuki, describe in Meyuro and Tanaka, Publ.International PreciousInst 1991, this publication arranges this with for referencial use.Coordination chemistry formula is PdCl
2(C
2h
8n
2), and by mixing K
2pdCl
4with ethylenediamine (ED) and heated solution prepare.Although preferably keep lower free ED in sensitized solution, but usually about 3: 1 are greater than to the mol ratio of preferred ED and the Pd of sensitized solution, such as about 5: 1, and can be higher, in sensitized solution, the amount of catalytic metal is generally about 0.1-10% (weight), preferred 0.5-4% (weight).
Palladium sensitized solution also preferably contains complexing agent as the fluorine ion of NaF form, the metal ion removed from metal/oxide layers with complexing.Consumption can change in the wide region of about 1-5%, preferably generally uses 2-4% (weight) NaF.Also preferably contain complexing agent in solution as EDTA and chelating agent, such as those are above-mentioned for the chelating agent in etching solution, and its amount is about 1g/l or higher, with chelating foreign ion such as iron, nickel and copper.
When using preferred ED/Pd complex on Ti/W alloy barrier layer, assuming that there is following reaction:
Key character of the present invention is the scope that the pH value of immersion deposition solution controls especially at 9-13, and preferable ph is 11-12, logical common acid such as rare HCl or alkali such as NaOH adjust ph to the level required.To sensitization aluminium, pH value is 10.5-11 is particularly preferred.Find, the pH value of sensitized solution is important to control displacement reaction, and the value outside above-mentioned scope, then can not provide the reliability needed for IC manufacturing.
If necessary, the aforementioned metallization wafer activated contacts with above-mentioned palladium chtalyst complex sensitizer solution with catalytic metal barrier layer.Usually, the serviceability temperature of palladium complex solution is about 30-80 DEG C to Ti/W alloy, is 25-60 DEG C to aluminium, and time of contact is 18-60 second, preferred 10-30 second.
An important benefits of the present invention is, after immersion palladium complex solution, metallized wafer does not need further process, and in first technology, usually with reductant solution, palladium ion is reduced to palladium metal.Rinsing be ready for use on electroless metal deposition in addition after wafer is catalyzed.Known, electroless metal deposition method typically adopts containing PdCl
2-SnCl
2the catalyst solution of-HCl, due to the reduction of tin, this catalyst is providing Metal Palladium for deposition surface.These solution can not use in the present invention, and because their limited opereating specifications can cause production integrity problem, these solution bath have example in United States Patent (USP) 3011920.Catalyzing and displacement complex solution such as ED-Pd complex is used to provide high selectivity to sensitization metal level, and can not to electronic device remainder such as to the significant sensitization of silicon dioxide, and provide large opereating specification, its dip time and temperature can have a greater change, and can not cause defective wafer owing to there is deposition in the unwanted region of device.
Industrially know without electrolytic copper bath, and any bath without electrolytic copper all can be used in the inventive method.Although be preferred metal without electrolytic copper, other also can use without electrobath such as electroless nickel, Ni-Co, Co etc.For simplicity, following description will be bathed for electroless deposition of copper.
In particular, contain without electrolytic copper bath: 1) copper ion source, 2) reducing agent such as formaldehyde, 3) acid or hydroxide conditioning agent, to provide required pH and 4) be enough to the metallic ion coordination agent that prevents metal ion from precipitating in the solution.In United States Patent (USP) 4171225, have description for the composition deposited without electrolytic copper, this patent draws that this is for referencial use.
According to without electrolytic copper or the metal layer carrying out Deposit die with electroless nickel, its sedimentary condition can change according to the sedimentation type of deposition rate and requirement.To with acid bath without electrolytic copper, the general temperature used is about 45-70 DEG C, and the time, up to 60 minutes, is generally 30-40 minute.To electroless nickel bath, no matter alkaline or acid, conventional dip time is about 15-60 minute, and preferred 10-25 minute, temperature is about 60-85 DEG C.
embodiment 1
Diameter is 6 inches and containing the silicon wafer of many chips separated, and it has silica deposition layer, and this sedimentary deposit is etched the circuitous pattern that formed and require as passage.Wafer CVD method metallizes, and is the TiW metal layer of about 500 dusts at the bottom deposit thickness of etched passage.The TiW layer of wafer is activated through immersing in the 10g/lNaF solution of 80 DEG C 40 seconds.The wafer of activation is transferred directly in the palladium catalyst sensitizer solution containing 4g/l palladium without rinsing, wherein palladium exists with the form of ED/ palladium complex, and the mol ratio of ED/Pd is 4: 1, containing NaF 22g/l and EDTA 1g/l.The pH of solution remains on 10.5-11, and wafer to immerse in 80 DEG C of solution 35 seconds.After dipping, this wafer is thoroughly rinsing in deionized water, with the alkaline electroless nickel bath plated metal of commercialization.Wafer to immerse in 80 DEG C of baths 40 minutes with plated metal, and generates and have that metal and metlbond deposit and the acceptable wafer product depositing metal of commercialization checked by adhesive band indentation.The form of deposition and the plesiomorphism of the deposition obtained with usual deposition process.
Should be appreciated that above-described embodiment is only and technical conceive of the present invention and feature are described, its object is to person skilled in the art can be understood content of the present invention and implement according to this, can not limit the scope of the invention with this.All equivalences done according to Spirit Essence of the present invention change or modify, and all should be encompassed within protection scope of the present invention.
Claims (10)
1. manufacturing a method of carrying out electroless metal deposition in integrated circuit (IC) wafer on the metal layer, it is characterized in that the method comprises:
With activated solution activated metal layer, this solution removing metal layer thing and/or etching metal surface;
Contact with activated wafer with the alkaline compositions of the non-ammonia type nitrogen complex containing sensitization metal, with sensitization metal level; With
The wafer of electroless metal deposition catalysis.
2. the method for electroless metal deposition according to claim 1, is characterized in that described metal is selected from Ti, W, Ti/W alloy and/or Al and Alalloy.
3. the method for electroless metal deposition according to claim 1, is characterized in that described activated solution is acid or alkaline and comprises a kind of complexant, to form complex with the metal that can be removed during activation step.
4. the method for electroless metal deposition according to claim 1 and 2, it is characterized in that described metal is Ti, W, Ti/W alloy, described activated solution is alkaline.
5. the method for electroless metal deposition according to claim 4, it is characterized in that described activated solution also includes chelating agent with chelated mineral impurity, described metal impurities comprise iron, cobalt, nickel and copper.
6. the method for electroless metal deposition according to claim 4, is characterized in that described activated solution contains fluorine ion as complexant.
7. the method for electroless metal deposition according to claim 4, it is characterized in that described sensitization metal comprises palladium, the pH value of described sensitized solution is about 11-12; Described complex is palladium-ethylene diamine complex, and wherein palladium is to the mol ratio of ethylenediamine about 3: 1-5: 1.
8. the method for electroless metal deposition according to claim 1 and 2, is characterized in that described metal level is Al and Alalloy, and described activated solution is in acid.
9. the method for electroless metal deposition according to claim 8, it is characterized in that described sensitization composition is non-ammonia type palladium nitrogen complex, the pH of described sensitized solution is about 10.5-11, and described complex is palladium-ethylene diamine complex.
10. the integrated circuit (IC) wafer of the method manufacture any one of claim 1,4 or 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510071406.3A CN104716089A (en) | 2015-02-11 | 2015-02-11 | Method for conducting non-electric metal deposition on metal layer and application |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510071406.3A CN104716089A (en) | 2015-02-11 | 2015-02-11 | Method for conducting non-electric metal deposition on metal layer and application |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104716089A true CN104716089A (en) | 2015-06-17 |
Family
ID=53415281
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510071406.3A Pending CN104716089A (en) | 2015-02-11 | 2015-02-11 | Method for conducting non-electric metal deposition on metal layer and application |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104716089A (en) |
-
2015
- 2015-02-11 CN CN201510071406.3A patent/CN104716089A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6261637B1 (en) | Use of palladium immersion deposition to selectively initiate electroless plating on Ti and W alloys for wafer fabrication | |
| US5169680A (en) | Electroless deposition for IC fabrication | |
| JP4055319B2 (en) | Manufacturing method of semiconductor device | |
| JP3332668B2 (en) | Electroless plating bath used for forming wiring of semiconductor device and method for forming wiring of semiconductor device | |
| CN100408202C (en) | Electroless plating solution and process | |
| US6794288B1 (en) | Method for electroless deposition of phosphorus-containing metal films onto copper with palladium-free activation | |
| TWI419995B (en) | Method for surface treatment of aluminum or aluminum alloy | |
| JP2008503093A (en) | Metal internal wiring capping in integrated circuit electronics. | |
| JP2017508076A (en) | Pretreatment method for electroless plating | |
| JP5982092B2 (en) | Activation solution for electroless plating of dielectric layers | |
| KR100807948B1 (en) | Method of preparing low resistance metal pattern, patterned metal wire structure, and display devices using the same | |
| WO2014044435A1 (en) | Manufacture of coated copper pillars | |
| JP2004019003A (en) | Printed circuit board and plating method thereon | |
| US20160108254A1 (en) | Zinc immersion coating solutions, double-zincate method, method of forming a metal plating film, and semiconductor device | |
| CN104716089A (en) | Method for conducting non-electric metal deposition on metal layer and application | |
| JP2004200273A (en) | Process for fabricating semiconductor device | |
| JP2000038682A (en) | Nickel plating method and semiconductor device | |
| KR100619345B1 (en) | Method for plating on printed circuit board for semi-conductor package and printed circuit board produced therefrom | |
| CN116324032A (en) | Electroless nickel deposition on copper without palladium activation | |
| JP4647159B2 (en) | Formation method of electroless plating film | |
| CN105051254A (en) | Method for activating a copper surface for electroless plating | |
| JP2003179057A (en) | Semiconductor device and method of manufacturing the same | |
| JP4343366B2 (en) | Copper deposition on substrate active surface | |
| KR101096812B1 (en) | Ni-Co-B three-element alloys electroless plating solution, electroless plating method using the same and Ni-Co-B three-element alloys coating layer prepared by the same | |
| JP2007141936A (en) | Method of manufacturing printed wiring board having high-density copper pattern |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150617 |