CN104575937A - Chip electronic component and manufacturing method thereof - Google Patents
Chip electronic component and manufacturing method thereof Download PDFInfo
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- CN104575937A CN104575937A CN201410566473.8A CN201410566473A CN104575937A CN 104575937 A CN104575937 A CN 104575937A CN 201410566473 A CN201410566473 A CN 201410566473A CN 104575937 A CN104575937 A CN 104575937A
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- insulating film
- conductive pattern
- oxide insulating
- pattern portion
- chip electronic
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- 230000000712 assembly Effects 0.000 claims 16
- 238000000429 assembly Methods 0.000 claims 16
- 230000007547 defect Effects 0.000 abstract description 19
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 13
- 229910000859 α-Fe Inorganic materials 0.000 description 12
- 238000010586 diagram Methods 0.000 description 10
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- 230000006866 deterioration Effects 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 4
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F17/00—Fixed inductances of the signal type
- H01F17/0006—Printed inductances
- H01F17/0013—Printed inductances with stacked layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01F—MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H01F27/00—Details of transformers or inductances, in general
- H01F27/28—Coils; Windings; Conductive connections
- H01F27/2866—Combination of wires and sheets
Abstract
A chip electronic component and a manufacturing method thereof are provided. The chip electronic component may include: a magnetic body having a coil conductive pattern part embedded therein; and an oxide insulating film formed on a surface of the coil conductive pattern part. Even in the case that the insulating film is formed to be thinner than an insulating film, it may prevent the coil conductive pattern part from being exposed, whereby a magnetic material and the coil conductive pattern part may not contact each other. Therefore, a waveform defect may be prevented at a high frequency.
Description
The rights and interests of the foreign priority of the 10-2014-0090841 korean patent application that this application claims the 10-2013-0126137 korean patent application submitted in Korean Intellectual Property Office on October 22nd, 2013 and submit on July 18th, 2014 in Korean Intellectual Property Office, the disclosure of described patent application is contained in this by reference.
Technical field
The disclosure relates to a kind of chip electronic assembly and a kind of method manufacturing this chip electronic assembly.
Background technology
Inductor as chip electronic assembly forms electronic circuit with resistor to remove the representative passive component of noise together with capacitor.
By forming coil conductive pattern portion by plating technic and the magnetic material sheets being that stacking, compacting and sclerosis are formed by the mixture of Magnaglo and resin manufactures film inductor.
Here, in order to prevent the contact between coil conductive pattern portion and magnetic material, the surface in coil conductive pattern portion forms dielectric film.
Summary of the invention
Exemplary embodiment can provide and comprise than thin according to the dielectric film of prior art and can effectively prevent and the chip electronic assembly of the dielectric film of the contact of magnetic material and manufacture method thereof.
According to exemplary embodiment, can provide the chip electronic assembly of the oxide insulating film had on the surface being formed in coil conductive pattern portion, wherein, oxide insulating film is formed by the metal oxide comprising at least one metal forming coil conductive pattern portion.
Accompanying drawing explanation
By the detailed description of carrying out below in conjunction with accompanying drawing, above and other aspects, features and advantages of the present disclosure more clearly will be understood, in the accompanying drawings:
Fig. 1 is the perspective illustration with the chip electronic assembly in coil conductive pattern portion according to exemplary embodiment;
Fig. 2 is the cutaway view intercepted along the line I-I' of Fig. 1;
Fig. 3 is the enlarged diagram of the example of the part A of Fig. 2;
Fig. 4 is the cutaway view of chip electronic assembly on length-thickness (L-T) direction according to exemplary embodiment;
Fig. 5 is the enlarged diagram of the example of the part B of Fig. 4;
Fig. 6 is the enlarged diagram of the example of the part C of Fig. 5;
Fig. 7 is the enlarged diagram of the example of the part A of Fig. 2;
Fig. 8 is the enlarged diagram of the example of the part B of Fig. 4;
Fig. 9 is magnified sweep electron microscope (SEM) photo of the part according to the coil conductive pattern portion its in the chip electronic assembly of exemplary embodiment being formed with dielectric film; And
Figure 10 is the flow chart of the method for the manufacture chip electronic assembly illustrated according to exemplary embodiment.
Embodiment
Exemplary embodiment is described in detail now with reference to accompanying drawing.
But the disclosure can illustrate in many different forms and should not be construed as limited to the specific embodiment of illustrating here.On the contrary, these embodiments are provided and make the disclosure to be thorough and complete, and will pass on the scope of the present disclosure fully to those skilled in the art.
In the accompanying drawings, for the sake of clarity, the shape and size of element can be exaggerated, and identical Reference numeral will be used to indicate same or analogous element all the time.
Below, by describing the chip electronic assembly according to exemplary embodiment, particularly, film inductor will be described.But, the present invention is not limited thereto.
Fig. 1 is the perspective illustration with the chip electronic assembly in coil conductive pattern portion according to exemplary embodiment; Fig. 2 is the cutaway view intercepted along the line I-I' of Fig. 1.
See figures.1.and.2, as the example of chip electronic assembly, disclose the film inductor 100 used in the power line of power circuit.
The outer surface that can comprise magnetic body 50 according to the film inductor 100 of exemplary embodiment, embed the coil conductive pattern portion 42 and 44 in magnetic body 50 and be formed in magnetic body 50 is connected to the external electrode 80 in coil conductive pattern portion 42 and 44.
Magnetic body 50 can form the outward appearance of film inductor 100 and can be formed by any material showing magnetic.Such as, magnetic body 50 is formed by filling ferrite or Metal Substrate soft magnetic material.
Ferrite can comprise the ferrite known in the art of such as Mn-Zn based ferrite, Ni-Zn based ferrite, Ni-Zn-Cu based ferrite, Mn-Mg based ferrite, Ba based ferrite, Li based ferrite etc.
Metal Substrate soft magnetic material can be the alloy comprising at least one selected from the group be made up of Fe, Si, Cr, Al and Ni.Such as, Metal Substrate soft magnetic material can comprise Fe-Si-B-Cr base amorphous metal particle, but is not limited thereto.
Metal Substrate soft magnetic material can have the particle size of about 0.1 μm to about 30 μm, and dispersibles in the polymer of such as epoxy resin, polyimides etc.
Magnetic body 50 can have hexahedral shape.In order to clearly limit exemplary embodiment, hexahedral direction will be defined.L, W and T shown in Figure 1 be indicating length direction, Width and thickness direction respectively.
The insulated substrate 23 be formed in magnetic body 50 can be such as polypropylene glycol (PPG) substrate, ferrite substrate, Metal Substrate soft magnetism substrate etc.
Insulated substrate 23 can have the through hole be formed in its core, and wherein, this hole can with the same material of such as ferrite, Metal Substrate soft magnetic material etc. to form core 55.Inductance L can be increased with the core 55 of same material.
Insulated substrate 23 can have the coil conductive pattern portion 42 and 44 be respectively formed on one surface and another surface, and wherein, coil conductive pattern portion 42 and 44 has the pattern of coil shape.
Coil conductive pattern portion 42 and 44 can comprise and has spiral coil pattern, and the coil conductive pattern portion 42 and 44 on a surface of insulated substrate 23 and another surface of being respectively formed at is by being formed in being electrically connected to each other by electrode 46 in insulated substrate 23.
Coil conductive pattern portion 42 and 44 and can being formed by the metal with excellent conductivity by electrode 46, such as, can be formed by silver (Ag), palladium (pd), aluminium (Al), nickel (Ni), titanium (Ti), gold (Au), copper (Cu), platinum (Pt) or their alloy.
Fig. 3 is the enlarged diagram of the example of the part A of Fig. 2.
With reference to Fig. 3, coil conductive pattern portion 42 and 44 can have formation oxide insulating film 31 in its surface.
The surperficial usable polymers Material coating in coil conductive pattern portion is to form dielectric film.But, can restriction be there is in the thickness reducing the dielectric film be formed as described above.Such as, when the thickness of reduction dielectric film is to form thin dielectric film, coil conductive pattern portion can be partially exposed.When coil conductive pattern portion is exposed, leakage current can be produced.Therefore, although inductance is normal under 1MHz, inductance can reduce in high frequency fast, causes waveform defect.
Therefore, in the exemplary embodiment, the oxide insulating film 31 formed by metal oxide can be formed on the surface in coil conductive pattern portion 42 and 44, thus has been formed uniformly thin dielectric film and has there is not the part not forming dielectric film.
Oxide insulating film 31 can be formed by the metal oxide with at least one metal be included in coil conductive pattern portion 42 and 44.Be oxidized by making coil conductive pattern portion 42 and 44 under high temperature or high humidity environment or by chemical etching, coil conductive pattern portion 42 and 44 be oxidized and form oxide insulating film 31.
The surface roughness Ra of oxide insulating film 31 can be about 0.6 μm to about 0.8 μm.
When forming oxide insulating film 31 by chemical etching etc., the surface roughness Ra of oxide insulating film 31 can increase to about 0.6 μm to about 0.8 μm.Surface area increases due to the surface roughness Ra increased, and can improve oxide insulating film 31 thus and is formed in interface adhesion between the second dielectric film on oxide insulating film 31 and can ensures reliability.
Oxide insulating film 31 can have the various shapes of such as acicular texture, rattan shape structure etc.
Oxide insulating film 31 can be formed as the thickness with about 0.5 μm to about 2.5 μm.
When the thickness of oxide insulating film 31 is less than about 0.5 μm, oxide insulating film may be damaged, the appearance of the waveform defect causing the generation of leakage current and inductance to reduce in high frequency.When the thickness of oxide insulating film 31 exceedes about 2.5 μm, inductance characteristic may deterioration.
Fig. 4 is the cutaway view of chip electronic assembly on length-thickness (L-T) direction according to exemplary embodiment; Fig. 5 is the enlarged diagram of the example of the part B of Fig. 4.
With reference to Fig. 4 and Fig. 5, same material can be used in the region it is formed between the coil conductive pattern portion 42 of oxide insulating film 31 and the adjacent patterns of 44.
Because oxide insulating film 31 can be formed as obviously thin while the shape on the surface with coil conductive pattern portion 42 and 44 is corresponding, therefore space can be formed in the region between adjacent patterns.Same material can be used in this space, thus can increase the volume of magnetic material, therefore, increases inductance by the volume increasing magnetic material.
Fig. 6 is the enlarged diagram of the example of the part C of Fig. 5.
With reference to Fig. 6, the average thickness being formed in the oxide insulating film 31 ' on the upper surface in coil conductive pattern portion 42 and 44 can than the oxide insulating film 31 be formed on the side surface in coil conductive pattern portion 42 and 44 " average thickness thick.
The upper surface in coil conductive pattern portion 42 and 44 can refer to the upper surface of the coil pattern based on dotted line A and B, the side surface in coil conductive pattern portion 42 and 44 can refer to the side surface of the coil pattern based on dotted line A and B, wherein, dotted line A and B extends from the edge of the coil pattern of the width w of definition coil pattern.
Owing to being formed in coil conductive pattern portion 42 and the relative impact being subject to external force in the process of compacting magnetic material sheets being etc. of the oxide insulating film 31 ' on the upper surface of 44, therefore the oxide insulating film 31 on the comparable side surface being formed in coil conductive pattern portion 42 and 44 of the thickness of oxide insulating film 31 ' " thickness thick, to ensure insulation property thus.
In addition, cause the reduction of the area of coil pattern and the increase of direct current (DC) resistance (Rdc) to prevent due to the increase of the thickness of oxide insulating film, be formed on the side surface in coil conductive pattern portion 42 and 44 be with relatively little subject to external force impact oxide insulating film 31 " oxide insulating film 31 ' that can be formed as than being formed on the upper surface in coil conductive pattern portion 42 and 44 is thin.
Namely, be formed in the average thickness of the oxide insulating film 31 ' on the upper surface in coil conductive pattern portion 42 and 44 than the oxide insulating film 31 be formed on the side surface in coil conductive pattern portion 42 and 44 " average thickness thick; therefore, excellent insulation property can be ensured and DC resistance (Rdc) can be reduced.
The thickness being formed in the oxide insulating film 31 ' on the upper surface in coil conductive pattern portion 42 and 44 can be about 1.8 μm to about 2.5 μm.
When the thickness of oxide insulating film 31 ' is less than about 1.8 μm, oxide insulating film may be damaged, the appearance of the waveform defect causing the generation of leakage current and inductance to reduce in high frequency.When the thickness of oxide insulating film 31 ' exceedes about 2.5 μm, inductance characteristic may deterioration.
Be formed in the oxide insulating film 31 on the side surface in coil conductive pattern portion 42 and 44 " thickness can be about 0.8 μm to about 1.8 μm.
At oxide insulating film 31 " thickness when being less than about 0.8 μm, may leakage current be produced and the waveform defect that inductance reduces in high frequency may be occurred.At oxide insulating film 31 " thickness when exceeding about 1.8 μm, the area of coil pattern can reduce, and causes the increase of DC resistance (Rdc).
In addition, the surface roughness Ra being formed in the oxide insulating film 31 ' on the upper surface in coil conductive pattern portion 42 and 44 can be greater than the oxide insulating film 31 on the side surface being formed in coil conductive pattern portion 42 and 44 " surface roughness.
Fig. 7 is the enlarged diagram of the example of the part A of Fig. 2; Fig. 8 is the enlarged diagram of the example of the part B of Fig. 4.
With reference to Fig. 7, polymer insulation film 32 can be formed as applying oxide insulating film 31.
Polymer insulation film 32 is formed by such as silk screen print method, the exposure of photoresist (PR) and the method for development method, gunite, infusion process etc.
Polymer insulation film 32 can be formed by any material that can form thin dielectric film on oxide insulating film 31, such as, can by epoxylite, polyimide resin, phenoxy resin, polysulfone resin, polycarbonate resin etc. are formed.
Polymer insulation film 32 can be formed as the thickness with about 1 μm to about 3 μm.
When the thickness of polymer insulation film 32 is less than about 1 μm, polymer insulation film may be damaged, thus may produce leakage current and may occur the circuit defect between the waveform defect that inductance reduces in high frequency or coil pattern.When the thickness of polymer insulation film 32 exceedes about 3 μm, inductance characteristic may deterioration.
Average thickness ratio between oxide insulating film 31 and polymer insulation film 32 can be about 1:1.2 to about 1:3.
Above-mentioned average thickness ratio is met with two insulating film structure of polymer insulation film 32 by forming oxide insulating film 31, the generation of leakage current can be prevented and waveform defect and circuit defect can be reduced, and by dielectric film is formed as thin, excellent inductance characteristic can be ensured.
With reference to Fig. 8, the shape on the surface of polymer insulation film 32 can be formed as corresponding with the shape on the surface in coil conductive pattern portion 42 and 44.
This means that polymer insulation film 32 is coated on the surface in coil conductive pattern portion 42 and 44 thinly, as shown in Figure 8.
When the surface of polymer insulation film 32 is formed as thin while the shape on the surface with coil conductive pattern portion 42 and 44 is corresponding, space can be formed in the region between coil pattern.Same material can be used in this space, thus can increase the volume of magnetic material, therefore, increases inductance by the volume increasing magnetic material.
Fig. 9 is magnified sweep electron microscope (SEM) photo of the part according to the coil conductive pattern portion its in the chip electronic assembly of exemplary embodiment being formed with dielectric film.
With reference to Fig. 9, it is seen that, oxide insulating film 31 as the first dielectric film is formed on the surface in coil conductive pattern portion 42 by making the surface oxidation in coil conductive pattern portion 42, and the polymer insulation film 32 as the second dielectric film is formed on oxide insulating film 31.
By forming dielectric film to have double-decker as above, even if when dielectric film is formed as thin, also can prevents the contact between coil conductive pattern portion and magnetic material 50 ' and waveform defect and circuit defect can be reduced.
The end being formed in the coil conductive pattern portion 42 on a surface of insulated substrate 23 can be exposed in their length direction end surfaces of magnetic body 50, and the end being formed in the coil conductive pattern portion 44 on another surface of insulated substrate 23 can be exposed to the surface of the other end in their length direction of magnetic body 50.
External electrode 80 can be formed in their length direction two end surfaces of magnetic body 50, to be connected respectively to the coil conductive pattern portion 42 and 44 of in their length direction two end surfaces being exposed to magnetic body 50.
External electrode 80 can be formed by the metal with excellent conductivity, such as, can be formed by nickel (Ni), copper (Cu), tin (Sn), silver (Ag) or their alloy etc.
Figure 10 is the flow chart of the method for the manufacture chip electronic assembly illustrated according to exemplary embodiment.
With reference to Figure 10, coil conductive pattern portion 42 and 44 can be formed on insulated substrate 23.
Insulated substrate 23 is not particularly restricted, but can be such as printed circuit board (PCB) (PCB), ferrite substrate, Metal Substrate soft magnetism substrate etc., and can have the thickness of about 40 μm to about 100 μm.
The method forming coil conductive pattern portion 42 and 44 can be such as galvanoplastic, but is not limited thereto.
Coil conductive pattern portion 42 and 44 can be formed by the metal with excellent conductivity, such as, can be formed by silver (Ag), palladium (pd), aluminium (Al), nickel (Ni), titanium (Ti), gold (Au), copper (Cu), platinum (Pt) or their alloy.
Hole can be formed in a part for insulated substrate 23, and available conductive material fills this hole to be formed by electrode 46, be electrically connected to each other with the coil conductive pattern portion 42 and 44 on another surface by being made the surface being respectively formed at insulated substrate 23 by electrode 46.
Boring, laser processing, sandblasting, punching etc. can be performed to the core of insulated substrate 23 and form the hole penetrating insulated substrate 23.
Then, oxide insulating film 31 can be formed on the surface in coil conductive pattern portion 42 and 44.
By making to be included at least one burning in coil conductive pattern portion 42 and 44 to form oxide insulating film 31.
Be not particularly restricted by the method making the surface oxidation in coil conductive pattern portion 42 and 44 form oxide insulating film 31.Such as, by making coil conductive pattern portion 42 and 44 be oxidized under high temperature or high humidity environment or make coil conductive pattern portion 42 and 44 be oxidized by chemical etching to form oxide insulating film 31.
When being formed oxide insulating film 31 by chemical etching, the surface roughness Ra of oxide insulating film 31 can be improved.
The surface roughness Ra of oxide insulating film 31 can be about 0.6 μm to about 0.8 μm.
When forming oxide insulating film 31 by chemical etching etc., the surface roughness Ra of oxide insulating film 31 can increase to about 0.6 μm to about 0.8 μm.When surface area increases due to the surface roughness Ra increased, oxide insulating film 31 can be improved thus and be formed in interface adhesion between the second dielectric film on oxide insulating film 31 and can reliability be ensured.
Oxide insulating film 31 can have the various shapes of such as acicular texture, rattan shape structure etc.
When by making coil conductive pattern portion 42 and 44 oxidation form oxide insulating film 31 in high temperature environments, the cleaning effect between coil conductive pattern portion 42 and the coil pattern of 44 can be splendid.
Oxide insulating film 31 can be formed as the thickness with about 0.5 μm to about 2.5 μm.
When the thickness of oxide insulating film 31 is less than about 0.5 μm, oxide insulating film may be damaged, the appearance of the waveform defect causing the generation of leakage current and inductance to reduce in high frequency.When the thickness of oxide insulating film 31 exceedes about 2.5 μm, inductance characteristic may deterioration.
When forming oxide insulating film 31, the concentration, oxidizing temperature, time etc. of controlled oxide layer formation solution regulate the thickness of oxide insulating film 31.
Be formed in the oxide insulating film 31 on the comparable side surface being formed in coil conductive pattern portion 42 and 44 of average thickness of the oxide insulating film 31 ' on the upper surface in coil conductive pattern portion 42 and 44 " average thickness thick.
Be formed in the average thickness of the oxide insulating film 31 ' on the upper surface in coil conductive pattern portion 42 and 44 than the oxide insulating film 31 be formed on the side surface in coil conductive pattern portion 42 and 44 " average thickness thick, thus excellent insulation property can be ensured and DC resistance (Rdc) can be reduced.
The thickness being formed in the oxide insulating film 31 ' on the upper surface in coil conductive pattern portion 42 and 44 can be about 1.8 μm to about 2.5 μm.
When the thickness of oxide insulating film 31 ' is less than about 1.8 μm, oxide insulating film may be damaged, the appearance of the waveform defect causing the generation of leakage current and inductance to reduce in high frequency.When the thickness of oxide insulating film 31 ' exceedes about 2.5 μm, inductance characteristic may deterioration.
Be formed in the oxide insulating film 31 on the side surface in coil conductive pattern portion 42 and 44 " thickness can be about 0.8 μm to about 1.8 μm.
At oxide insulating film 31 " thickness when being less than about 0.8 μm, may leakage current be produced and the waveform defect that inductance reduces in high frequency may be occurred.At oxide insulating film 31 " thickness when exceeding about 1.8 μm, the area of coil pattern can reduce, and causes the increase of DC resistance (Rdc).
Then, polymer insulation film 32 can be formed as applying oxide insulating film 31.
Polymer insulation film 32 is formed by such as silk screen print method, the exposure of photoresist (PR) and the method well known in the art of development method, gunite, infusion process etc.
Polymer insulation film 32 can be formed by any material that can form thin dielectric film on oxide insulating film 31, such as, can be formed by photoresist (PR), epoxy, polyimide resin, phenoxy resin, polysulfone resin, polycarbonate resin etc.
Polymer insulation film 32 can be formed as the thickness with about 1 μm to about 3 μm.
When the thickness of polymer insulation film 32 is less than about 1 μm, polymer insulation film may be damaged, thus may produce leakage current and may occur the circuit defect between the waveform defect that inductance reduces in high frequency or coil pattern.When the thickness of polymer insulation film 32 exceedes about 3 μm, inductance characteristic may deterioration.
The shape on the surface of polymer insulation film 32 can be formed as corresponding with the shape on the surface in coil conductive pattern portion 42 and 44.
The method forming polymer insulation film 32 is not particularly restricted, as long as it is simultaneously corresponding with the shape on the surface in coil conductive pattern portion 42 and 44 polymer insulation film 32 can be formed as film.Such as, the infusion process by chemical vapour deposition (CVD) (CVD) method or use low viscosity polymer coating solution forms polymer insulation film 32.
When the surface of polymer insulation film 32 is formed as thin while the shape on the surface with coil conductive pattern portion 42 and 44 is corresponding, space can be formed in the region between coil pattern.This space of available same material, thus the volume of magnetic material can be increased, therefore, increase inductance by the volume increasing magnetic material.
By forming dielectric film to have the double-decker according to exemplary embodiment, even if when dielectric film is formed as thin, also can prevents the contact between coil conductive pattern portion and magnetic material and waveform defect and circuit defect can be reduced.
Then, the stacked magnetic material layer above and below of the insulated substrate 23 in coil conductive pattern portion 42 and 44 can be formed with respectively thereon to form magnetic body 50.
Can on two of insulated substrate 23 surface stacked magnetic material layer, and suppress magnetic material layer by laminating or isostatic pressed method for making and form magnetic body 50.Here, available same material hole is to form core 55.
In addition, external electrode 80 can be formed as being connected to the coil conductive pattern portion 42 and 44 of the end surfaces being exposed to magnetic body 50.
External electrode 80 can be formed by the paste comprising the metal with excellent conductivity, such as, can be formed by the conductive paste comprising nickel (Ni), copper (Cu), tin (Sn), silver (Ag) or their alloy.External electrode 80 can be formed by print process, infusion process etc. according to the shape of external electrode 80.
The description of the feature identical with the feature of the chip electronic assembly according to previous exemplary embodiment will be omitted.
As mentioned above, according in the chip electronic assembly of exemplary embodiment and manufacture method thereof, even if when by when being formed in coil conductive pattern portion than the dielectric film thin according to the dielectric film of prior art, also coil conductive pattern portion can be prevented to be exposed, magnetic material and coil conductive pattern portion can not be contacted with each other.Therefore, waveform defect in high frequency can be prevented.
Although illustrate and describe exemplary embodiment above, being apparent that those skilled in the art, when not departing from the scope of the present invention be defined by the claims, can modifying and change.
Claims (31)
1. a chip electronic assembly, comprising:
Magnetic body, is wherein embedded with coil conductive pattern portion; And
Oxide insulating film, is arranged on the surface in coil conductive pattern portion.
2. chip electronic assembly as claimed in claim 1, described chip electronic assembly also comprises the polymer insulation film of coating oxide insulating film.
3. chip electronic assembly as claimed in claim 1, wherein, oxide insulating film is formed by the metal oxide comprising at least one metal forming coil conductive pattern portion.
4. chip electronic assembly as claimed in claim 1, wherein, oxide insulating film has the surface roughness of 0.6 μm to 0.8 μm.
5. chip electronic assembly as claimed in claim 1, wherein, the surface roughness being formed in the oxide insulating film on the upper surface in coil conductive pattern portion is greater than the surface roughness of the oxide insulating film on the side surface being formed in coil conductive pattern portion.
6. chip electronic assembly as claimed in claim 1, wherein, oxide insulating film has the thickness of 0.5 μm to 2.5 μm.
7. chip electronic assembly as claimed in claim 1, wherein, the average thickness being formed in the oxide insulating film on the upper surface in coil conductive pattern portion is greater than the average thickness of the oxide insulating film on the side surface being formed in coil conductive pattern portion.
8. chip electronic assembly as claimed in claim 1, wherein, the oxide insulating film be formed on the upper surface in coil conductive pattern portion has the thickness of 1.8 μm to 2.5 μm.
9. chip electronic assembly as claimed in claim 1, wherein, the oxide insulating film be formed on the side surface in coil conductive pattern portion has the thickness of 0.8 μm to 1.8 μm.
10. chip electronic assembly as claimed in claim 2, wherein, the shape on the surface of polymer insulation film is corresponding with the shape on the surface in coil conductive pattern portion.
11. chip electronic assemblies as claimed in claim 2, wherein, polymer insulation film has the thickness of 1 μm to 3 μm.
12. chip electronic assemblies as claimed in claim 2, wherein, the average thickness between oxide insulating film and polymer insulation film is than being 1:1.2 to 1:3.
13. chip electronic assemblies as claimed in claim 1, wherein, the region same material between the adjacent patterns in coil conductive pattern portion.
14. 1 kinds of chip electronic assemblies, comprising:
Magnetic body, comprises insulated substrate;
Coil conductive pattern portion, be arranged on insulated substrate at least one on the surface;
First dielectric film, is arranged on the surface in coil conductive pattern portion; And
Second dielectric film, applies the first dielectric film.
15. chip electronic assemblies as claimed in claim 14, wherein, the first dielectric film is formed by the metal oxide with at least one metal be included in coil conductive pattern portion.
16. chip electronic assemblies as claimed in claim 14, wherein, the second dielectric film comprises polymer,
The shape on the surface of the second dielectric film is corresponding with the shape on the surface in coil conductive pattern portion.
17. chip electronic assemblies as claimed in claim 14, wherein, the first dielectric film has the surface roughness of 0.6 μm to 0.8 μm.
18. chip electronic assemblies as claimed in claim 14, wherein, the surface roughness being formed in the first dielectric film on the upper surface in coil conductive pattern portion be greater than be formed in coil conductive pattern portion side surface on the surface roughness of the first dielectric film.
19. chip electronic assemblies as claimed in claim 14, wherein, the average thickness being formed in the first dielectric film on the upper surface in coil conductive pattern portion be greater than be formed in coil conductive pattern portion side surface on the average thickness of the first dielectric film.
20. chip electronic assemblies as claimed in claim 14, wherein, the region same material between the adjacent patterns in coil conductive pattern portion.
21. 1 kinds of methods manufacturing chip electronic assembly, described method comprises the steps:
Coil conductive pattern portion is formed on the surface at least one of insulated substrate;
The surface in coil conductive pattern portion forms oxide insulating film; And
Be formed with the stacked magnetic material layer above and below of the insulated substrate in coil conductive pattern portion thereon to form magnetic body.
22. methods as claimed in claim 21, described method also comprises the polymer insulation film forming coating oxide insulating film.
23. methods as claimed in claim 21, wherein, form oxide insulating film by making the surface oxidation in coil conductive pattern portion.
24. methods as claimed in claim 21, wherein, are formed as the surface roughness with 0.6 μm to 0.8 μm by oxide insulating film.
25. methods as claimed in claim 21, wherein, are formed as the insulated by oxide thickness than being formed on the side surface in coil conductive pattern portion by the oxide insulating film be formed on the upper surface in coil conductive pattern portion.
26. chip electronic assemblies as claimed in claim 1, wherein, manufacture oxide insulating film by the method comprised the steps:
Oxide insulating film is formed by making the outer oxide of coil.
27. chip electronic assemblies as claimed in claim 26, manufacture oxide insulating film by the method comprised the steps:
By exposing coil or form oxide insulating film by chemical etching under high temperature or high humidity environment.
28. chip electronic assemblies as claimed in claim 27, wherein, oxide insulating film has the surface roughness of 0.6 μm to 0.8 μm.
29. chip electronic assemblies as claimed in claim 14, wherein, oxide insulating film is manufactured by the method comprised the steps:
Oxide insulating film is formed by making the outer oxide of coil.
30. chip electronic assemblies as claimed in claim 29, wherein, manufacture oxide insulating film by the method comprised the steps:
By exposing coil or form oxide insulating film by chemical etching under high temperature or high humidity environment.
31. chip electronic assemblies as claimed in claim 30, wherein, oxide insulating film has the surface roughness of 0.6 μm to 0.8 μm.
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Also Published As
| Publication number | Publication date |
|---|---|
| CN104575937B (en) | 2018-05-18 |
| KR101952859B1 (en) | 2019-02-28 |
| KR102138887B1 (en) | 2020-07-29 |
| KR20150046717A (en) | 2015-04-30 |
| KR101565703B1 (en) | 2015-11-03 |
| KR20150073900A (en) | 2015-07-01 |
| CN108597730A (en) | 2018-09-28 |
| CN108597730B (en) | 2021-02-05 |
| KR20180031653A (en) | 2018-03-28 |
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