CN104425459B - 半导体装置及半导体装置的检查方法 - Google Patents
半导体装置及半导体装置的检查方法 Download PDFInfo
- Publication number
- CN104425459B CN104425459B CN201310729562.5A CN201310729562A CN104425459B CN 104425459 B CN104425459 B CN 104425459B CN 201310729562 A CN201310729562 A CN 201310729562A CN 104425459 B CN104425459 B CN 104425459B
- Authority
- CN
- China
- Prior art keywords
- wiring
- semiconductor device
- ground connection
- terminal
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Sample1 | Sample2 | |
磁场屏蔽效果(dB) | 19.9 | 7.6 |
Claims (8)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP187132/2013 | 2013-09-10 | ||
JP2013187132A JP5684349B1 (ja) | 2013-09-10 | 2013-09-10 | 半導体装置および半導体装置の検査方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN104425459A CN104425459A (zh) | 2015-03-18 |
CN104425459B true CN104425459B (zh) | 2017-10-20 |
Family
ID=52624997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201310729562.5A Active CN104425459B (zh) | 2013-09-10 | 2013-12-26 | 半导体装置及半导体装置的检查方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20150070046A1 (zh) |
JP (1) | JP5684349B1 (zh) |
CN (1) | CN104425459B (zh) |
TW (1) | TWI503931B (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5684349B1 (ja) | 2013-09-10 | 2015-03-11 | 株式会社東芝 | 半導体装置および半導体装置の検査方法 |
KR20160036945A (ko) * | 2014-09-26 | 2016-04-05 | 삼성전기주식회사 | 인쇄회로기판 및 이를 포함하는 전자부품 패키지 |
JP5933047B2 (ja) * | 2015-01-13 | 2016-06-08 | 株式会社東芝 | 半導体装置の製造方法、半導体装置の検査方法、および半導体装置 |
US10379156B2 (en) | 2015-05-29 | 2019-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump ball testing system and method |
JP6418605B2 (ja) * | 2015-07-31 | 2018-11-07 | 東芝メモリ株式会社 | 半導体装置および半導体装置の製造方法 |
JP6397806B2 (ja) | 2015-09-11 | 2018-09-26 | 東芝メモリ株式会社 | 半導体装置の製造方法および半導体装置 |
WO2017179325A1 (ja) * | 2016-04-11 | 2017-10-19 | 株式会社村田製作所 | 高周波部品 |
US9793222B1 (en) | 2016-04-21 | 2017-10-17 | Apple Inc. | Substrate designed to provide EMI shielding |
JP6887326B2 (ja) * | 2017-06-28 | 2021-06-16 | 株式会社ディスコ | 半導体パッケージの形成方法 |
JP7001096B2 (ja) * | 2017-08-21 | 2022-01-19 | 株式会社村田製作所 | 電子部品モジュール及び電子部品モジュールの製造方法 |
CN112309873B (zh) * | 2019-07-26 | 2023-11-10 | 江苏长电科技股份有限公司 | 电磁屏蔽封装结构及其封装方法 |
US11694972B2 (en) * | 2020-06-09 | 2023-07-04 | Mediatek Inc. | Semiconductor package with heatsink |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5483101A (en) * | 1993-12-10 | 1996-01-09 | Nec Corporation | Multilayer printed circuit board |
CN1774804A (zh) * | 2003-04-15 | 2006-05-17 | 波零公司 | 用于电子元件封装的emi屏蔽 |
CN102105981A (zh) * | 2008-07-31 | 2011-06-22 | 斯盖沃克斯解决方案公司 | 半导体封装的集成干扰屏蔽罩及其制造方法 |
CN102610591A (zh) * | 2011-01-20 | 2012-07-25 | 夏普株式会社 | 半导体模块 |
CN102623438A (zh) * | 2011-01-31 | 2012-08-01 | 株式会社东芝 | 半导体装置 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6552425B1 (en) * | 1998-12-18 | 2003-04-22 | Intel Corporation | Integrated circuit package |
KR100691632B1 (ko) | 2006-05-16 | 2007-03-12 | 삼성전기주식회사 | 반도체칩, 반도체칩의 제조방법 및 반도체칩 패키지 |
JP2008251608A (ja) | 2007-03-29 | 2008-10-16 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2009236712A (ja) * | 2008-03-27 | 2009-10-15 | Toyota Motor Corp | 半導体集積回路及び半導体集積回路の検査装置、検査方法 |
JP2010109274A (ja) | 2008-10-31 | 2010-05-13 | Sanyo Electric Co Ltd | 半導体モジュールおよび半導体モジュールの製造方法 |
US9362196B2 (en) | 2010-07-15 | 2016-06-07 | Kabushiki Kaisha Toshiba | Semiconductor package and mobile device using the same |
JP2012146882A (ja) | 2011-01-13 | 2012-08-02 | Renesas Electronics Corp | 半導体装置 |
US8766654B2 (en) * | 2012-03-27 | 2014-07-01 | Universal Scientific Industrial Co., Ltd. | Package structure with conformal shielding and inspection method using the same |
US8948712B2 (en) * | 2012-05-31 | 2015-02-03 | Skyworks Solutions, Inc. | Via density and placement in radio frequency shielding applications |
JP5684349B1 (ja) | 2013-09-10 | 2015-03-11 | 株式会社東芝 | 半導体装置および半導体装置の検査方法 |
KR102163707B1 (ko) * | 2013-11-14 | 2020-10-08 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐층을 갖는 반도체 패키지 및 테스트 방법 |
-
2013
- 2013-09-10 JP JP2013187132A patent/JP5684349B1/ja active Active
- 2013-12-18 TW TW102146999A patent/TWI503931B/zh active
- 2013-12-26 CN CN201310729562.5A patent/CN104425459B/zh active Active
-
2014
- 2014-09-02 US US14/474,635 patent/US20150070046A1/en not_active Abandoned
-
2019
- 2019-04-17 US US16/386,774 patent/US11715701B2/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5483101A (en) * | 1993-12-10 | 1996-01-09 | Nec Corporation | Multilayer printed circuit board |
CN1774804A (zh) * | 2003-04-15 | 2006-05-17 | 波零公司 | 用于电子元件封装的emi屏蔽 |
CN102105981A (zh) * | 2008-07-31 | 2011-06-22 | 斯盖沃克斯解决方案公司 | 半导体封装的集成干扰屏蔽罩及其制造方法 |
CN102610591A (zh) * | 2011-01-20 | 2012-07-25 | 夏普株式会社 | 半导体模块 |
CN102623438A (zh) * | 2011-01-31 | 2012-08-01 | 株式会社东芝 | 半导体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20150070046A1 (en) | 2015-03-12 |
US11715701B2 (en) | 2023-08-01 |
JP2015056427A (ja) | 2015-03-23 |
US20190244912A1 (en) | 2019-08-08 |
TWI503931B (zh) | 2015-10-11 |
JP5684349B1 (ja) | 2015-03-11 |
TW201511189A (zh) | 2015-03-16 |
CN104425459A (zh) | 2015-03-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104425459B (zh) | 半导体装置及半导体装置的检查方法 | |
CN102339817B (zh) | 半导体封装以及使用其的移动设备 | |
CN103996670B (zh) | 半导体装置 | |
TWI615065B (zh) | 柔性線路板及其製作方法 | |
CN104349575B (zh) | 柔性电路板及其制作方法 | |
US20150235966A1 (en) | Wiring board and semiconductor device using the same | |
CN105792504B (zh) | 一种具有屏蔽措施的pcb空穴埋置装置及制备工艺 | |
CN104754855A (zh) | 柔性电路板及其制作方法 | |
CN104582240B (zh) | 电路板及电路板制作方法 | |
CN104716114A (zh) | 半导体装置 | |
CN104955260B (zh) | 部件内置电路板 | |
KR20080001395A (ko) | 반도체 패키지 및 그 제조 방법 | |
CN101814459A (zh) | 半导体封装的安装结构及等离子体显示器件 | |
CN105514053A (zh) | 半导体封装件及其制法 | |
WO2020057216A1 (zh) | 一种内存信号测试板 | |
TWI400012B (zh) | 電路板和構造電路板的方法 | |
JP2006261622A (ja) | 集積回路パッケージ構造とそのパッケージ方法 | |
JP2012033786A (ja) | 配線基板 | |
CN207897217U (zh) | 一种高信赖性碳墨线路板 | |
CN113015314B (zh) | 电路板装置 | |
JP5933047B2 (ja) | 半導体装置の製造方法、半導体装置の検査方法、および半導体装置 | |
TWI712358B (zh) | 電路板裝置 | |
CN101894761B (zh) | 开窗型球栅阵列封装结构的基板及其制造方法 | |
CN206963178U (zh) | 一种具有良好导电性能的电源厚铜板 | |
JP2630294B2 (ja) | 混成集積回路装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
TA01 | Transfer of patent application right | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20170803 Address after: Tokyo, Japan Applicant after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Applicant before: Toshiba Corp. |
|
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo, Japan Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo, Japan Patentee before: Japanese businessman Panjaya Co.,Ltd. Address after: Tokyo, Japan Patentee after: Kaixia Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |
|
TR01 | Transfer of patent right | ||
TR01 | Transfer of patent right |
Effective date of registration: 20211014 Address after: Tokyo, Japan Patentee after: Japanese businessman Panjaya Co.,Ltd. Address before: Tokyo, Japan Patentee before: TOSHIBA MEMORY Corp. |