CN104422870A - Test structure and test method for micro grooves - Google Patents
Test structure and test method for micro grooves Download PDFInfo
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- CN104422870A CN104422870A CN201310410805.9A CN201310410805A CN104422870A CN 104422870 A CN104422870 A CN 104422870A CN 201310410805 A CN201310410805 A CN 201310410805A CN 104422870 A CN104422870 A CN 104422870A
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Abstract
The invention relates to a test structure and a test method for micro grooves. The test structure comprises a first test piece, a second test piece, a first connecting end and a second connecting end, wherein the first test piece and the second test piece are vertically stacked; strip conductor arrays connected into a whole are arranged in the first test piece and the second test piece; the strip conductors in the first test piece and the strip conductors in the second test piece are perpendicular to one another; and according to the first connecting end and the second connecting end, the first test piece and the second test piece are respectively connected to a first test pad and a second test pad. According to the method disclosed by the invention, the defect in the prior that lots of samples need to be detected is overcome, all the micro grooves in the whole wafer map can be scanned by virtue of the test structure, and analysis is performed according to the current, so that the result can be accurate, and the whole process is simple and time-saving.
Description
Technical field
The present invention relates to semiconductor applications, particularly, the present invention relates to a kind of test structure and method of testing of microchannels.
Background technology
Along with the sustainable development of integrated circuit technique, by integrated more devices on chip, chip also will adopt clock speed faster.Under the propelling that these require, the physical dimension of device will constantly reduce, and constantly adopts new material, new technology and new manufacturing process in the manufacturing process of chip.These improvement are very large for the aging effects of individual devices, may cause that the fragility of regional area increases, the raising of power density, device complicacy increase and introduce new inefficacy mechanism, less fault tolerant workspace means that life problems must at must considering of designing at the very start simultaneously, and carry out monitoring and testing in the exploitation and manufacture process of device, up to completing of final products always.
The current monitoring to semiconductor devices and test generally comprise carries out various electrical performance testing and reliability of technology test to the device with special package form, mostly adopt static easy assess memorizer (referred to as static RAM or Static RAM at present, SRAM) as the test platform of assessment electric property, along with sram cell size become more and more less, in the preparation process of device, microchannels (Micro trench) 103(may be formed as shown in the part in circle) between different metal layer 101 and 102, as shown in Figure 1, described microchannels 103(Micro trench) voltage breakdown (the Breakdown Voltage of semiconductor devices can be caused, VBD) degradation, and in advanced technology nodes, voltage breakdown (the Breakdown Voltage of described semiconductor devices, VBD) performance becomes one of topmost parameter evaluating device performance.Therefore the VBD performance how evaluating device has great importance.
Mostly detected by SEM otch (SEM cut) performance to described microchannels 103 in prior art, but described detection method can only detect qualitatively to described microchannels 103, and described detection needs the more time, and in order to obtain result more accurately, need to detect a large amount of samples, but effect is unsatisfactory.
Therefore, along with reducing of semiconductor dimensions, the detection method for microchannels exist lose time, sample mainly with and can only many drawbacks such as qualitative detection, production efficiency is restricted, need badly at present and described detection method is improved, to eliminate the problems referred to above.
Summary of the invention
In summary of the invention part, introduce the concept of a series of reduced form, this will further describe in embodiment part.Summary of the invention part of the present invention does not also mean that the key feature and essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection domain attempting to determine technical scheme required for protection.
The present invention, in order to overcome current existing problems, provides a kind of test structure of microchannels, comprising:
First test block and the second test block, described first test block and described second test block stacked on top of one another are arranged, respectively containing the strip conductor array connected as one in described first test block and described second test block, the strip conductor in described first test block is mutually vertical with the strip conductor in described second test block;
First link and the second link, described first test block and described second test block are connected to the first testing weld pad and the second testing weld pad by described first link and described second link respectively.
As preferably, described first test block and described second test block are all in pectination, all containing connecting line and the some strip conductors be set in parallel on described connecting line, the strip conductor in described first test block is mutually vertical with the strip conductor in described second test block.
As preferably, described first test block and described second test block are arranged in upper and lower two parallel planes.
As preferably, described first test block and described second test block are positioned at same plane with described first testing weld pad and described second testing weld pad respectively.
As preferably, described first test block and described second test block are metallic test part.
As preferably, the width of described strip conductor is identical.
As preferably, the width of described strip conductor be the basic width of setting n doubly wherein n be natural number.
Present invention also offers a kind of method of testing based on above-mentioned test structure, comprising:
Step (a) applies scanning voltage on described first testing weld pad and described second testing weld pad;
Step (b) record applies Leakage Current during described scanning voltage;
Step (c) is analyzed according to the VBD performance of the change of described leakage current to described microchannels.
As preferably, described in step (a), scanning voltage is less than or equal to 100V.
As preferably, described method is used for detecting whole wafer map.
As preferably, the voltage become rapidly when reaching greatly peak value when described Leakage Current in described step (c) is voltage breakdown.
As preferably, described method is further comprising the steps of:
Change the width of strip conductor in the strip conductor array of described first test block and described second test block, test described microchannels, according to test result analysis, strip conductor width is on the impact of described microchannels VBD performance.
The method of the invention can by being positioned at the test block of lower planes, obtain the data evaluating device VBD, to meet the demand of current advanced technology nodes, the method of the invention is by the electric property of described test structure, the performance of described microchannels is evaluated, the detection of described groove VBD performance is realized by the detection of electric current, make the method more simple, the method of the invention is except its performance of qualitative analysis, the association between described Leakage Current and VBD can also be set up, quantitative test is carried out by described association, to carry out assay to the VBD performance of described microchannels more accurately.
The method of the invention changes in prior art the drawback needed detecting a large amount of samples, all microchannels on whole wafer map can be scanned by described test structure, analyze according to electric current, enable described result more accurate, and whole process more simple, save time.
Accompanying drawing explanation
Following accompanying drawing of the present invention in this as a part of the present invention for understanding the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining device of the present invention and principle.In the accompanying drawings,
Fig. 1 is the structural representation forming described microchannels in prior art;
Fig. 2 is the structural representation of test structure described in the embodiment of the invention;
Fig. 3 affects schematic diagram to test result for test block line thickness in test structure described in the embodiment of the invention;
Fig. 4 is the process chart of method of testing described in an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details is given to provide more thorough understanding of the invention.But, it is obvious to the skilled person that the present invention can be implemented without the need to these details one or more.In other example, in order to avoid obscuring with the present invention, technical characteristics more well known in the art are not described.
In order to thoroughly understand the present invention, by following description, detailed description is proposed, so that test structure of the present invention and method of testing to be described.Obviously, the specific details that the technician that execution of the present invention is not limited to semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other embodiments.
Should give it is noted that term used here is only to describe specific embodiment, and be not intended to restricted root according to exemplary embodiment of the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative be also intended to comprise plural form.In addition, it is to be further understood that, " comprise " when using term in this manual and/or " comprising " time, it indicates exists described feature, entirety, step, operation, element and/or assembly, but does not get rid of existence or additional other features one or more, entirety, step, operation, element, assembly and/or their combination.
Now, describe in more detail with reference to the accompanying drawings according to exemplary embodiment of the present invention.But these exemplary embodiments can multiple different form be implemented, and should not be interpreted as being only limited to the embodiments set forth herein.Should be understood that, providing these embodiments to be of the present inventionly disclose thorough and complete to make, and the design of these exemplary embodiments fully being conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region, and use the element that identical Reference numeral represents identical, thus will omit description of them.
The present invention is long to the described microchannels test duration in order to solve in prior art, and the accurate not problem of result, provides a kind of test structure of new microchannels, comprising:
First test block and the second test block, described first test block and the stacked setting of described second test block, all containing the strip conductor array connected as one in described first test block and described second test block, the strip conductor in described first test block is mutually vertical with the strip conductor in described second test block;
First link and the second link, described first test block and described second test block are connected to the first pad and the second pad by described first link and described second link respectively.
Particularly, described strip conductor array is integrated setting, comprise multiple strip conductor be arranged in parallel, as preferably, in one embodiment of the invention, as shown in Figure 2, described first test block 203 and the second test block 204 are all in pectination, wherein said first test block 203 is arranged in the plane of below, and described second test block 204 is arranged in the plane of top, and described upper and lower two planes be arranged in parallel.
Further, described first test block 203 comprises connecting line and is set in parallel in the strip conductor on described connecting line, described multiple strip conductor forms described strip conductor array, wherein, the width of described strip conductor can be identical or different, as preferably, described strip conductor can select basic width 1-n doubly in one or more combination, further, one or more combinations in 1-10 times of basic width can be preferably.
Structure and described first test block 203 of described second test block 204 are similar, width in described first test block 203 and described second test block 204 between the number of strip conductor, width and strip conductor can be identical or different, arrange according to actual needs, be not limited to a certain situation.
Further, described first test block 203 and described second test block 204 are metallic test part, and described metallic test part can select copper, tungsten, titanium, cobalt, nickel, aluminium, yttrium, one or more in ytterbium and erbium, are not limited to a certain.Be preferably copper in this embodiment.
Described first test block 203 is connected with described first pad 202 by the first link 205, as preferably, described first test block 203 be arranged in parallel with described first pad 202, further, described first test block 203, first link 205 is in the same plane with described first pad 202, further, described first link 205 and described strip conductor be arranged in parallel.
Described second test block 204 is connected with described second pad 201 by the second link 206, as preferably, described second test block 204 be arranged in parallel with described second pad 201, further, described first test block 204, second link 206 is in the same plane with described second pad 201, and further, described second link 206 is vertical with described strip conductor, described second link 206 is the extended line of connecting line in described second test block 204, additionally need not arrange link.
As shown in Figure 2, strip conductor in described first test block 203 is horizontally set, the strip conductor of described second test block 204 is longitudinally arrange, although be positioned in planes different up and down, or even in the plane be parallel to each other, the mutually vertical setting horizontal in the strip conductor of described second test block 204 of the strip conductor in described first test block 203.
Present invention also offers a kind of method utilizing described detection architecture to detect microchannels, described method comprises:
Step (a) applies scanning voltage on described first pad and described second pad;
Step (b) record applies Leakage Current during described scanning voltage;
Step (c) is analyzed according to the performance of the change of described leakage current to described microchannels.
The method of the invention is by the electric property of described test structure, the performance of described microchannels is evaluated, wherein, described in described step (a), scanning voltage is less than or equal to 100V, when described first pad and described second pad apply described scanning voltage, along with the progressively increase of voltage, electric current constantly increases, as shown in the lines 1-3 in Fig. 3, evaluated by the performance of change to described microchannels of described electric current.
Particularly, along with the increase of voltage, electric current constantly increases, when described Leakage Current increases rapidly, reach peak value, voltage corresponding to current peak place as shown in Figure 3 is the voltage breakdown VBD of described device, the detection method that the detection of described electric current can select this area conventional, the detection of described electric current is simple, therefore by described method can the realization of simple and fast more to the detection of the VBD performance of described microchannels.
As preferably, because the size of described electric current can carry out precision measurement, therefore the method for the invention is except its performance of qualitative analysis, the association between described Leakage Current and VBD can also be set up, quantitative test is carried out, to carry out assay to the VBD performance of described microchannels more accurately by described association.
As preferably, described method can also investigate the relation between described strip conductor width and described microchannels VBD performance, particularly, change the width of strip conductor in the strip conductor array of described first test block and described second test block, test described microchannels, according to test result analysis, strip conductor width is on the impact of described microchannels performance.
In of the present invention one particularly embodiment, as shown in Figure 3, wherein said voltage-current curve, the curve that wherein said curve 1 is the width of described strip conductor when being 10 times of setting value, the curve that described curve 2 is the width of described strip conductor when being 2 times of setting value, the curve that described curve 1 is the width of described strip conductor when being 1 times of setting value, the setting value of wherein said strip conductor width can set according to actual conditions, is not limited to a certain numerical value.
Can be found out by the data in Fig. 3, along with the change of described strip conductor width is large, the VBD performance degradation of device is more serious, meaning that larger metal width can cause makes the performance of described microchannels poorer, the result obtained by described method measurement is consistent with the testing result that SEM otch (SEM cut) method obtains, and further demonstrates the accuracy of the method for the invention.
Further, the method of the invention changes in prior art the drawback needed detecting a large amount of samples, all microchannels on whole wafer map can be scanned by described test structure, analyze according to electric current, enable described result more accurate, and whole process more simple, save time.
The method of the invention can by being positioned at the test block of lower planes, obtain the data evaluating device VBD, to meet the demand of current advanced technology nodes, the method of the invention is by the electric property of described test structure, the performance of described microchannels is evaluated, the detection of described groove VBD performance is realized by the detection of electric current, make the method more simple, the method of the invention is except its performance of qualitative analysis, the association between described Leakage Current and VBD can also be set up, quantitative test is carried out by described association, to carry out assay to the VBD performance of described microchannels more accurately.
Fig. 4 is the process chart of method of testing described in an embodiment of the present invention, particularly, comprises the following steps:
Step (a) applies scanning voltage on described first testing weld pad and described second testing weld pad;
Step (b) record applies Leakage Current during described scanning voltage;
Step (c) is analyzed according to the VBD performance of the change of described leakage current to described microchannels.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just for the object of illustrating and illustrate, and is not intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, more kinds of variants and modifications can also be made according to instruction of the present invention, within these variants and modifications all drop on the present invention's scope required for protection.Protection scope of the present invention defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a test structure for microchannels, comprising:
First test block and the second test block, described first test block and described second test block stacked on top of one another are arranged, respectively containing the strip conductor array connected as one in described first test block and described second test block, the strip conductor in described first test block is mutually vertical with the strip conductor in described second test block;
First link and the second link, described first test block and described second test block are connected to the first testing weld pad and the second testing weld pad by described first link and described second link respectively.
2. test structure according to claim 1, is characterized in that, described first test block and described second test block all in pectination, all containing connecting line be set in parallel in some described strip conductor on described connecting line.
3. test structure according to claim 1 and 2, is characterized in that, described first test block and described second test block are arranged in upper and lower two parallel planes.
4. test structure according to claim 1 and 2, is characterized in that, described first test block and described second test block are positioned at same plane with described first testing weld pad and described second testing weld pad respectively.
5. test structure according to claim 1 and 2, is characterized in that, described first test block and described second test block are metallic test part.
6. test structure according to claim 2, is characterized in that, the width of described strip conductor is identical.
7. test structure according to claim 6, is characterized in that, the width of described strip conductor is n times of the basic width of setting, and wherein n is natural number.
8., based on a method of testing for the test structure one of claim 1-7 Suo Shu, comprising:
Step (a) applies scanning voltage on described first testing weld pad and described second testing weld pad;
Step (b) record applies Leakage Current during described scanning voltage;
Step (c) is analyzed according to the VBD performance of the change of described leakage current to described microchannels.
9. method of testing according to claim 8, is characterized in that, described in step (a), scanning voltage is less than or equal to 100V.
10. method of testing according to claim 8, is characterized in that, described method is used for detecting whole wafer map.
11. method of testings according to claim 8, is characterized in that, the voltage become rapidly when reaching greatly peak value when described Leakage Current in described step (c) is voltage breakdown.
12. method of testings according to claim 8, is characterized in that, described method is further comprising the steps of:
Change the width of strip conductor in the strip conductor array of described first test block and described second test block, test described microchannels, according to test result analysis, strip conductor width is on the impact of described microchannels VBD performance.
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| CN201310410805.9A CN104422870B (en) | 2013-09-10 | 2013-09-10 | A kind of test structure and test method of microchannels |
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