CN104103539A - Chip testing structure and testing method - Google Patents
Chip testing structure and testing method Download PDFInfo
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- CN104103539A CN104103539A CN201310130297.9A CN201310130297A CN104103539A CN 104103539 A CN104103539 A CN 104103539A CN 201310130297 A CN201310130297 A CN 201310130297A CN 104103539 A CN104103539 A CN 104103539A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- Power Engineering (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
The invention discloses a chip testing structure, which is used for testing reasons for chip crack. The chip testing structure comprises a first testing metal line and a second testing metal line which are parallel and insulated; the first testing metal line and the second testing metal line are made of the same metal layer. Each of the first testing metal line and the second testing metal line is provided with a beginning-end gasket and an ending-end gasket, and each forms a non-closed cycle round the protection cycle of the chip, and the first testing metal line is located outside the second testing metal line. The invention also provides a testing method for the chip testing structure. According to the chip testing structure, whether packaged chip crack is formed during the front manufacturing process or during the latter manufacturing process can be accurately estimated.
Description
Technical field
The present invention relates to reliability (Reliability) field in semiconductor manufacturing industry, particularly relate to a kind of chip testing structure and method of testing thereof.
Background technology
In field of semiconductor manufacture, for manufacturing process is monitored, ensure the reliability of semiconductor device, common way is in device, to form test structure (testkey), for the test of some key parameters.
The preparation process of semiconductor chip is divided into manufacture process He Hou road, front road encapsulation process, wherein, front road manufacture process is: on the wafer (wafer) of blank out, prepare multiple chips (chip) with repetitive structure, device architecture in each chip is around protected by guard ring (seal ring), guard ring is a kind of protection, passivation layer structure, and guard ring has scribe line (scrible line) outward; Rear road encapsulation process is: along predetermined scribe line, wafer is cut, form multiple separate chip, and then discrete chip is encapsulated.But, in encapsulation process, need to weld (bounding) to the pad on chip (pad), in the process of welding, chip is subject to the effect of stress, and the dielectric layer in chip can form slight crack, there will be chip split (chip crack) at the edge of chip, form the defect shown in Fig. 1 a and Fig. 1 b, thereby cause the performance of chip not good.
But, in the preparation process of actual semiconductor chip, in the process of front road manufacture, can form equally chip and split.But, chip testing structure and the chip detecting method of prior art, whether the edge that can only detect chip occurs that chip splits, can not distinguish chip and split and form in the process of Shi Qian road manufacture, or after form in the process of road manufacture.
Summary of the invention
The object of the invention is to, a kind of chip testing structure and method of testing thereof are provided, can accurate evaluation chip after encapsulation split and form in the process of Shi Qian road manufacture, or after form in the process of road manufacture.
For solving the problems of the technologies described above, the invention provides a kind of chip testing structure, the reason of splitting for test chip, comprising: the first test metal wire and second parallel and mutually insulated is tested metal wire; Described the first test metal wire and the second test metal wire are that same layer metal is made; Described the first test metal wire and the second test metal wire all have top pad and terminal pad, and form nonocclusive ring-type around the guard ring of chip separately, and described the first test metal wire is positioned at the outside of described the second test metal wire.
Further, in described chip testing structure, the spacing between described the first test metal wire and the second test metal wire is 2 microns～8 microns.
Further, in described chip testing structure, described chip testing structure also comprises the first weld pad that at least one and described the first test metal wire is electrically connected, and at least one and described second tests the second weld pad that metal wire is electrically connected.
Further, in described chip testing structure, on described the first test metal wire and the second test metal wire, all definition has test point, and the first test metal wire and the second test metal wire are divided into some detection segment by described test point; Described at least one the first weld pad is connected with the test point on the first test metal wire respectively, and described at least one the second weld pad is connected with the test point on the second test metal wire respectively.
Further, in described chip testing structure, the quantity of the test point on described the first test metal wire equates with the quantity of the test point on described the second test metal wire.
Further, in described chip testing structure, the each detection segment on described the first test metal wire is equal in length, and the each detection segment on described the second test metal wire is equal in length.
Further, in described chip testing structure, the spacing between described the first test metal wire and described guard ring is 2 microns～8 microns.
Further, in described chip testing structure, the arbitrary metal level in the interconnection layer that described the first test metal wire and the second test metal wire are described chip.
According to another side of the present invention, the present invention also provides a kind of chip detecting method that adopts described chip testing structure, comprising:
Detect the open circuit conditions of described the first test metal wire;
Detect the open circuit conditions of described the second test metal wire;
According to the open circuit conditions of described the first test metal wire and the second test metal wire, judge the reason that chip splits, exist and open circuit if only had on described the second test metal wire, when chip splits the encapsulation of Shi Youhou road, cause; Exist and open circuit if only had on described the first test metal wire, or all exist and open circuit on described the first test metal wire and the second test metal wire, when chip splits the manufacture of Shi Youqian road, cause.
Further, in described chip detecting method, comprising:
Making alive on the top pad of described the first test metal wire, measures the electric current of terminal pad of described the first test metal wire, to detect the open circuit conditions of described the first test metal wire;
Making alive on the top pad of described the second test metal wire, measures the electric current of terminal pad of described the first test metal wire, to detect the open circuit conditions of described the second test metal wire.
Further, in described chip detecting method, described chip testing structure also comprises the first weld pad that at least one and described the first test metal wire is electrically connected, and at least one and described second the second weld pad of being electrically connected of test metal wire, on described the first test metal wire and the second test metal wire, all definition has test point, and the first test metal wire and the second test metal wire are divided into some detection segment by described test point; Described each the first weld pad is connected with the test point on the first test metal wire respectively, and each the second weld pad is connected with the test point on the second test metal wire respectively, and described chip detecting method also comprises:
Exist and open circuit if only had on described the second test metal wire, detect the open circuit conditions of each detection segment of described the second test metal wire, to determine the concrete position of splitting;
Exist and open circuit if only had on described the first test metal wire, detect the open circuit conditions of each detection segment of described the second test metal wire, to determine the concrete position of splitting;
If all exist and open circuit on described the first test metal wire and the second test metal wire, detect the open circuit conditions of each detection segment of described the first test metal wire and the second test metal wire, to determine the concrete position of splitting.
Compared with prior art, chip testing structure provided by the invention and method of testing thereof have the following advantages:
1, chip testing structure provided by the invention and method of testing thereof, this chip testing structure has the first test metal wire and the second test metal wire of parallel and mutually insulated, both all have top pad and terminal pad, and form nonocclusive ring-type around the guard ring of chip separately, and described the first test metal wire is positioned at the outside of described the second test metal wire, compared with prior art, the position difference that the chip that chip testing structure of the present invention causes according to different reasons splits, judge, exist and open circuit if only had on described the second test metal wire, when chip splits the encapsulation of Shi Youhou road, cause, exist and open circuit if only had on described the first test metal wire, or all exist and open circuit on described the first test metal wire and the second test metal wire, when chip splits the manufacture of Shi Youqian road, cause, the method is simple, accurate, the reason that the chip after the encapsulation of energy accurate evaluation splits.
2, chip testing structure provided by the invention and method of testing thereof, this chip testing structure also comprises the first weld pad that at least one and described the first test metal wire is electrically connected, and at least one and described second the second weld pad of being electrically connected of test metal wire, when described the first test metal wire or the second test metal wire are while existing open circuit conditions, can whether exist and open circuit by detecting between each the first weld pad and the top pad of described the first test metal wire, or detect between each the second weld pad and the top pad of described the second test metal wire and whether exist and open circuit, to determine the concrete position of splitting, thereby the reason that facilitates further analysis chip to split.
Brief description of the drawings
Fig. 1 a-Fig. 1 b is the surface sweeping electron micrograph that chip of the prior art splits;
Fig. 2 is the schematic diagram of one embodiment of the invention chips test structure;
Fig. 3 is the flow chart of one embodiment of the invention chips method of testing;
Fig. 4 is the schematic diagram of further embodiment of this invention chips test structure.
Embodiment
Chip testing structure and the chip detecting method of prior art, whether the edge that can only detect chip occurs that chip splits, can not distinguish chip and split and form in the process of Shi Qian road manufacture, or after form in the process of road manufacture.Inventor is through finding the further investigation of prior art chips structure, because the pad on chip is positioned at the region, center of described chip, so in encapsulation process, to the pad on chip weld and the chip that forms to split be outwards to spread from the pad of described chip that cracking forms.Inventor further studies discovery, and the formation that the process chips of Qian road manufacture is split is often due to the problem of manufacturing process, and the problem of manufacturing process tends to reaction on whole chip.So the position range that the process chips of the position range Bi Qian road manufacture that the chip forming in encapsulation process splits is split is little, and the general region, center that only concentrates on more close described chip.
Because above-mentioned research, the present invention propose a kind of can accurate evaluation the split chip testing structure of reason of chip after encapsulation, described chip testing structure has the described first test metal wire of more close described chip edge and the described second test metal wire in more close chip center region, according to the open circuit conditions of described the first test metal wire and the second test metal wire, can judge easily and accurately the reason that chip splits.
Below in conjunction with schematic diagram, chip testing structure of the present invention and method of testing thereof are described in more detail, the preferred embodiments of the present invention are wherein represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.They in the following description, are not described in detail known function and structure, because can make the present invention chaotic due to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example, according to about system or about the restriction of business, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but be only routine work to those skilled in the art.
In the following passage, with way of example, the present invention is more specifically described with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the object of the aid illustration embodiment of the present invention lucidly.
Core concept of the present invention is; a kind of chip testing structure and method of testing thereof are provided; this chip testing structure has the first test metal wire and the second test metal wire of parallel and mutually insulated; and form nonocclusive ring-type around the guard ring of chip separately; and described the first test metal wire is positioned at the outside of described the second test metal wire; the position difference that the chip that chip testing structure of the present invention causes according to different reasons splits; judge; the method is simple, accurate, the reason that the chip after the encapsulation of energy accurate evaluation splits.
In conjunction with above-mentioned core concept, the invention provides a kind of chip testing structure, the reason of splitting for test chip, comprising: the first test metal wire and second parallel and mutually insulated is tested metal wire; Described the first test metal wire and the second test metal wire are same layer metal; Both all have top pad and terminal pad, and form nonocclusive ring-type around the guard ring of chip separately, and described the first test metal wire is positioned at the outside of described the second test metal wire.
In conjunction with said chip test structure, the present invention also provides a kind of method of testing, comprises the following steps:
Step S01, detects the described first open circuit conditions of testing metal wire;
Step S02, detects the described second open circuit conditions of testing metal wire;
Step S03, according to the open circuit conditions of described the first test metal wire and the second test metal wire, judges the reason that chip splits.
Illustrate chip testing structure of the present invention and method of testing thereof below in conjunction with Fig. 2 and Fig. 3, Fig. 2 is the schematic diagram of one embodiment of the invention chips test structure, and Fig. 3 is the flow chart of one embodiment of the invention chips method of testing.
As shown in Figure 2, described chip testing structure comprises the first test metal wire 120 and the second test metal wire 130 of parallel and mutually insulated, wherein, described the first test metal wire 120 and the second test metal wire 130 are same layer metal, thus the error of avoiding different layers metal to cause.And, described the first test metal wire 120 and the second test metal wire 130 all have top pad and terminal pad separately, described the first test metal wire 120 has top pad 121 and terminal pad 122, and described the second test metal wire 130 has top pad 131 and terminal pad 132.Described the first test metal wire 120 and the second test metal wire 130 also form nonocclusive ring-type around the guard ring 110 of chip 100 separately, and in the present embodiment, described guard ring 110 is square, so nonocclusive ring-type is Q-RING.Described the first test metal wire 120 is positioned at the outside of described the second test metal wire 130; the more close described guard ring 110 of described the first test metal wire 120; the welding gasket region (welding gasket does not specifically illustrate in the drawings, and this is the ordinary skill in the art) at described the second test more close described chip of metal wire 130 100 centers.The position range that the process chips of the position range Bi Qian road manufacture of splitting due to the chip forming in encapsulation process is split is little, and generally only concentrate on the region, center of more close described chip, so, can be according to the open circuit conditions of described the first test metal wire 120 and the second test metal wire 130, judge the position that chip splits, thereby judge the reason that chip splits.
In the present embodiment, spacing L between described the first test metal wire 120 and the second test metal wire 130 is unsuitable excessive, when spacing L is excessive, be not easy test structure to control, spacing L is also unsuitable too small, when spacing L is too small, described the first test metal wire 120 and the second test metal wire 130 short circuits simultaneously, cause and cannot distinguish the position that chip splits.Preferably, described the first test metal wire 120 is 2 microns～8 microns with the second spacing L testing between metal wire 130, preferably 3 microns, 4 microns, 5 microns, 6 microns, can control well the accuracy of test.But the spacing L between described the first test metal wire 120 and the second test metal wire 130 is not limited to 2 microns～8 microns, and the concrete size of spacing L is decided by the device architecture of chip 100 and the size of size.For example, in the time that the size of chip 100 is very large, while being of a size of 1 decimeter as chip 100, spacing L can be set to 10 microns.
In addition, in the present embodiment, described chip testing structure also comprises first weld pad 123 being electrically connected with described the first test metal wire 120, and second weld pad 133 being electrically connected with described the second test metal wire 130.On described the first test metal wire 120, definition has test point a, on described the second test metal wire 130, definition has test point b, the first test metal wire 120 is divided into two detection segment by described test point a, and the second test metal wire 130 is divided into two detection segment by described test point b.The first weld pad 123 being electrically connected with described the first test metal wire 120 is connected with the test point a on the first test metal wire 120, and the second weld pad 133 being electrically connected with described the second test metal wire 130 is connected with the test point b on the second test metal wire 130.Wherein, can be by being connected with the metal wire of layer with the first test metal wire 120 between the first weld pad 123 and test point a, can be by being connected with the metal wire of the first test metal wire 120 different layers between the second weld pad 133 and test point b, this common practise that is this area, therefore not to repeat here.In the time there is open circuit conditions in described the first test metal wire 120, can whether exist and open circuit by detecting between the first weld pad 123 and the top pad 121 of described the first test metal wire 120, in the time there is open circuit conditions in described the second test metal wire 130, detect between the second weld pad 133 and the top pad 131 of described the second test metal wire 120 and whether exist and open circuit, to determine the concrete position of splitting, thus the reason that facilitates further analysis chip to split.
In the present embodiment; spacing W between described the first test metal wire 120 and described guard ring 110 is preferably 2 microns～8 microns; can reach good testing result; but it is 2 microns～8 microns that the spacing W between described the first test metal wire 120 and described guard ring 110 is not limited to, specifically according to the structures shape of device in the size of chip 100 and chip 100.
Illustrate the method for testing of the present embodiment chips test structure below in conjunction with Fig. 3.
First, carry out step S01, detect the open circuit conditions of described the first test metal wire 120.In the present embodiment, making alive on the top pad 121 of described the first test metal wire 120, measure the electric current of the terminal pad 122 of described the first test metal wire 120, to detect the open circuit conditions of described the first test metal wire 120, detection electric current is the ordinary skill in the art, and therefore not to repeat here.But can also, by detecting the resistance of the top pad 121 of described the first test metal wire 120 and the terminal pad 122 of described the first test metal wire 120, detect the open circuit conditions of described the first test metal wire 120.
Then, carry out step S02, detect the open circuit conditions of described the second test metal wire 130.In the present embodiment, making alive on the top pad 131 of described the second test metal wire 130, measure the electric current of the terminal pad 132 of described the second test metal wire 130, to detect the open circuit conditions of described the second test metal wire 130, detection electric current is the ordinary skill in the art, and therefore not to repeat here.But can also, by detecting the resistance of the top pad 131 of described the second test metal wire 130 and the terminal pad 132 of described the second test metal wire 130, detect the open circuit conditions of described the second test metal wire 130.
Finally, carry out step S03, according to the open circuit conditions of described the first test metal wire 120 and the second test metal wire 130, judge the reason that chip splits, exist and open circuit if only had on described the second test metal wire 130, when chip splits the encapsulation of Shi Youhou road, cause; Exist and open circuit if only had on described the first test metal wire 120, or all exist and open circuit on described the first test metal wire 120 and the second test metal wire 130, when chip splits the manufacture of Shi Youqian road, cause.
In the present embodiment, exist and open circuit if only had on described the second test metal wire 130, detect the open circuit conditions of each detection segment of described the second test metal wire 130, to determine the concrete position of splitting, wherein, the detection method of described second test metal wire 130 open circuit conditions of detection method reference of the open circuit conditions to each detection segment, this conventional method that is this area, therefore not to repeat here; Exist and open circuit if only had on described the first test metal wire 120, detect the open circuit conditions of each detection segment of described the first test metal wire 120, to determine the concrete position of splitting; If all exist and open circuit on described the first test metal wire 120 and the second test metal wire 130, detect the open circuit conditions of each detection segment of described the first test metal wire 120 and the second test metal wire 130, to determine the concrete position of splitting.
Wherein, described the first test metal wire 120 and second arbitrary metal level of testing in the interconnection layer that metal wire 130 is described chip 100.; in the process of test; can described the first test metal wire 120 and the second test metal wire 130 be all set to every one deck, test respectively the described first test metal wire 120 of every one deck and the open circuit conditions of the second test metal wire 130, with the reason that facilitates analysis chip to split.
Table 1
Table 1 is the test result statistical form in one embodiment of the invention.In table 1, test respectively two samples, each sample has all been tested 5 interconnecting metal layers: the first metal layer M1, the second metal level M2, the 3rd metal level M3, the 4th metal level M4, top layer metallic layer TM.As can be seen from Table 1, there is not open circuit conditions in described the first test metal wire 120 and the second test metal wire 130 in sample 2, so do not have chip to split in sample 2.There is not open circuit conditions in described the first test metal wire 120 in sample 1, open circuit conditions appears in described the second test metal wire 130, but terminal pad 132 does not detect electric current, and the second weld pad 133 detects electric current.So, in sample 1, occurring that chip splits, chip causes while splitting due to the encapsulation of rear road, and the position that chip splits occurs on described the second test metal wire 130 between test point b and terminal pad 132; And described the second test metal wire 130 of M1 and M2 is good, so chip splits may be relevant with M3 and later preparation thereof.
The present invention is not limited to above embodiment, for example, the quantity of the test point on the quantity of the test point on described the first test metal wire 120 and described the second test metal wire 130 can also be greater than one, (equivalent in meaning with label identical in Fig. 2 at Fig. 4) as shown in Figure 4, the quantity of the test point on the quantity of the test point on described the first test metal wire 120 and described the second test metal wire 130 is 3, test point a1 on described the first test metal wire 120, described the first test metal wire 120 is divided into 3 detection segment by test point a2 and test point a3, test point b1 on described the second test metal wire 130, described the second test metal wire 130 is divided into 3 detection segment by test point b2 and test point b3, when described the first test metal wire 120 or/and described the second test metal wire 130 while there is short circuit, can test metal wire 120 or/and the short-circuit conditions of each detection segment of described the second test metal wire 130 detects to described first, detection method is with reference to the detection to described the first test metal wire 120 and described the second test metal wire 130, therefore not to repeat here.In addition, the quantity of the test point on described the first test metal wire 120 equates with the quantity of the test point on described the second test metal wire 130, each detection segment on described the first test metal 120 is equal in length, each detection segment on described the second test metal wire 130 is equal in length, is conducive to accurately test and assess.
In sum; the invention provides a kind of chip testing structure and method of testing thereof; this chip testing structure has the first test metal wire and the second test metal wire of parallel and mutually insulated; and form nonocclusive ring-type around the guard ring of chip separately; and described the first test metal wire is positioned at the outside of described the second test metal wire; the position difference that the chip that chip testing structure of the present invention causes according to different reasons splits; judge; the method is simple, accurate, the reason that the chip after the encapsulation of energy accurate evaluation splits.Compared with prior art, the bias voltage temperature instability test circuit that contains provided by the invention has the following advantages:
1, chip testing structure provided by the invention and method of testing thereof, this chip testing structure has the first test metal wire and the second test metal wire of parallel and mutually insulated, both all have top pad and terminal pad, and form nonocclusive ring-type around the guard ring of chip separately, and described the first test metal wire is positioned at the outside of described the second test metal wire, compared with prior art, the position difference that the chip that chip testing structure of the present invention causes according to different reasons splits, judge, exist and open circuit if only had on described the second test metal wire, when chip splits the encapsulation of Shi Youhou road, cause, exist and open circuit if only had on described the first test metal wire, or all exist and open circuit on described the first test metal wire and the second test metal wire, when chip splits the manufacture of Shi Youqian road, cause, the method is simple, accurate, the reason that the chip after the encapsulation of energy accurate evaluation splits.
2, chip testing structure provided by the invention and method of testing thereof, this chip testing structure also comprises the first weld pad that at least one and described the first test metal wire is electrically connected, and at least one and described second the second weld pad of being electrically connected of test metal wire, when described the first test metal wire or the second test metal wire are while existing open circuit conditions, can whether exist and open circuit by detecting between each the first weld pad and the top pad of described the first test metal wire, or detect between each the second weld pad and the top pad of described the second test metal wire and whether exist and open circuit, to determine the concrete position of splitting, thereby the reason that facilitates further analysis chip to split.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (11)
1. a chip testing structure, the reason of splitting for test chip, comprising: the first test metal wire and second parallel and mutually insulated is tested metal wire; Described the first test metal wire and the second test metal wire are that same layer metal is made; Described the first test metal wire and the second test metal wire all have top pad and terminal pad, and form nonocclusive ring-type around the guard ring of chip separately, and described the first test metal wire is positioned at the outside of described the second test metal wire.
2. chip testing structure as claimed in claim 1, is characterized in that, the spacing between described the first test metal wire and the second test metal wire is 2 microns～8 microns.
3. the chip testing structure as described in any one in claim 1-2, it is characterized in that, described chip testing structure also comprises the first weld pad that at least one and described the first test metal wire is electrically connected, and at least one and described second tests the second weld pad that metal wire is electrically connected.
4. chip testing structure as claimed in claim 3, is characterized in that, on described the first test metal wire and the second test metal wire, all definition has test point, and the first test metal wire and the second test metal wire are divided into some detection segment by described test point; Described at least one the first weld pad is connected with the test point on the first test metal wire respectively, and described at least one the second weld pad is connected with the test point on the second test metal wire respectively.
5. chip testing structure as claimed in claim 4, is characterized in that, the quantity of the test point on described the first test metal wire equates with the quantity of the test point on described the second test metal wire.
6. chip testing structure as claimed in claim 5, is characterized in that, the each detection segment on described the first test metal wire is equal in length, and the each detection segment on described the second test metal wire is equal in length.
7. chip testing structure as claimed in claim 1, is characterized in that, the spacing between described the first test metal wire and described guard ring is 2 microns～8 microns.
8. chip testing structure as claimed in claim 1, is characterized in that, the arbitrary metal level in the interconnection layer that described the first test metal wire and the second test metal wire are described chip.
9. a chip detecting method that adopts the chip testing structure described in any one in claim 1-2, comprising:
Detect the open circuit conditions of described the first test metal wire;
Detect the open circuit conditions of described the second test metal wire;
According to the open circuit conditions of described the first test metal wire and the second test metal wire, judge the reason that chip splits, exist and open circuit if only had on described the second test metal wire, when chip splits the encapsulation of Shi Youhou road, cause; Exist and open circuit if only had on described the first test metal wire, or all exist and open circuit on described the first test metal wire and the second test metal wire, when chip splits the manufacture of Shi Youqian road, cause.
10. chip detecting method as claimed in claim 9, is characterized in that, described chip detecting method comprises:
Making alive on the top pad of described the first test metal wire, measures the electric current of terminal pad of described the first test metal wire, to detect the open circuit conditions of described the first test metal wire;
Making alive on the top pad of described the second test metal wire, measures the electric current of terminal pad of described the second test metal wire, to detect the open circuit conditions of described the second test metal wire.
11. chip detecting methods as claimed in claim 9, it is characterized in that, described chip testing structure also comprises the first weld pad that at least one and described the first test metal wire is electrically connected, and at least one and described second the second weld pad of being electrically connected of test metal wire, on described the first test metal wire and the second test metal wire, all definition has test point, and the first test metal wire and the second test metal wire are divided into some detection segment by described test point; Described each the first weld pad is connected with the test point on the first test metal wire respectively, and each the second weld pad is connected with the test point on the second test metal wire respectively, and described chip detecting method also comprises:
Exist and open circuit if only had on described the second test metal wire, detect the open circuit conditions of each detection segment of described the second test metal wire, to determine the concrete position of splitting;
Exist and open circuit if only had on described the first test metal wire, detect the open circuit conditions of each detection segment of described the first test metal wire, to determine the concrete position of splitting;
If all exist and open circuit on described the first test metal wire and the second test metal wire, detect the open circuit conditions of each detection segment of described the first test metal wire and the second test metal wire, to determine the concrete position of splitting.
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| CN201310130297.9A CN104103539A (en) | 2013-04-15 | 2013-04-15 | Chip testing structure and testing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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| CN107728042A (en) * | 2017-11-13 | 2018-02-23 | 睿力集成电路有限公司 | Integrated circuit and its method of testing with protection test |
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