CN102882814B - Parameterized and modularized multi-channel digital down-conversion design platform and parameterized and modularized multi-channel digital down-conversion design method - Google Patents

Abstract

The invention provides a parameterized and modularized multi-channel digital down-conversion design platform and a parameterized and modularized multi-channel digital down-conversion design method, belonging to the digital signal processing field. A design platform is a parameterized and modularized multi-channel digital down-conversion design platform, which selects M channels from analog input signals of N channels to perform analog-digital conversion and performs the digital down-conversion treatment to output M paths of baseband digital signals. The invention is also a design method, wherein the design process is as follows: an input analog signal gating performs the analog-digital conversion and then the orthorhombic mixing; order H of a filter and a branch extracting multiple D area analyzed in real time; the signals after performing the orthorhombic mixing are respectively delayed, extracted and buffered; meanwhile, the selected filter coefficients are extracted and rearranged, so that the coefficient vector of every branch is obtained and buffered; the buffered data and coefficient are multiplied and added, and the results are periodically extracted and summed, then the output of the M path is obtained. The parameterized and modularized multi-channel digital down-conversion design platform has the advantages of usability, generality and flexibility; the platform is used for transforming multiple intermediate frequency sampling signals to a baseband signal; and meanwhile, the purpose of reducing the data speed rate is achieved.

Description

Parameterized module multi-channel digital down-conversion design platform and method

Technical field

The present invention relates to digital signal processing technique field, be mainly concerned with the specific implementation of multiphase filter structure, specifically parameterized module multi-channel digital down-conversion design platform and a method, can realize the Digital Down Convert design of parametrization, modularization, multichannel, variable filter exponent number.

Background technology

Cost is high, rate of reusing is low and the feature of poor universality to utilize application-specific integrated circuit (ASIC) to have to the technology realizing Digital Signal Processing.Along with the fast development of signal processing technology, software radio becomes the key technology in current signal transacting field.The basic thought of software radio be with general, standard, a modular hardware platform for relying on, realize various function by software programming.Therefore the function of software implementation decreases the hardware circuit design of function singleness, very flexible, especially decreases simulation link, has given full play to the digitized advantage of signal transacting.Along with the raising of sampling rate, major issue is exactly that streaming rate after sampling is very high, causes follow-up conversion speed not catch up with; If data throughput is too high, be difficult to requirement of real time, so carry out reduction of speed process to the data flow after A/D just seem most important.Feasible way adopts a digital down-conversion technology exactly, high-speed data-flow is become low rate data streams in can processing in real time, then does follow-up process to low speed data.Digital down-conversion technology is one of core technology of software radio reception, and general digital down converter is also applied to various Wireless Telecom Equipment and the field such as radar and information home appliances more and more widely, has importance extremely.

Digital quadrature down conversion technology is that if sampling signal is transformed to digital baseband, mainly contains two kinds of implementation methods: the Orthogonal Transformation Method based on digital mixing and the digital quadrature transformation method based on multiphase filter structure.

If sampling output signal is multiplied with the two-way orthogonal signalling that local oscillator produces to carry out digital mixing by respectively, and by the signal after mixing through low pass filter, filtering high fdrequency component, obtains required base band quadrature simple two-way signal.The shortcoming of this down conversion method is for wideband IF signal, needs higher sample rate, due to the restriction of operating frequency, is difficult to design the low pass filter of satisfying the demand.

The digital quadrature transformation method based on multiphase filter structure utilizes bandpass sample theory, according to carrier frequency and signal bandwidth determination if sampling frequency, chooses the sequence of parity after sampling respectively, by correcting filter, realizes exporting two-way orthogonal signalling.According to heterogeneous structure and the equivalent transformation principle of FIR filter, low-pass filtering and extraction can be carried out simultaneously, greatly reduce the requirement to filter process speed.The shortcoming of this down conversion method is the exponent number of branching filter and the data rate after extracting is fixing, and when being used in different systems, change comparatively large, flexibility is poor, and versatility is not strong.

Summary of the invention

The object of the invention is to overcome the shortcoming such as above-mentioned digital down-conversion technology very flexible, versatility be not strong, Digital Down Convert design platform and the method for a kind of modularization, parametrization, multichannel, variable filter exponent number are provided.The present invention can the coefficient of real-time reception configuration parameter and filter, and the method adopting submodule to build realizes Digital Down Convert, has the features such as ease for use, versatility and flexibility.

The present invention is a kind of parameterized module multi-channel digital down-conversion design platform, include analog-to-digital conversion module and N channel Digital Down Converter Module, N road analog signal is given N number of Digital Down Converter Module through the digital signal that analog-to-digital conversion module exports and is done Digital Down Convert process, and exports N road baseband digital signal, parameterized module multi-channel digital down-conversion design platform of the present invention also includes N channel analog signal Shaping Module, parameter receiver module, input channel gating module, N channel parameters input port, N road analog signal inputs to N channel analog signal Shaping Module, export N road through shaping analog signal and give analog-to-digital conversion module, parameter is given parameter receiver module by data-interface simultaneously, the control signal of passage gating is given input channel gating module by parameter receiver module, input channel gating module exports the enable control signal of N number of passage to analog-to-digital conversion module, under the control of the enable control signal of N number of passage, analog-to-digital conversion module does analog-to-digital conversion to the M selected (M≤N) road analog signal, export M railway digital signal to M Digital Down Converter Module, the channel parameters on M road is given the parameters input port of M Digital Down Converter Module by parameter receiver module respectively simultaneously, M railway digital down-converted is done under state modulator, and export M road baseband digital signal, every roadbed band signal is by I, the digital signal formation that Q two-way is orthogonal, described Digital Down Converter Module is the Digital Down Converter Module of parameterized module.

Digital down-conversion technology is one of core technology of software radio reception, simultaneously digital down-conversion technology is also applied to various Wireless Telecom Equipment and the field such as radar and information home appliances more and more widely, but existing digital down-conversion technology very flexible, versatility be not strong etc., and shortcoming makes it be very limited in the application.In order to make digital down-conversion technology be more widely used, the present invention, on the basis of existing digital down-conversion technology, adopts parametrization and modular thought, makes Digital Down Convert as a module, realize parametric control to this module.For realizing goal of the invention, the parameterized module Digital Down Convert design platform of variable-data-rate provided by the invention, variable filter exponent number, realize the Digital Down Convert of N (N >=1) individual channel signal, the Digital Down Converter Module of each passage independently uses by parameter configuration simultaneously.

The Digital Down Convert process of the present invention to the M road signal selected is all realize based on the design philosophy of above-mentioned parameter Modularized digital down-conversion, by the parameters input to M Digital Down Converter Module, realize the Digital Down Convert process of M road signal under respective state modulator, export M road baseband digital signal, wherein every roadbed band signal comprises the orthogonal signal of I, Q two-way.

Realization of the present invention is also: the Digital Down Converter Module of parameterized module, and the basis of original quadrature downconvert module, data delay cache module, filter coefficient module and multiply accumulating module also increases parameters input port, filter order and data rate control module, branching filter coefficient module.Filter order control signal and rate controlled signal are given filter order and data rate control module by parameters input port simultaneously, the while of filter order and data rate control module, output filter exponent number and branch's extracting multiple signal are to branching filter coefficient module, and branch's extracting multiple signal are delivered to the input of data delay cache module; Feedback command information channel and filter factor sendaisle is provided with between branching filter coefficient module and parameters input port, select the branching filter coefficient of process according to parameter, each branching filter coefficient is given multiply accumulating module by branching filter coefficient module; The data of quadrature downconvert give data delay cache module simultaneously, under the control of branch's extracting multiple signal, data delay cache module carries out the delay under state modulator to the data of mixing and extracts process, does buffer memory, then export to multiply accumulating module to the data after extracting; Multiply accumulating module completes the multiply accumulating of data and filter coefficient and exports the baseband digital signal of Digital Down Converter Module.

The realization of Digital Down Converter Module builds realization by submodule, and each submodule is connected by interconnecting signal each other.The submodule of Digital Down Converter Module has: quadrature downconvert module, filter order and data rate control module, branching filter coefficient module, data delay cache module, multiply accumulating module.The present invention simultaneously arranges several data interface, can facilitate and realize interactive type communication between external equipment, and the design of data-interface simultaneously also embodies the present invention's extensibility on this basis, and digital down-conversion technology is got up more flexibly with simple in utilization.

Realization of the present invention is also: the branching filter coefficient module in parameterized module Digital Down Converter Module is also parametric control.Be provided with feedback command information channel and filter factor sendaisle between branching filter coefficient module and parameters input port, according to filter order and branch's extracting multiple signal, filter coefficient selected.If inner preset filter coefficient can meet the demand of design, choice for use is preset at the filter coefficient in buffer area A; If the filter order determined does not mate with preset filter order, then send feedback signal to parameters input port, and export to data-interface through parameter receiver module, require that data-interface sends the filter coefficient of corresponding exponent number, and by real-time reception to filter coefficient be buffered in the buffer area B of branching filter coefficient module, give the multiply accumulating module of each branch.

The present invention is not only a kind of method for designing of a kind of parameterized module multi-channel digital down-conversion design platform or parameterized module multi-channel digital down-conversion, and as shown in Figure 3, design process comprises its design cycle:

A, N channel and multi-channel analog signal Shaping Module carry out shaping to N road analog signal to be processed, export the analog signal after the shaping of N road and send to analog-to-digital conversion module.

B, parameter receiver module receive data-interface and mainly comprise Ethernet interface, PCI mouth, serial ports, parameter that USB port is sent here and required filter coefficient, from Digital Down Converter Module, feedback information are sent to data-interface simultaneously, carry out interactive process.

C, input channel gating module export the enable control signal of N number of passage, and produce the enable control signal of N number of passage according to the passage gate control signal that parameter receiver module is sent here, this enable control signal is as the input signal of following analog-to-digital conversion module.

D, analog-to-digital conversion module comprise N number of analog to digital converter, and under the control of the N number of enable control signal that analog-to-digital conversion module provides in input channel gating module, the analog signal selecting the shaping of M road is carried out analog-to-digital conversion and exports M road independently digital signal.

Said process mainly realizes gating and analog-to-digital conversion to inputting analog signal channel, and the present invention, by real-time reception parameter, parses the enable control signal of passage, selects and needs passage to be processed carry out follow-up Digital Down Convert process.

E, parameterized digital down conversion module comprise M digital down-converted module, wherein each Digital Down Converter Module realizes parametrization by input parameter arrange and control, and the specific implementation process of Digital Down Converter Module comprises successively: quadrature downconvert, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating; The baseband digital signal after M railway digital down-converted is obtained after Digital Down Converter Module.

Realization of the present invention is also: the parameter receiver module in above process B, the reception of its parameter, formed and be allocated as follows shown in:

The order that B1, reception data-interface (data-interface can be Ethernet interface, PCI mouth, serial ports, USB port etc.) are sent here and corresponding filter coefficient, send to data-interface by each Digital Down Converter Module feedack simultaneously.

B2, the order received according to the parsing of concrete communication protocol, obtain filter order control signal L and the rate controlled signal K of each passage, export to the parameters input port of the Digital Down Converter Module of respective channel, realize the parametric control to each railway digital down-conversion.

B3, receiving filter coefficient, and filter coefficient is carried out buffer memory, then export to the branching filter coefficient module of respective channel.

Realization of the present invention is also: the generation of the enable control signal of input channel gating module in above process C, and its production method is:

The control signal of the passage gating that C1, input channel gating module receiving parameter receiver module are sent here, control signal is resolved according to concrete interface communications protocol, obtain the enable control signal Ctrl [N-1:0] of N number of passage, the initialization value of Ctrl [N-1:0] is set to zero, and is defined as effectively high.

C2, wherein Ctrl [0] are the enable control of analog-to-digital conversion of passage 1, and Ctrl [1] is the enable control of analog-to-digital conversion of passage 2 ..., Ctrl [N-1] is the enable control of analog-to-digital conversion of passage N.

C3, when Ctrl [0] is for time high, represent that the analog signal of the enable i.e. selector channel 1 of passage 1 carries out analog-to-digital conversion, when Ctrl [0] is for time low, represent that the analog signal of the not enable i.e. passage 1 of passage 1 does not carry out analog-to-digital conversion; When Ctrl [1] is for time high, represent that passage 2 is enable, when Ctrl [1] is for time low, represent that passage 2 is not enable ..., the rest may be inferred respectively with M passage required for the M in N number of enable control signal effective signal behavior.

Realization of the present invention is also: parameterized digital down conversion module realizes Digital Down Convert process, Digital Down Converter Module all can be used to carry out parametric control by input parameter realize Digital Down Convert to the Digital Down Convert process on each road of the M railway digital signal selected.The design process of Digital Down Converter Module comprises: quadrature downconvert, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating; Below each process is described in detail:

The digital signal that analog-to-digital conversion exports by E1, quadrature downconvert and orthogonal local oscillation sequence with be multiplied, sample rate f _swith signal intermediate frequency f ₀meet certain relation, make the local oscillator sequence be multiplied with meet:

$\cos \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{1,0,-\mathrm{1,0},\·\·\·\},$ $\sin \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{0,1,0},-1,\·\·\·\},$ So first 2 times of extractions will be carried out to sampled signal, obtain signal X (2n); After sampled signal being postponed a clock cycle simultaneously, carry out 2 times of extractions again and obtain signal X (2n+1), signal X (2n+1) is delayed a clock cycle than signal X (2n), d type flip flop latch signal X (2n) is adopted to postpone a clock cycle by X (2n), respectively 1 and-1 is alternately multiplied with X (2n+1) to the sequence X (2n) after extracting alignment, obtains orthogonal I (n), Q (n) two paths of signals.

E2, according to input parameter L and K, determine filter order H and branch extracting multiple D.The exponent number of the conventional low-pass filter coefficients pre-set has 32 rank, 64 rank, 128 rank, 144 rank, be pre-stored in buffer area A, can for the filter coefficient selecting this preset when inputting without external filter coefficient, make this invention not exclusively depend on the filter coefficient of outside input, functionally there is independence; If inner preset filter coefficient meets the demand of design, filter coefficient that can be preset in choice for use buffer area A, if the filter order H determined does not mate with preset filter order, data-interface can be exported to parameter receiver module feedback signal Cmd, require that data-interface sends the filter coefficient on H rank, and by real-time reception to H rank filter coefficient be buffered in the buffer area B of branching filter coefficient module.

E3, carrying out control data postpone according to the branch extracting multiple D obtained in above process E2, is f in frequency _sunder the clock control of/2,0 carried out respectively to the orthogonal I (n) produced in E1, Q (n) two paths of signals, 1,2 ..., a D-1 clock cycle delay, I (n), Q (n) two-way respectively resolve into parallel D data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD, now the data rate of each branch road is the same, data rate and I (n) in E1, Q (n) two paths of data speed are identical, are f _s/ 2.

E4, carrying out control data extract according to the branch extracting multiple D obtained in above process E2, is f in frequency _sunder the clock control of/2, to in E3 postpone after data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD carries out D respectively and doubly extracts namely every D-1 data pick-up one number, obtain like this extract after data branch road be Ic1, Ic2 ..., IcD, Qc1, Qc2 ..., QcD, now the data rate of each branch is 1/D times of data rate in E3, is f _s/ 2D.

E5, be f in frequency _sunder the clock control of/2D, by the data branch road Ic1 after the extraction that obtains in E4, Ic2 ..., IcD, Qc1, Qc2 ..., QcD write respectively respective data buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., in RAMDQD.

E6, according to the filter order H obtained in above process E2 and branch extracting multiple D, switching signal Select is produced by data selector, choose optimum filter coefficient, choose the filter coefficient in buffer area A when Select is ' 0 ', choose the filter coefficient in the B of buffering area when Select is ' 1 '.

E7, control the generation of branching filter coefficient according to the branch extracting multiple D obtained in above process E2, the coefficient C of filter first will chosen in above process E6 ₁, C ₂, C ₃..., C _hcarry out odd even extraction, the filter coefficient C of even number ₂, C ₄..., C _hcomposition I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C _h-1composition Q path filter coefficient, carries out D to I path filter coefficient and doubly extracts, obtain the filter coefficient C of I1 branch from first coefficient ₂, , from second coefficient, carry out D to I path filter coefficient doubly to extract, obtain the filter coefficient C of I2 branch ₄, , the rest may be inferred to the filter coefficient C of ID branch _2D, , i path filter coefficient resolves into the filter coefficient vector of D branch altogether, finally the filter coefficient vector inverted sequence of each branch is buffered in respective coefficient buffering area RAMCI1, RAMCI2 ..., in RAMCID, the coefficient as buffer memory in RAMCI1 is followed successively by by address order from small to large , c ₂, the coefficient in like manner in other buffering area known, the generation of Q road branching filter coefficient is identical with the treatment step on I road.

E8, branch's filtering are actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 2D branch needs 2D multiply accumulating module, in frequency is clock control under, by above process E5 buffer area RAMDI1, RAMDI2, RAMDID, RAMDQ1, RAMDQ2, the I of buffer memory in RAMDQD, the data reading of each branch of Q two-way, simultaneously by above process E7 buffer area RAMCI1, RAMCI2, RAMCID, RAMCQ1, RAMCQ2, the I of buffer memory in RAMCQD, the filter coefficient of each branch of Q two-way reads, the data read in RAMDI1 and RAMCI1 and coefficient give the input of a multiply accumulating module respectively, carry out the filtering of I1 branch, the filtering of other each branch is identical, I, the filter result of each branch of Q two-way is doutI1, doutI2, doutID, doutQ1, doutQ2, doutQD, now the data rate of each branch is f _s/ 2D.

E9, be f in frequency _sunder the clock control of/2D, by D, I road in E8 branch filter result doutI1, doutI2 ..., doutID is added, the I road result obtaining Digital Down Convert exports doutI; By D, Q road branch filter result doutQ1, doutQ2 ..., doutQD is added, the Q road result obtaining Digital Down Convert exports doutQ.So far, the process of parameterized module Digital Down Convert is completed.

Through the process of process A ~ F, by the control of external parameter, the analog signal of M passage of actual needs can be selected, the analog signal of M passage is exported after analog-to-digital conversion the digital signal of M passage, the Digital Down Converter Module of each passage receives respective parameter, the digital signal of reception is carried out Digital Down Convert process, exports M road baseband digital signal.Whole method for designing achieves and multichannel analog intermediate frequency signal is converted to multichannel baseband digital signal, and reaches the requirement reducing data rate.

To sum up, the inventive method makes full use of the design that parametrization and modularization idea realize Digital Down Convert, and compared with prior art, tool of the present invention has the following advantages:

1, the present invention is based on changeable channel Digital Signal Processing, by input channel gating module, the enable control signal of passage is set, select and need channel signal to be processed to carry out subsequent treatment, and do not need the channel signal processed not process.Enable setting like this has the advantage of changeable channel, can reach the object of effectively saving power consumption simultaneously.

2, the present invention is based on parametrization, modular thinking, each railway digital down conversion module, by real-time reception parameter separately, can realize the parametrization independent process to every railway digital signal neatly; Meanwhile, in certain scope, the parameter of being given by outside is to control the change of filter order and data rate, and make it be applicable to the system that need not require, range of application is broader.There is the integrality of parameterized moduleization design, flexibility and ease for use.

3, data-interface of the present invention can be Ethernet interface, PCI mouth, serial ports, USB port etc., data-interface sends order and corresponding filter coefficient to parameter receiver module, simultaneously also can by the information feed back of Digital Down Converter Module of the present invention to data-interface, carry out interactive process, the selection of this multiple interfaces and interactive process, add the simplicity of system, ease for use and versatility.

4, the present invention can the filter coefficient that sends of real-time reception data-interface, also can select inner preset filter coefficient, achieve filter factor and move variable, move back the generalization that can keep and control, have very strong versatility and practicality.

Accompanying drawing explanation

Fig. 1 is the modularization block diagram of design platform of the present invention, is also the formation block diagram of method for designing of the present invention;

Fig. 2 is the formation block diagram of single passage Digital Down Converter Module in M passage Digital Down Converter Module of the present invention;

Fig. 3 is the flow chart of single passage Digital Down Converter Module;

Fig. 4 is the flow chart of the quadrature downconvert module of single passage Digital Down Converter Module;

Fig. 5 is the filter order of single passage Digital Down Converter Module and the flow chart of data rate control module;

Fig. 6 is the symmetric form FIR filter block diagram of single passage Digital Down Converter Module;

Fig. 7 is the formation block diagram of the I circuit-switched data delay buffer module of single passage Digital Down Converter Module:

Fig. 8 is the formation block diagram of the branching filter coefficient module of single passage Digital Down Converter Module;

Fig. 9 is the formation block diagram of the multiply accumulating module of the I road branch filtering of single passage Digital Down Converter Module;

Figure 10 is the time-sharing multiplex sequential chart of the multiply accumulating module of the I road branch filtering of single passage Digital Down Converter Module.

Embodiment

Following embodiment for illustration of the present invention, but is not used for limiting the scope of application of the present invention.

Embodiment 1

The present invention is a kind of parameterized module multi-channel digital down-conversion design platform, include analog-to-digital conversion module and N channel Digital Down Converter Module, N road analog signal is given N number of Digital Down Converter Module through the digital signal that analog-to-digital conversion module exports and is done Digital Down Convert process, and exports N road baseband digital signal, see Fig. 1, parameterized module multi-channel digital down-conversion design platform of the present invention also includes N channel analog signal Shaping Module, parameter receiver module, input channel gating module, N channel parameters input port, N road analog signal inputs to N channel analog signal Shaping Module, export N road through shaping analog signal and give analog-to-digital conversion module, parameter is given parameter receiver module by data-interface simultaneously, the order of passage gating is given input channel gating module by parameter receiver module, input channel gating module exports the enable control signal of N number of passage to analog-to-digital conversion module, under the control of the enable control signal of N number of passage, analog-to-digital conversion module does analog-to-digital conversion to the M road analog signal selected, export M railway digital signal to M Digital Down Converter Module, the channel parameters on M road is given the parameters input port of M Digital Down Converter Module by parameter receiver module respectively simultaneously, M railway digital down-converted is done under state modulator, and export M road baseband digital signal.Digital Down Converter Module of the present invention is the Digital Down Converter Module of parameterized module.

See Fig. 2, the Digital Down Converter Module of parameterized module of the present invention is in original quadrature downconvert module, data delay cache module, the basis of filter coefficient module and multiply accumulating module also increases and has parameters input port, filter order and data rate control module, branching filter coefficient module, filter order control signal and rate controlled signal are given filter order and data rate control module by parameters input port simultaneously, the while of filter order and data rate control module, output filter exponent number and branch's extracting multiple signal are to branching filter coefficient module, and branch's extracting multiple signal is delivered to the input of data delay cache module, feedback command information channel and filter coefficient sendaisle is provided with between branching filter coefficient module and parameters input port, the branching filter coefficient of actual needs is selected according to parameter, each branching filter coefficient is given multiply accumulating module by branching filter coefficient module, the data of quadrature downconvert give data delay cache module simultaneously, under the control of branch's extracting multiple signal, data delay cache module carries out the delay under state modulator to the data of mixing and extracts process, buffer memory is done to the data after process, then export to multiply accumulating module, multiply accumulating module completes the multiply accumulating of data and filter coefficient and exports the baseband digital signal of Digital Down Convert.

Branching filter coefficient module in parameterized module Digital Down Converter Module of the present invention is also parametric control, feedback command information channel and filter coefficient sendaisle is provided with between branching filter coefficient module and parameters input port, according to filter order and branch's extracting multiple signal, filter coefficient is selected, if inner preset filter coefficient can meet the demand of design, choice for use is preset at the filter coefficient in buffer area A, if the filter order determined does not mate with preset filter order, feedback signal is sent to parameters input port, and export to data-interface through parameter receiver module, require that data-interface sends the filter coefficient on corresponding rank, and by real-time reception to filter coefficient be buffered in the buffer area B of branching filter coefficient module, give the multiply accumulating module of each branch.

Embodiment 2

Parameterized module multi-channel digital down-conversion design platform is with embodiment 1.

The present invention or a kind of parameterized module multi-channel digital down-conversion method for designing, method for designing runs on above-mentioned parameterized module multi-channel digital down-conversion design platform, and see Fig. 1, design process comprises:

A, N channel and multi-channel analog signal Shaping Module carry out shaping to N road analog signal, and export the analog signal after N shaping;

B, parameter receiver module receive data-interface and mainly comprise Ethernet interface, PCI mouth, serial ports, USB port, the parameter sent here and required filter coefficient, by the information feed back of Neutron module of the present invention to data-interface, can carry out interactive process simultaneously.

The reception of its parameter, formed and be allocated as follows shown in:

The order that B1, reception data-interface (data-interface can be Ethernet interface, PCI mouth, serial ports, USB port etc.) are sent here and corresponding filter coefficient, simultaneously also can by the information feed back of Neutron module of the present invention to data-interface, carry out interactive process, the selection of multiple interfaces, adds the simplicity of system, ease for use and versatility.

B2, the order received according to the parsing of concrete communication protocol, obtain filter order control signal L and the rate controlled signal K of each passage, export to the parameters input port of the Digital Down Converter Module of respective channel, realize the parametric control to each railway digital down-conversion.

B3, receiving filter coefficient, and filter coefficient is carried out buffer memory, then export to the branching filter coefficient module of respective channel.

C, input channel gating module export the enable control signal of N number of passage, and produce the enable control signal of N number of passage according to the passage gate control signal that parameter receiver module is sent here, this enable control signal is as the input signal of following analog-to-digital conversion module; Select M input channel gating module by N, it is enable that gating is set, select and need the passage processed to carry out subsequent treatment, and do not need the port number processed will be not enable, effectively can reduce the power consumption of system.

The generation of the enable control signal of input channel gating module, its production method is:

The control signal of the passage gating that C1, input channel gating module receiving parameter receiver module are sent here, control signal is resolved according to concrete interface communications protocol, obtain the enable control signal Ctrl [N-1:0] of N number of passage, the initialization value of Ctrl [N-1:0] is set to zero, and is defined as effectively high.

C2, wherein Ctrl [0] are the enable control of analog-to-digital conversion of passage 1, and Ctrl [1] is the enable control of analog-to-digital conversion of passage 2 ..., Ctrl [N-1] is the enable control of analog-to-digital conversion of passage N.

C3, when Ctrl [0] is for time high, represent that the analog signal of the enable i.e. selector channel 1 of passage 1 carries out analog-to-digital conversion, when Ctrl [0] is for time low, represent that the analog signal of the not enable i.e. passage 1 of passage 1 does not carry out analog-to-digital conversion; When Ctrl [1] is for time high, represent that passage 2 is enable, when Ctrl [1] is for time low, represent that passage 2 is not enable ..., the rest may be inferred respectively with M passage required for the M in N number of enable control signal effective signal behavior.

D, analog-to-digital conversion module comprise N number of analog to digital converter, and under the control of the N number of enable control signal that analog-to-digital conversion module provides in input channel gating module, the analog signal selecting the shaping of M road is carried out analog-to-digital conversion and exports M road independently digital signal.

E, parameterized digital down conversion module comprise M digital down-converted module, wherein each Digital Down Converter Module realizes parametric control by input parameter, and the specific implementation process that Digital Down Converter Module realizes Digital Down Convert comprises successively: quadrature downconvert, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating.

F, operation to the analog signal of N number of passage of input respectively implementation A ~ E, obtain the baseband digital signal after M railway digital down-converted.

In realization to the parameterized digital down-conversion of the M railway digital signal selected, the Digital Down Convert on each road all can use Digital Down Converter Module to carry out parametric control by input parameter and realize Digital Down Convert.The parametrization of Digital Down Convert, modularized design, make we pass through outside to parameter in certain scope, carry out the change of filter order and data rate, there is integrality and the reusability of parameterized module, make it apply broader.Design process comprises: quadrature downconvert, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating; Below each process is described in detail:

The digital signal that E1, analog-to-digital conversion export and orthogonal local oscillation sequence with be multiplied, sample rate f _swith signal intermediate frequency f ₀meet certain relation, make the local oscillator sequence be multiplied with meet:

$\cos \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{1,0,-\mathrm{1,0},\·\·\·\},$ $\sin \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{0,1,0},-1,\·\·\·\},$

See Fig. 4, first 2 times of extractions are carried out to sampled signal, obtain signal X (2n); After sampled signal being postponed a clock cycle simultaneously, carry out 2 times of extractions again and obtain signal X (2n+1), signal X (2n+1) is delayed a clock cycle than signal X (2n), d type flip flop latch signal X (2n) is adopted to postpone a clock cycle by X (2n), respectively 1 and-1 is alternately multiplied with X (2n+1) to the sequence X (2n) after extracting alignment, obtains orthogonal I (n), Q (n) two paths of signals respectively.

E2, see Fig. 5, according to input parameter L and K, determine filter order H and branch extracting multiple D, the exponent number of the conventional low-pass filter coefficients pre-set has 32 rank, 64 rank, 128 rank, 144 rank, be pre-stored in buffer area A, for the filter coefficient selecting this preset when inputting without external filter coefficient, this invention can be made not exclusively to depend on the filter coefficient of outside input, functionally there is independence.

If inner preset filter coefficient meets the demand of design, filter coefficient that can be preset in choice for use buffer area A, if the filter order H determined does not mate with preset filter order, data-interface can be exported to parameter receiver module feedback signal Cmd, require that data-interface sends the filter coefficient on H rank, and by real-time reception to H rank filter coefficient be buffered in the buffer area B of branching filter coefficient module; This of filter factor both can the coefficient that sends of real-time reception data-interface, also can select inner preset filter coefficient design, filter factor be moved variable, move back the generalization that can keep and control, have very strong versatility, practicality.

E3, see Fig. 7, according to the branch extracting multiple D obtained in E2 come control data postpone, be f in frequency _sunder the clock control of/2,0 carried out respectively to the orthogonal I (n) produced in E1, Q (n) two paths of signals, 1,2 ..., a D-1 clock cycle delay, I (n), Q (n) two-way respectively resolve into parallel D data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD, now the data rate of each branch road is the same, data rate and I (n) in E1, Q (n) two paths of data speed are identical, are f _s/ 2.

E4, carrying out control data extract according to the branch extracting multiple D obtained in E2, is f in frequency _sunder the clock control of/2, to in E3 postpone after data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD carries out D respectively and doubly extracts namely every D-1 data pick-up one number, obtain like this data branch road after extracting be Ic1, Ic2 ..., IcD, Qc1, Qc2 ..., QcD.Now the data rate of each branch is 1/D times of data rate in E3, is f _s/ 2D.

E5, see Fig. 6, be f in frequency _sunder the clock control of/2D, by the data branch road Ic1 after the extraction that obtains in E4, Ic2 ..., IcD, Qc1, Qc2 ..., QcD write respectively respective data buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., in RAMDQD.

E6, see Fig. 8, according to the filter order H obtained in E2 and branch extracting multiple D, produce switching signal Select by data selector, choose optimum filter coefficient.Choose the filter coefficient in buffer area A when Select is ' 0 ', choose the filter coefficient in the B of buffering area when Select is ' 1 '.

E7, control the generation of branching filter coefficient according to the branch extracting multiple D obtained in E2.First the coefficient C of filter will chosen in E6 ₁, C ₂, C ₃..., C _hcarry out odd even extraction, the filter coefficient C of even number ₂, C ₄..., C _hcomposition I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C _h-1composition Q path filter coefficient, carries out D to I path filter coefficient and doubly extracts, obtain the filter coefficient C of I1 branch from first coefficient ₂, , from second coefficient, carry out D to I path filter coefficient doubly to extract, obtain the filter coefficient C of I2 branch ₄, , the rest may be inferred to the filter coefficient C of ID branch _2D, , i path filter coefficient resolves into the filter coefficient vector of D branch altogether, finally the filter coefficient vector inverted sequence of each branch is buffered in respective coefficient buffering area RAMCI1, RAMCI2 ..., in RAMCID, the coefficient as buffer memory in RAMCI1 is followed successively by by address order from small to large , c ₂, the coefficient in like manner in other buffering area known, the generation of Q road branching filter coefficient is identical with the treatment step on I road.

E8, branch's filtering are actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 2D branch needs 2D multiply accumulating module.See Fig. 9, in frequency be clock control under, by E5 buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., the data reading of each branch of I, Q two-way of buffer memory in RAMDQD, simultaneously by E7 buffer area RAMCI1, RAMCI2 ..., RAMCID, RAMCQ1, RAMCQ2 ..., the filter coefficient of each branch of I, Q two-way of buffer memory reads in RAMCQD, the data read in RAMDI1 and RAMCI1 and coefficient give the input of a multiply accumulating module respectively, carry out the filtering of I1 branch.The filtering of other each branch is identical, the filter result of each branch of I, Q two-way be doutI1, doutI2 ..., doutID, doutQ1, doutQ2 ..., doutQD, now the data rate of each branch is f _s/ 2D.

E9, be f in frequency _sunder the clock control of/2D, by D, I road in E8 branch filter result doutI1, doutI2 ..., doutID is added, the I road result obtaining Digital Down Convert exports doutI; By D, Q road branch filter result doutQ1, doutQ2 ..., doutQD is added, the Q road result obtaining Digital Down Convert exports doutQ.So far, the process of parameterized module Digital Down Convert is completed.

Embodiment 3

Parameterized module multi-channel digital down-conversion design platform and parameterized module multi-channel digital down-conversion method for designing are with embodiment 1-2.

For making object of the present invention, advantage and technical method clearly, based on modularization idea, the modules in embodiment of the present invention is described in detail in programmable logic device Xilinx Virtex5 Series FPGA below.

1, N (N >=1) channel analog signal Shaping Module.Each passage comprises an analog signal shaping circuit, after analog signal shaping circuit is used for adjusting the analog signal of N number of passage of input, exports to analog-to-digital conversion module.

2, input channel gating module.This module exports the enable control signal of N number of passage, selects M passage for carrying out selection to N number of separate analog channel.This enable control signal, as the input of analog-to-digital conversion module, only has enable signal effective respective channel analog signal selected.

3, analog-to-digital conversion module.This module comprises N number of analog to digital converter, carrys out the analog signal after gating M road shaping according to the individual effective enable control signal of the M provided in input channel gating module (M≤N), carries out analog-to-digital conversion and exports M road independently digital signal.

4, parameter receiver module.Parameter receiver module is the interface carrying out data communication with outside, for receiving the filter coefficient of order as the data-interfaces such as Ethernet interface, PCI mouth, serial ports, USB port send and needs.This module also by the information feed back of Neutron module of the present invention to data-interface, can carry out interactive process simultaneously.This module mainly according to the command analysis that concrete communication protocol will receive, obtains filter order control signal L and the rate controlled signal K of each passage, exports to the Digital Down Converter Module of respective channel; The filter coefficient of each passage received is carried out buffer memory simultaneously, also Digital Down Converter Module can be sent here feedback command send to outside port.

5, M channel parameters Modularized digital down conversion module.This module is nucleus module of the present invention, comprises M digital down-converted module, wherein the digital lower side frequency of each passage be by M Digital Down Converter Module respectively input parameter realize parametrization and arrange and control, independently process.Digital Down Converter Module comprises each submodule, Qi Zhongyou: quadrature downconvert module, filter order and data rate control module, branching filter coefficient module, data delay cache module and multiply accumulating module.Be described the submodule of Digital Down Converter Module below, Fig. 2 is shown in by concrete block diagram.

6, quadrature downconvert module.The theory diagram of quadrature downconvert as shown in Figure 4.Based on the thought of modularized processing, the input of this module is the digital signal that analog-to-digital conversion module exports, and output is I, Q two-way baseband signal orthogonal after mixing.This module to A/D sampling export digital signal carry out mixing, sampled signal is carried out odd even extraction, the two paths of signals obtained respectively with orthogonal local oscillation sequence with be multiplied, export the baseband signal that two-way is orthogonal.

7, filter order and data rate control module.The filter order control signal L that this module is sent here according to parameter receiver module and rate controlled signal K, carry out the optimum choice of filter order, obtain total exponent number H and the branch extracting multiple D of present filter needs, exponent number H and branch extracting multiple D is exported to other submodule through buffer memory.Here filter order control signal L is defined as the outside filter order sent; Need the multiple extracted according to actual conditions after rate controlled signal K is defined as sampled signal quadrature downconvert; H is defined as the exponent number of actually determined filter; Before branch extracting multiple D is defined as each branching filter filtering, each branch data is needed to the extracting multiple of carrying out.

8, data delay cache module.According to the branch extracting multiple D that process 7 obtains, I, Q two paths of data after this module registration hands over mixing carries out postponing, extracting and caching process respectively.Following process is all for I road, as shown in Figure 7, first 1 postponed successively to data, 2 ..., a D-1 unit, altogether obtain the data that D road is parallel, carry out D respectively to every circuit-switched data more doubly to extract, D circuit-switched data obtains D tap altogether, the data of D tap is buffered in respectively in D buffer area, exports to the data input pin of multiply accumulating module in process 10.

9, branching filter coefficient module.The filter coefficient received is buffered in an independent buffer area by this module.According to multiphase filter total exponent number H and branch extracting multiple D that process 7 obtains, this module can select the filter coefficient of corresponding exponent number, and according to multiphase filtering principle, filter coefficient is carried out extracting and resetting, obtain the coefficient vector of D tap and the coefficient vector of D branching filter, after buffer memory, export to the coefficient input terminals of multiply accumulating module in process 10 respectively.

10, multiply accumulating module.Through the process of process 1 ~ 9, what this module realized is final step and the multiply accumulating of multiphase filter.After the coefficient of each branching filter that the data of each branch process 8 exported and process 9 export carries out multiply accumulating respectively, obtain the output of D the branching filter on I road, the output of this D branching filter periodically to be sued for peace output by control signal, the I road finally obtaining Digital Down Convert exports again.The processing procedure on Q road is similar.

Embodiment 4

Parameterized module multi-channel digital down-conversion design platform and parameterized module multi-channel digital down-conversion method for designing are with embodiment 1-2-3.

For making object of the present invention, advantage and technical method clearly, by arranging corresponding parameter, the present invention will be described in more detail.The parameter that in this example, host computer is sent to this platform by PCI mouth is: N=16, M=8, filter order H=144, branch extracting multiple D=6, and in this example, the parameter of each passage process is duplicate.In programmable logic device Xilinx Virtex5 Series FPGA, embodiment of the present invention is described in further detail below.

Realize step of the present invention as follows:

Step 1, analog signal shaping.

N=16 in this example, after the analog input signal that 16 channel analog signal Shaping Modules receive 16 passages adjusts, then exports to analog-to-digital conversion module.

Step 2, parses the enable control signal of 16 passages.

In this example, data-interface is pci interface, and host computer sends parameter to parameter receiver module by pci interface.Parameter receiver module parses the order of passage gating according to the communication protocol of pci interface, obtains the enable control signal Ctrl [15:0] of 16 passages.In this example, the enable control signal parsed is CtrI [15:0]=0000000011111111.

Step 3, multi-center selection.

Enable control signal Ctrl [15:0] in step 2 is sent to analog-to-digital conversion module, and the analog signal controlling respective channel carries out analog-to-digital conversion.In this example, the analog signal of selector channel 1 ~ 8 carries out analog-to-digital conversion, obtains 8 railway digital signals.And passage 9 ~ 16 is not enable does not namely carry out analog-to-digital conversion.

Step 4, parses the controling parameters of 8 passages.

Parameter receiver module, according to the communication protocol of pci interface, receives the host computer order of sending and corresponding filter coefficient in real time.From order parse 8 passages filter order control signal L1, L2 ..., L8 and rate controlled signal K1, K2 ..., K8.L1 and K1 is given the parameters input port of passage 1 Digital Down Converter Module, L2 and K2 is given the parameters input port of passage 2 Digital Down Converter Module ..., L8 and K8 is given the parameters input end of passage 8 Digital Down Converter Module; The filter coefficient of 8 passages sends to 8 Digital Down Converter Module respectively simultaneously, and is buffered in the buffer area of branching filter coefficient module.

Step 5, the realization of parameterized module Digital Down Convert.

The structure of the parameterized digital down conversion module of 8 passages is identical, distinguish to some extent unlike inputted controling parameters and filter coefficient, the parameter L1 produced by step 4, L2 ..., L8 and K1, K2 ..., K8 can realize the parametric control on each road.Below the step of passage 1 parameterized digital down conversion module of the present invention is described in detail:

1, signal in orthogonal mixing.

In this example, the intermediate frequency f of analog signal ₀=210M, bandwidth B=5M.According to bandpass sample theory n gets the integer meeting fs>=2B, the sample rate f s=120M of the analog to digital converter in this example.Local oscillator sequence with meet following relation:

$\cos \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{1,0,-\mathrm{1,0},\·\·\·\},$ $\sin \left(2\mathrm{\π}\frac{f_0}{f_s}n\right)=\{\mathrm{0,1,0},-1,\·\·\·\}.$

Based on above-mentioned condition, be under the control of 120M clock in frequency, from first efficient clock edge, first 2 times of extractions carried out to sampled signal, obtain signal X (2n); After sampled signal being postponed a clock cycle simultaneously, then carry out 2 times of extractions and obtain signal X (2n+1).Signal X (2n+1) is delayed a clock cycle than signal X (2n), X (2n) is postponed a clock cycle, then when efficient clock is along arrival, sequence X (2n) after extracting alignment is alternately multiplied 1 and-1 respectively with X (2n+1), obtains orthogonal I (n), Q (n) two paths of signals.Data rate now has been reduced to the half of sample rate, is 60M.

2, filter order H and the branch extracting multiple D of passage 1 is parsed.

In this example, the parameter L1=144 sent according to host computer and K1=12, determines filter order H=144, branch extracting multiple D=6.The filter order H=144 determined in this example, do not mate with preset filter order, to parameter receiver module feedback signal Cmd, host computer is sent to by pci interface, host computer receives this feedback signal, and the filter coefficient being sent H=144 rank by pci interface is buffered in the buffer area B of branching filter coefficient module.

3, data delay.

Carry out control data according to the branch extracting multiple D=6 obtained to postpone.Be under the clock control of 60M in frequency, 0 carried out respectively to the orthogonal I (n) produced in 1, Q (n) two paths of signals, 1,2 ..., 5 clock cycle delay, I (n), Q (n) two-way respectively resolve into 6 parallel data branch road Id1, Id2 ..., Id6, Qd1, Qd2 ..., Qd6, now the data rate of each branch road is the same, data rate and I (n) in 1, Q (n) two paths of data speed are identical, are 60M.

4, branch data extracts.

Carry out control data according to the branch extracting multiple D=6 obtained to extract.Be under the clock control of 60M in frequency, to the data branch road Id1 after postponing in 3, Id2 ..., Id6, Qd1, Qd2 ..., Qd6 carry out respectively 6 times extract namely every 5 data pick-up one numbers, obtain like this extract after data branch road be Ic1, Ic2 ..., Ic6, Qc1, Qc2 ..., Qc6.Now the data rate of each branch is 1/6 times of data rate in 3, is 10M.

5, branch data buffer memory.

Be under the clock control of 10M in frequency, extract according to branch data the data branch road Ic1 after the extraction obtained, Ic2 ..., Ic6, Qc1, Qc2 ..., Qc6 write respectively respective data buffer area RAMDI1, RAMDI2 ..., RAMDI6, RAMDQ1, RAMDQ2 ..., in RAMDQ6.

6, the selection of filter coefficient.

According to the filter order H=144 obtained and branch extracting multiple D=6, produce switching signal Select=1 by data selector, choose optimum filter coefficient and the filter coefficient be buffered in buffer area B of real-time reception.

7, the generation of branching filter coefficient.

The generation of branching filter coefficient is controlled according to the branch extracting multiple D=6 obtained.First the coefficient C of filter will chosen ₁, C ₂, C ₃..., C ₁₄₄carry out odd even extraction, the filter coefficient C of even number ₂, C ₄..., C ₁₄₄composition I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C ₁₄₃composition Q path filter coefficient.Then from first coefficient, carry out D=6 to I path filter coefficient doubly to extract, obtain the filter coefficient C of I1 branch ₂, C ₁₄, C ₂₆..., C ₁₃₄; From second coefficient, carry out D=6 to I path filter coefficient doubly to extract, obtain the filter coefficient C of I2 branch ₄, C ₁₆, C ₂₈..., C ₁₃₆; The rest may be inferred to the filter coefficient C of I6 branch ₁₂, C ₂₄, C ₃₆..., C ₁₄₄.I path filter coefficient resolves into the filter coefficient vector of 6 branches altogether.Finally the filter coefficient vector inverted sequence of each branch is buffered in respective coefficient buffering area RAMCI1, RAMCI2 ..., in RAMCI6, the coefficient as buffer memory in RAMCI1 is followed successively by C by address order from small to large ₁₃₄..., C ₂₆, C ₁₄, C ₂, the coefficient in like manner in other buffering area known.

The generation of Q road branching filter coefficient is identical with the treatment step on I road.

8, branch's filtering process.

Branch's filtering is actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 12 branches needs 12 multiply accumulating modules, also just needs 12 adder and multiplier DSP48E.Be under the clock control of 120M in frequency, by buffer area RAMDI1, RAMDI2 ..., RAMDI6, RAMDQ1, RAMDQ2 ..., the data reading of each branch of I, Q two-way of buffer memory in RAMDQ6, simultaneously by buffer area RAMCI1, RAMCI2 ..., RAMCI6, RAMCQ1, RAMCQ2 ..., the filter coefficient of each branch of I, Q two-way of buffer memory reads in RAMCQ6.The data read in RAMDI1 and RAMCI1 and coefficient give A, B input of a DSP48E respectively, and the operating frequency of DSP48E is identical with data rate here, are 120M, and the mode of operation arranging DSP48E is multiply accumulating pattern.See Figure 10, utilize the thought of DSP48E time-sharing multiplex, achieve the filtering of I1 branch; The filtering of other each branch is identical.

Be under the clock control of 120M in frequency, be that the Output rusults of count cycle to DSP48E extracts with 12, can obtain the filter result doutI1 of each branch of I, Q two-way, doutI2 ..., doutI6, doutQ1, doutQ2 ..., doutQ6, now the data rate of each branch is 10M.

9, passage 1 Digital Down Convert I, Q two-way result exports

Be under the clock control of 10M in frequency, by obtain 6, I road branch filter result doutI1, doutI2 ..., doutI6 is added, the I road result obtaining Digital Down Convert exports doutI; By 6, Q road branch filter result doutQ1, doutQ2 ..., doutQ6 is added, the Q road result obtaining Digital Down Convert exports doutQ.

Completed the parameterized digital down-converted of passage 1 by step 1 ~ 9, the processing procedure of passage 2 ~ 8 and the processing procedure of passage 1 similar, so far complete the Digital Down Convert process of 1 ~ 8 passage, obtain 8 railway digital baseband signals.

Above-mentioned implementation method is the present invention's preferably embodiment; but embodiments of the present invention are not by the restriction of above-mentioned embodiment; other any do not run counter to make under Spirit Essence of the present invention, technical scheme and principle change, replacement, combination, simplification or repacking; the substitute mode of equivalence all should be considered as, be included within protection scope of the present invention.

To sum up, the invention discloses a kind of parameterized module multi-channel digital down-conversion design platform and method, the present invention is a kind of Digital Down Convert design platform of parameterized module, select M passage to the analog input signal of N number of passage to carry out analog-to-digital conversion, then do Digital Down Convert process and export M road baseband digital signal, subsequent treatment uses altogether.The present invention is not only a kind of design platform or a kind of method for designing, and the design process of the method for designing of this parameterized moduleization multi-channel digital down-conversion is: carry out quadrature downconvert to supplied with digital signal; The parametric solution arrived according to real-time reception separates out filter order H and branch extracting multiple D, is done respectively by the signal after quadrature downconvert to postpone, extract and buffer memory; The filter coefficient chosen is carried out extraction to reset simultaneously, obtain each branching filter coefficient vector and do buffer memory; The data of buffer memory and coefficient are sent to multiply accumulating module simultaneously and do branch's filtering process, extract its periodicity of fruiting, sue for peace, obtain M roadbed band signal, each road signal comprises the orthogonal signalling of I, Q two-way.The present invention has the advantage of ease for use, versatility and flexibility, for multichannel if sampling signal is transformed into baseband signal, reaches the object reducing data rate simultaneously.

Claims (7)

1. a parameterized module multi-channel digital down-conversion design platform, include analog-to-digital conversion module and N number of Digital Down Converter Module, N road analog signal is given N number of Digital Down Converter Module through the digital signal that analog-to-digital conversion module exports and is done Digital Down Convert process, and exports N road baseband digital signal, it is characterized in that: parameterized module multi-channel digital down-conversion design platform also includes N channel analog signal Shaping Module, parameter receiver module, input channel gating module, N number of parameters input port, N road analog signal inputs to N channel analog signal Shaping Module, export N road through shaping analog signal and give analog-to-digital conversion module, parameter is given parameter receiver module by data-interface simultaneously, the order of passage gating is given input channel gating module by parameter receiver module, input channel gating module exports the enable control signal of N number of passage to analog-to-digital conversion module, under the control of the enable control signal of N number of passage, analog-to-digital conversion module does analog-to-digital conversion to the M road analog signal selected, export M railway digital signal to M Digital Down Converter Module, the channel parameters on M road is given the parameters input port of M Digital Down Converter Module by parameter receiver module respectively simultaneously, M railway digital down-converted is done under state modulator, and export M road baseband digital signal, described Digital Down Converter Module is the Digital Down Converter Module of parameterized module.

2. according to parameterized module multi-channel digital down-conversion design platform in claim 1, it is characterized in that: the Digital Down Converter Module of parameterized module, in original quadrature downconvert module, data delay cache module, the basis of filter coefficient module and multiply accumulating module also increases and has parameters input port, filter order and data rate control module, branching filter coefficient module, filter order control signal and rate controlled signal are given filter order and data rate control module by parameters input port simultaneously, the while of filter order and data rate control module, output filter exponent number and branch's extracting multiple signal are to branching filter coefficient module, and branch's extracting multiple signal is delivered to the input of data delay cache module, feedback command information channel and filter factor sendaisle is provided with between branching filter coefficient module and parameters input port, the branching filter coefficient of actual needs is selected according to parameter, each branching filter coefficient is given multiply accumulating module by branching filter coefficient module, the data of quadrature downconvert give data delay cache module simultaneously, under the control of branch's extracting multiple signal, data delay cache module carries out the reduction of speed process of delay under parametric control and extraction to the data of mixing, buffer memory is done to the data after reduction of speed, then export and give multiply accumulating module, multiply accumulating module completes the multiply accumulating of data and filter coefficient and exports I, Q two-way baseband digital signal of Digital Down Convert.

3. according to parameterized module multi-channel digital down-conversion design platform in claim 2, it is characterized in that: the branching filter coefficient module in parameterized module Digital Down Converter Module is also parametric control, according to filter order and branch's extracting multiple signal, filter coefficient is selected, if inner preset filter coefficients can meet the demand of design, choice for use is preset at the filter coefficient in buffer area A, if the filter order determined does not mate with preset filter order, feedback signal is sent to parameters input port, and export to data-interface through parameter receiver module, require that data-interface sends the filter coefficient on corresponding rank, and by real-time reception to filter coefficient be buffered in the buffer area B of branching filter coefficient module, give the multiply accumulating module of each branch.

4. a parameterized module multi-channel digital down-conversion method for designing, is characterized in that: design process comprises:

A, N channel and multi-channel analog signal Shaping Module carry out shaping to N road analog signal to be processed, export the analog signal after the shaping of N road and send to analog-to-digital conversion module;

B, parameter receiver module receive data-interface and mainly comprise Ethernet interface, PCI mouth, serial ports, parameter that USB port is sent here and required filter coefficient, from Digital Down Converter Module, feedback information are sent to data-interface simultaneously, carry out interactive process;

C, input channel gating module produce the enable control signal of N number of passage according to the passage gate control signal that parameter receiver module is sent here, and this enable control signal is as the input signal of following analog-to-digital conversion module;

D, analog-to-digital conversion module comprise N number of analog to digital converter, and under the control of the N number of enable control signal that analog-to-digital conversion module provides in input channel gating module, the analog signal selecting the shaping of M road is carried out analog-to-digital conversion and exports M road independently digital signal;

E, parameterized digital down conversion module comprise M digital down-converted module, wherein each Digital Down Converter Module realizes parametric control by input parameter, and the specific implementation process that Digital Down Converter Module realizes Digital Down Convert comprises successively: quadrature downconvert, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating;

F, the analog signal to be processed of N number of passage of input is performed respectively to the operation of design process A ~ E, obtain the baseband digital signal after M railway digital down-converted.

5., according to the parameterized module multi-channel digital down-conversion method for designing described in claim 4, it is characterized in that parameter receiving course, wherein parameter reception, formed and be allocated as follows shown in:

The order that B1, reception data-interface are sent here and corresponding filter coefficient, send to data-interface by each Digital Down Converter Module feedack simultaneously;

B2, the order received according to the parsing of concrete communication protocol, obtain filter order control signal L and the rate controlled signal K of each passage, export to the parameters input port of the Digital Down Converter Module of respective channel, realize the parametric control to each railway digital down-conversion;

B3, receiving filter coefficient, and filter coefficient is carried out buffer memory, then export to the branching filter coefficient module of respective channel.

6. parameterized module multi-channel digital down-conversion method for designing according to claim 5, be characterised in that the generation of the enable control signal of input channel gating, its production method is:

The control signal of the passage gating that C1, input channel gating module receiving parameter receiver module are sent here, control signal is resolved according to concrete interface communications protocol, obtain the enable control signal Ctrl [N-1:0] of N number of passage, the initialization value of Ctrl [N-1:0] is set to zero, and is defined as effectively high;

C2, wherein Ctrl [0] are the enable control of analog-to-digital conversion of passage 1, and Ctrl [1] is the enable control of analog-to-digital conversion of passage 2 ..., Ctrl [N-1] is the enable control of analog-to-digital conversion of passage N;

C3, when Ctrl [0] is for time high, represent that the analog signal of the enable i.e. selector channel 1 of passage 1 carries out analog-to-digital conversion, when Ctrl [0] is for time low, represent that the analog signal of the not enable i.e. passage 1 of passage 1 does not carry out analog-to-digital conversion; When Ctrl [1] is for time high, represent that passage 2 is enable, when Ctrl [1] is for time low, represent that passage 2 is not enable, the rest may be inferred respectively with M passage required for the M in N number of enable control signal effective signal behavior.

7. according to the parameterized module multi-channel digital down-conversion method for designing described in claim 6, it is characterized in that the realization of parameterized digital down-conversion, all can realize parametric control to the Digital Down Convert on each road of the M railway digital signal selected, design process comprises: quadrature downconvert, filter order and data rate control, the selection of branching filter coefficient, data delay buffer memory and multiply accumulating; Below each process is described in detail:

The digital signal that analog-to-digital conversion exports by E1, quadrature downconvert and orthogonal local oscillation sequence with be multiplied, sample rate f _swith signal intermediate frequency f ₀meet certain relation, make the local oscillator sequence be multiplied with meet:

first 2 times of extractions are carried out to sampled signal, obtain signal X (2n); After sampled signal being postponed a clock cycle simultaneously, carry out 2 times of extractions again and obtain signal X (2n+1), signal X (2n+1) is delayed a clock cycle than signal X (2n), d type flip flop latch signal X (2n) is adopted to postpone a clock cycle by X (2n), respectively 1 and-1 is alternately multiplied with X (2n+1) to the sequence X (2n) after extracting alignment, obtains orthogonal I (n), Q (n) two paths of signals respectively;

E2, according to input parameter L and K, determine filter order H and branch extracting multiple D, the exponent number of the conventional low-pass filter coefficients pre-set has 32 rank, 64 rank, 128 rank, 144 rank, be pre-stored in buffer area A, can for the filter coefficient selecting this preset when inputting without external filter coefficient, if inner preset filter coefficient meets the demand of design, filter coefficient preset in choice for use buffer area A, if the filter order H determined does not mate with preset filter order, data-interface is exported to parameter receiver module feedback signal Cmd, require that data-interface sends the filter coefficient on H rank, and by real-time reception to H rank filter coefficient be buffered in the buffer area B of branching filter coefficient module,

E3, carrying out control data postpone according to the branch extracting multiple D obtained in above process E2, is f in frequency _sunder the clock control of/2,0 carried out respectively to the orthogonal I (n) produced in E1, Q (n) two paths of signals, 1,2 ..., a D-1 clock cycle delay, I (n), Q (n) two-way respectively resolve into parallel D data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD, now the data rate of each branch road is the same, data rate and I (n) in E1, Q (n) two paths of data speed are identical, are f _s/ 2;

E4, carrying out control data extract according to the branch extracting multiple D obtained in above process E2, is f in frequency _sunder the clock control of/2, to in E3 postpone after data branch road Id1, Id2 ..., IdD, Qd1, Qd2 ..., QdD carries out D respectively and doubly extracts namely every D-1 data pick-up one number, obtain like this extract after data branch road be Ic1, Ic2 ..., IcD, Qc1, Qc2 ..., QcD, now the data rate of each branch is 1/D times of data rate in E3, is f _s/ 2D;

E5, be f in frequency _sunder the clock control of/2D, by the data branch road Ic1 after the extraction that obtains in E4, Ic2 ..., IcD, Qc1, Qc2 ..., QcD write respectively respective data buffer area RAMDI1, RAMDI2 ..., RAMDID, RAMDQ1, RAMDQ2 ..., in RAMDQD;

E6, according to the filter order H obtained in above process E2 and branch extracting multiple D, switching signal Select is produced by data selector, choose optimum filter coefficient, choose the filter coefficient in buffer area A when Select is ' 0 ', choose the filter coefficient in the B of buffering area when Select is ' 1 ';

E7, control the generation of branching filter coefficient according to the branch extracting multiple D obtained in above process E2, the coefficient C of filter first will chosen in above process E6 ₁, C ₂, C ₃..., C _hcarry out odd even extraction, the filter coefficient C of even number ₂, C ₄..., C _hcomposition I path filter coefficient, the filter coefficient C of odd number ₁, C ₃..., C _h-1composition Q path filter coefficient, carries out D to I path filter coefficient and doubly extracts, obtain the filter coefficient C of I1 branch from first coefficient ₂, , from second coefficient, carry out D to I path filter coefficient doubly to extract, obtain the filter coefficient C of I2 branch ₄, , the rest may be inferred to the filter coefficient C of ID branch _2D, , i path filter coefficient resolves into the filter coefficient vector of D branch altogether, finally the filter coefficient vector inverted sequence of each branch is buffered in respective coefficient buffering area RAMCI1, RAMCI2 ..., in RAMCID, the coefficient as buffer memory in RAMCI1 is followed successively by by address order from small to large , c ₂, the coefficient in like manner in other buffering area known, the generation of Q road branching filter coefficient is identical with the treatment step on I road;

E8, branch's filtering are actually the process of branch data and filter coefficient multiply accumulating, and I, Q two-way altogether 2D branch needs 2D multiply accumulating module, in frequency is clock control under, by above process E5 buffer area RAMDI1, RAMDI2, RAMDID, RAMDQ1, RAMDQ2, the I of buffer memory in RAMDQD, the data reading of each branch of Q two-way, simultaneously by above process E7 buffer area RAMCI1, RAMCI2, RAMCID, RAMCQ1, RAMCQ2, the I of buffer memory in RAMCQD, the filter coefficient of each branch of Q two-way reads, the data read in RAMDI1 and RAMCI1 and coefficient give the input of a multiply accumulating module respectively, carry out the filtering of I1 branch, the filtering of other each branch is identical, I, the filter result of each branch of Q two-way is doutI1, doutI2, doutID, doutQ1, doutQ2, doutQD, now the data rate of each branch is f _s/ 2D,

E9, be f in frequency _sunder the clock control of/2D, by D, I road in E8 branch filter result doutI1, doutI2 ..., doutID is added, the I road result obtaining Digital Down Convert exports doutI; By D, Q road branch filter result doutQ1, doutQ2 ..., doutQD is added, the Q road result obtaining Digital Down Convert exports doutQ.So far, the process of parameterized module Digital Down Convert is completed.