CN116015248A

CN116015248A - CIC-HB cascading digital filter and verification method thereof

Info

Publication number: CN116015248A
Application number: CN202211620853.6A
Authority: CN
Inventors: 章强
Original assignee: Huai'an Huihong Precision Mould Co ltd
Current assignee: Huai'an Huihong Precision Mould Co ltd
Priority date: 2022-12-16
Filing date: 2022-12-16
Publication date: 2023-04-25

Abstract

The invention discloses a CIC-HB cascade digital filter and a verification method thereof, wherein the CIC-HB cascade digital filter is obtained by cascading a two-stage CIC module and a one-stage HB module, wherein the first stage is a four-stage eight-time extraction CIC module, the second stage is a nine-stage eight-time extraction CIC module, and the third stage is a ten-stage two-time extraction HB module. The invention provides a CIC-HB cascade extraction filter with a down-sampling and filtering function of a signal based on the output of a Sigma-Delta modulator, which can reduce the data after over-sampling to the range of 2 times of the signal bandwidth, and the system has a smaller power signal-to-noise ratio loss ratio than the traditional architecture, realizes the effective data precision of 20.4 bits, and simultaneously provides the digital design, verification strategy and the result of the CIC-HB cascade extraction filter.

Description

CIC-HB cascading digital filter and verification method thereof

Technical Field

The application relates to the field of signal filtering, in particular to a CIC-HB cascade digital filter and a verification method thereof.

Background

In the background of the present big data age, the development of information technology is mainly developed in the directions of digitalization, networking and intelligence. In our real life, most of the signals are analog signals, and the digital signals account for only a small part. Analog signals are usually continuous functions based on time, can be represented by discrete sequences through discretization in amplitude and time, and are the whole process of analog-to-digital conversion, and a series of digital domain processes can be carried out on the analog-to-digital conversion of the signals through an embedded SoC or a computer to finish the works of encoding, transmitting, storing and the like of the signals. Meanwhile, with rapid development of digital signal processing technology, application requirements on digital signal acquisition and coding, transmission processing and the like are increasingly larger, and in order to optimize processing speed and storage space, designers often use various sampling rates in a digital signal processing system, so that multi-rate digital signal processing technology is widely focused and applied.

The analog implementation is tightly connected with the digital domain, namely an analog-to-digital converter (Analog to Digital Converter, ADC), and the Sigma-Delta ADC based on the over-sampling and noise shaping technology is widely applied to the application occasions of medium-long wave high resolution due to the characteristics of high precision and high signal-to-noise ratio. The Sigma-Delta modulator and digital decimation filter are combined into a complete Sigma-Delta ADC system. The main functions of the Sigma-Delta modulator are oversampling and noise shaping, whereas the oversampled signal eventually needs to be reduced to 2 times the sampling bandwidth.

Disclosure of Invention

The invention provides a CIC-HB cascade extraction filter with a down-sampling and filtering function of a signal based on the output of a Sigma-Delta modulator, which can reduce the data after over-sampling to the range of 2 times of the signal bandwidth, and the system has a smaller power signal-to-noise ratio loss ratio than the traditional architecture, realizes the effective data precision of 20.4 bits, and simultaneously provides the digital design, verification strategy and the result of the CIC-HB cascade extraction filter.

The embodiment of the application discloses a CIC-HB cascading digital filter, which is obtained by cascading a two-stage CIC module and a one-stage HB module, wherein the first stage is a four-order eight-time CIC module, the second stage is a nine-order eight-time CIC module, and the third stage is a ten-order two-time HB module.

Correspondingly, a verification method of the CIC-HB cascade digital filter is also disclosed, such as the verification method of the fourth-order eight-time extraction CIC module, algorithm modeling is carried out based on an MATLAB platform, the extraction rate D is set to be 8, the passband cutoff frequency is set to be 1KHz, the stopband initial frequency is set to be 2KHz, the passband ripple is +/-0.01 db and the stopband attenuation is-90 db, and a first-order CIC model is built.

Correspondingly, a verification method of the CIC-HB cascade digital filter is also disclosed, such as the verification method of the nine-order eight-time extraction CIC module, algorithm modeling is carried out based on an MATLAB platform, the extraction rate D is set to be 8, the passband cutoff frequency is set to be 1KHz, the stopband initial frequency is set to be 2KHz, the passband ripple is +/-0.01 db and the stopband attenuation is-90 db, and a second-order CIC model is constructed.

Correspondingly, a verification method of the CIC-HB cascade digital filter is also disclosed, such as the verification method of the tenth-order double-extraction HB module, wherein the input sampling rate is 4KHz, the extraction rate is 2 times, the passband is 0.5KHz, the stop band is started at 1.5KHz, the passband ripple is +/-0.01 db, the stop band attenuation is 80db, and the algorithm modeling is performed through MATLAB.

Compared with the prior art, the method is applied to the Sigma-Delta analog-to-digital converter, and the processing object is that the Sigma-Delta modulator outputs one-bit digital bit stream, so that the method has higher sampling frequency and high-frequency noise. The invention can accurately process the signal bit stream with the input signal rate of one bit quantized 256KHz and the output signal of 2KHz, and can realize the adjustment of the signal rate and ensure the integrity of the effective signal of the passband. The main performance indexes and advantages of the invention can be summarized as follows:

(1) Low pass filtering is realized: the attenuation of passband signals is reduced as much as possible, and high-frequency noise is filtered;

(2) Extraction is realized: the sampling rate of the output signal is reduced to the Nyquist frequency, so that the consumption is reduced;

(3) High fidelity: the digital circuit design strategy of the system can realize the representation of the power signal-to-noise ratio close to the theoretical end of the algorithm, and has higher fidelity.

(4) Low cost: compared with the traditional direct architecture, the system uses less hardware overhead to realize the system functions.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a diagram of a digital decimation filter system according to an embodiment of the invention;

FIG. 2 is a block diagram of an integrator vanity filter in accordance with an embodiment of the present invention;

FIG. 3 is a graph showing the amplitude-frequency response of the first stage CIC filter according to an embodiment of the present invention;

FIG. 4 is a signal-to-noise ratio diagram of the output power of the first stage CIC modeling in an embodiment of the invention;

FIG. 5 is a diagram showing the signal-to-noise ratio of the second stage CIC modeling output power in an embodiment of the invention;

FIG. 6 is a diagram of a five-order CIC differential transfer topology in an embodiment of the invention;

FIG. 7 is a diagram showing the signal-to-noise ratio of the output power of the first CIC RTL according to an embodiment of the present invention;

FIG. 8 is a diagram showing the signal-to-noise ratio of the second CIC RTL output power in an embodiment of the present invention;

FIG. 9 is a graph showing the amplitude-frequency response of a HalfBand filter in an embodiment of the invention;

FIG. 10 is a schematic diagram of a tenth order HalfBand differential transfer topology in an embodiment of the invention;

FIG. 11 is a top-level design of a cascaded digital decimation filter according to an embodiment of the invention;

FIG. 12 is a graph of power SNR for a cascaded digital decimation filter according to an embodiment of the invention;

FIG. 13 is a waveform diagram of the output of a cascaded digital decimation filter according to an embodiment of the invention;

FIG. 14 is a graph showing the signal-to-noise ratio of the output power of the cascaded digital decimation filter circuit according to an embodiment of the invention.

Detailed Description

The following detailed description of the technical solutions according to the embodiments of the present invention will be given with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Cascaded digital decimation filter designs.

1.1 Cascade digital decimation Filter architecture

The invention takes a bit quantized bit stream with a rate of 256KHz as an example, and performs decimation filtering on the rate signal, so that the digital decimation filter provided by the invention is effective. The following table gives the performance index of the cascaded digital decimation filter of the invention.

The CIC-HB cascade type extraction filter provided by the invention is obtained by adopting two-stage CIC modules and one-stage HB module in cascade connection, and a schematic diagram of the whole extraction filter is shown in FIG. 1. The first stage is four-order eight-time pumping CIC, the second stage is nine-order eight-time pumping CIC, and the third stage is ten-order two-time pumping HB.

1.2 integral dressing filter and cascade design and verification thereof

As shown in fig. 2, the CIC filter belongs to a finite impulse response filter, and has the advantages of saving hardware overhead and saving cost compared with a direct FIR. The filter system is proposed by authors such as KWENTUS, a transfer function of the filter system is shown in the following formula (1), D in the function represents the extraction rate of a CIC filter, N represents the order of the CIC filter, and the relation between the order N and the order L of a modulator is as follows: n is more than or equal to L+1.

(1) The first order CIC algorithm models. Algorithm modeling is carried out based on an MATLAB platform, the extraction rate D is set to be 8, the passband cut-off frequency is 1KHz, the stopband starting frequency is 2KHz, the passband ripple is +/-0.01 db and the stopband attenuation is-90 db through formula reasoning, a first-order CIC model is constructed, and the filter amplitude frequency response is shown in figure 3. By analyzing the waveform curve, it can be obtained that: passband attenuation in the 1kHz range is almost negligible, however signal roll-off in the 1kHz-2kHz range is not significant enough, and this problem is addressed by cascading second-stage CIC. The 256Khz one-bit data stream is then used as the fourth-order eight-times-extraction CIC input for the design, and the output power signal-to-noise ratio is as shown in fig. 4.

(2) The second order CIC algorithm models. Setting the extraction rate D as 8, the passband cut-off frequency as 1KHz, the stopband initial frequency as 2KHz, the passband ripple as +/-0.01 db and the stopband attenuation as-90 db to construct a second-order CIC model; but since the input signal sampling rate is reduced by 8 times, the second-stage CIC generation order is increased to 9 th order. The output power signal to noise ratio is shown in fig. 5.

The product form transformation is performed on the formula 1, so that as shown in the formula (2), taking n=5 as an example, fig. 6 shows a circuit implementation structure. Firstly, an adder and a register feedback path are used as a basic integral structure unit to carry out circuit encapsulation, secondly, a decimator is subjected to encapsulation design, and finally, an addition of a differentiator and a register are subjected to encapsulation design, and the RTL implementation strategy of the two-stage CIC filter is realized according to the method.

Because the weight per coefficient of each step of the CIC filter is 1, the multiplier DSP resource is not needed, the downsampling task and the filtering work can be realized at low resource consumption, and the task can be completed in a smaller order and smaller area than the direct connection type FIR, so that the CIC filter has considerable resource saving characteristic.

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The Russian feedback accumulation operation performed by the integrator part can lead to the increase of the data bit width, and the unreasonable word length setting of the internal register and the full adder can cause operation overflow to cause output error signals. In theory, the internal maximum word length Bcic should satisfy the relation of formula (3) to ensure stable operation of the system, where Bin represents the input word length, and N and Ds represent the order and the extraction multiple, respectively. Thus, according to the reasoning of the formula, the first stage 4-order 8-times pump and the second stage 9-order 8-pump Hcic transmission word lengths are set to 13 and 40 respectively.

Bcic＝Bin+N*log ₂ (D-1) formula (3)

Firstly, a CIC extraction filter which is passed by MATLAB verification design is used for mapping a first-stage CIC algorithm to Verilog realization according to the RTL design. Secondly, preparing circuit verification platform test data, and storing a txt text format of an output signal (256 Khz one-bit data stream) of a Sigma-Delta modulator on MATLAB. Then writing a testbench test platform, instantiating a target top-layer file, and inputting simulated real signal txt text data derived by MATLAB into CIC bit by bit as a test vector set; finally, leading the first-stage and RTL and testbench files into a Modelsim for front-end simulation verification, carrying out simulation test, leading out 16-system data into another output vector text, and automatically converting the output 16-system vector text into a 10-system vector text by designing a script program in order to improve experimental efficiency, wherein the system is changed but the length is unchanged, so that the design of a circuit and the extraction of basic verification data are completed once. The second-stage CIC design strategy is the same as the first-stage CIC, but the data vectors are subjected to cascade superposition based on the first-stage CIC during testing, the vector data of the testing platform are modified, and the 10-system format text of the testing result is obtained to be analyzed by an algorithm.

The signal-to-noise ratio analysis is carried out on the first-stage CIC RTL output signal, the result is shown in fig. 7, the output power signal-to-noise ratio is 111.6489db, and the power signal-to-noise ratio is 116.2326db close to the modeling output power; and then, the signal-to-noise ratio analysis is carried out on the second-stage CIC RTL output signal, and the result is shown in fig. 8, wherein the output power signal-to-noise ratio is 88.3322db and is close to the power signal-to-noise ratio 89.4157db of the modeling output.

1.3 half-band filter design

The half-band filter is a relatively special direct FIR low-pass filter, wherein among fixed multiplication coefficients, even coefficients are 0, odd coefficients are not 0, and coefficients which are not 0 are consistent with the symmetry of the coefficients of the FIR in the HalfBand. The coefficient of halfpad is only 1/4 of its order and the channel frequency of halfpad is close to half the normalized frequency. The halfpad passband ripple is smaller and has a certain upturned trend, so the system mainly considers the rejection ratio of the halfpad to the stopband and the transition band.

As a final filter, other noise should be avoided as much as possible, for which reason the rejection ratio should be sufficiently large, and the transition band should be greatly attenuated to approach the ideal state as much as possible, so the design parameters are: the input sampling rate is 4KHz, the extraction rate is 2 times, the passband is 0.5KHz, the stopband is 1.5KHz, the passband ripple is +/-0.01 db, the stopband attenuation is 80db, the algorithm modeling is carried out through MATLAB, and the HalfBand amplitude frequency response is shown in figure 9.

Modeling by MATLAB can obtain a differential transfer topological graph like that of FIG. 10, and RTL design is performed based on the algorithm behavior level, and is divided into: the 2-time speed decimator, the delay multiplication and addition unit and the first-stage adder insert circuit. In order to improve the performance adaptation degree of the system, the multiplier IP is designed autonomously, and the characteristic is that the parallelism of single-side fixed coefficients and multiplication shift addition is achieved, and verification is passed.

Multiple speed cascade and joint verification analysis

(1) Top layer cascading

And carrying out top-level cascading design on each module based on an algorithm modeling architecture and an RTL digital circuit system passing verification, wherein an RTL design link diagram is shown in FIG. 11. The signal output power under the ideal state of the MATLAB algorithm modeling platform is shown in figure 12, the power signal to noise ratio reaches 124.4647db, the effective word length is 20.3828bits, the ideal system performance meets the design requirement, and the system has certain noise suppression advantages.

(2) Cascaded RTL verification analysis

Aiming at the characteristics of the cascaded digital decimation filter, a testbench verification platform is designed to analyze the actual performance of a circuit, an excitation vector outputs a 50s real signal by using a Sigma-Delta modulator of a modeling platform single-ring four-order CIFB architecture, and the specific implementation method is the same as that of a CIC module.

The output waveform is substantially free of noise, as shown in fig. 13, through simulation verification analysis. The output signal of the circuit is poured into a Matlab evaluation script platform, the signal-to-noise ratio of the output power is 124.374db and is close to the signal-to-noise ratio 124.4647db of the output power of an ideal platform, the word length 20.3678 is also close to 20.3828bits in an ideal state, and the design requirement is met, as shown in fig. 14.

The cascade digital decimation filter provided by the invention has the characteristic advantages of low-pass filtering, decimation, anti-aliasing, high fidelity and low cost, and can be applied to a high-precision analog-to-digital conversion circuit. The system is applied to the output signal processing of a Sigma-Delta modulator of a single-ring four-order CIFB type framework of an associated project at present, and the post test after flow sheet shows that the design of the cascaded digital decimation filter achieves the expected target.

The present embodiment is only illustrative of the present patent and does not limit the scope of protection thereof, and those skilled in the art can make local changes thereto, and the present patent is regarded as equivalent replacement thereof as long as the present patent does not exceed the spirit of the present patent, and the present patent is within the scope of protection.

Claims

1. The CIC-HB cascading digital filter is characterized by being obtained by cascading a two-stage CIC module and a one-stage HB module, wherein the first stage is a four-order eight-time CIC module, the second stage is a nine-order eight-time CIC module, and the third stage is a ten-order two-time HB module.

2. The verification method of the CIC-HB cascade digital filter is characterized in that the verification method of the fourth-order eight-time extraction CIC module is characterized in that algorithm modeling is conducted based on a MATLAB platform, the extraction rate D is set to be 8, the passband cutoff frequency is 1KHz, the stopband initial frequency is 2KHz, the passband ripple is +/-0.01 db and the stopband attenuation is-90 db, and a first-order CIC model is built.

3. The verification method of the CIC-HB cascade digital filter is characterized in that the verification method of the nine-order eight-time extraction CIC module is characterized in that algorithm modeling is conducted based on an MATLAB platform, the extraction rate D is set to be 8, the passband cutoff frequency is 1KHz, the stopband initial frequency is 2KHz, the passband ripple is +/-0.01 db and the stopband attenuation is-90 db, and a second-order CIC model is built.

4. The verification method of the CIC-HB cascade digital filter is characterized in that the verification method of the tenth-order double-extraction HB module is characterized in that the input sampling rate is 4KHz, the extraction rate is 2 times, the passband is 0.5KHz, the stop band is started at 1.5KHz, the passband ripple is +/-0.01 db, the stop band attenuation is 80db, and algorithm modeling is carried out through MATLAB.