CN113300795A

CN113300795A - Frequency spectrum monitor

Info

Publication number: CN113300795A
Application number: CN202110553305.5A
Authority: CN
Inventors: 代伟; 冯晓东; 王曲; 林波
Original assignee: Chongqing Huiling Electron New Technology Co ltd
Current assignee: Chongqing Huiling Electron New Technology Co ltd
Priority date: 2021-05-20
Filing date: 2021-05-20
Publication date: 2021-08-24
Anticipated expiration: 2041-05-20
Also published as: CN113300795B

Abstract

The invention discloses a spectrum monitor, which comprises an amplitude limiter, wherein the amplitude limiter is connected with a first program-controlled attenuator, the first program-controlled attenuator is connected with a sub-octave preselection filter bank through a first single-pole multi-throw switch, the sub-octave preselection filter bank is connected with a first low-noise amplifier through a second single-pole multi-throw switch, the first low-noise amplifier is connected with a first mixer through a first low-pass filter, the first mixer is connected with a second low-noise amplifier through a first filter, the second low-noise amplifier is connected with a second mixer through a second filter, the second mixer is connected with a band-pass filter through a second program-controlled attenuator, the band-pass filter is connected with a second low-pass filter through a third low-noise amplifier, and the second low-pass filter is connected with an ADC (analog to digital converter) through an operational amplifier. The first programmable attenuator and the second programmable attenuator are respectively used for performing adjustable attenuation control aiming at a radio frequency band and a medium frequency band, and the adjustment dynamic range of the product is larger.

Description

Frequency spectrum monitor

Technical Field

The invention relates to the technical field of communication equipment, in particular to a frequency spectrum monitor.

Background

Application No. 201620944832.3, grant publication No.: CN 206041984U; the invention name is as follows: a universal microwave frequency converter; this patent discloses the following:

the invention discloses a universal microwave frequency converter, which comprises:

the local oscillator power division amplifying module is composed of a power divider and an amplifier connected with the output end of the power divider, and is used for dividing the input local oscillator signals required by frequency conversion into two paths, and then amplifying the two paths of local oscillator signals and respectively providing the amplified local oscillator signals to the local oscillator ends of the up-conversion mixer and the down-conversion mixer;

the down channel module is formed by connecting a coupler, an amplitude limiter, an amplifier, a 3dB fixed attenuator, a switch selector, a 31dB/1dB step attenuator, an amplifier, a 3dB fixed attenuator, a down-conversion mixer and an amplifier together in sequence, and is used for carrying out frequency spectrum shifting on a received microwave signal and then converting the microwave signal into a received intermediate frequency signal;

the receiving front end mainly realizes that an antenna receiving signal is coupled and divided into a main path and a coupling branch path, the main path signal possibly has a large signal due to antenna receiving, an amplitude limiter is required to be added to carry out amplitude limiting on the large signal, a rear end device is protected, the anti-burning capacity of a frequency converter is improved, then, radio frequency signals are subjected to low noise amplification, and then, the main path signal and the coupling branch path signal are subjected to switch selection, attenuation amplification processing is carried out after the switch selection, the total attenuation value of the attenuator is designed to be 31Db, 1dB stepping is realized, and thus the linear dynamic range of the receiving signal can be improved.

Secondly, downlink frequency mixing:

the downlink mixing moves the radio frequency signals processed by the radio frequency receiving front end to the intermediate frequency through a down-conversion mixer, the intermediate frequency signals after frequency conversion are subjected to amplitude amplification and then output, and the intermediate frequency signals are extracted to an intermediate frequency processing unit for use according to a corresponding intermediate frequency third band-pass filter accessed to the outside of the intermediate frequency range after output. The microwave frequency converter can be applied to any equipment with down-conversion requirement by externally connecting intermediate frequency filters with various frequency bands.

Therefore, the prior art has the defects that the 3dB fixed attenuator and the 31dB/1dB step attenuator are combined to adjust the radio frequency signal and the intermediate frequency signal, the attenuation control is carried out on the input signal, and the fixed attenuator used at the radio frequency front end cannot be adjusted, so that the adjustable dynamic range of the product is smaller.

Disclosure of Invention

In view of at least one of the drawbacks of the prior art, an object of the present invention is to provide a spectrum monitor, in which a first programmable attenuator and a second programmable attenuator are respectively used for attenuation control that can be adjusted for a radio frequency band and a medium frequency band, an adjustment dynamic range of a product is large, and second-order intermodulation suppression is improved by suppressing a sub-octave point and an octave point through a sub-octave preselection filter group.

In order to achieve the purpose, the invention adopts the following technical scheme: the spectrum monitor is characterized by comprising an amplitude limiter, wherein a signal input end of the amplitude limiter is used for being connected with a radio frequency interface, a signal output end of the amplitude limiter is connected with a first program-controlled attenuator, the first program-controlled attenuator is connected with an input end group of a sub-octave preselection filter group through a first single-pole multi-throw switch, an output end group of the sub-octave preselection filter group is connected with a signal input end of a first low-noise amplifier through a second single-pole multi-throw switch, a signal output end of the first low-noise amplifier is connected with a first signal input end of a first mixer through a first low-pass filter, a second signal input end of the first mixer is connected with a first local oscillator, a signal output end of the first mixer is connected with a signal input end of a second low-noise amplifier through a first band-pass filter, a signal output end of the second low-noise amplifier is connected with a first signal input end of a second mixer through a second band-pass filter, the second signal input end of the second frequency mixer is connected with a second local oscillator, the signal output end of the second frequency mixer is connected with the signal input end of a third band-pass filter through a second programmable attenuator, the signal output end of the third band-pass filter is connected with the signal input end of a second low-pass filter through a third low-noise amplifier, and the signal output end of the second low-pass filter is connected with an ADC (analog-to-digital converter) through an operational amplifier.

The ADC converter is connected with a digital processor.

The digital processor is also connected with the first program-controlled attenuator, the first single-pole multi-throw switch, the second single-pole multi-throw switch and the second program-controlled attenuator.

The spectrum monitor has the remarkable effects that the first programmable attenuator and the second programmable attenuator are used for respectively carrying out adjustable attenuation control on a radio frequency band and a medium frequency band, the adjustment dynamic range of a product is large, and the second-order intermodulation suppression is improved through the suppression of a sub-octave preselection filter group on a sub-octave and an octave point.

Drawings

FIG. 1 is a circuit block diagram of the present invention;

FIG. 2 is a flow chart of a storage method of the present invention;

FIG. 3 is a circuit diagram of the RF front end;

FIG. 4 is a flow chart of gain control of the digital processor;

FIG. 5 is a view of the housing structure of the present invention;

FIG. 6 is a perspective view of the outer shape of the housing of the present invention;

FIG. 7 is a layout diagram of electrical components on the upper surface of the first PCB board;

fig. 8 is a layout view of electrical components on the lower surface of the first PCB.

Detailed Description

The invention is described in further detail below with reference to the figures and specific examples.

As shown in fig. 1-8, a storage method of a spectrum monitor is used for the spectrum monitor, the spectrum monitor includes an ARM embedded device, and the ARM embedded device is connected with a memory; the memory is provided with a frequency spectrum data buffer area, a queue buffer area and a statistic buffer area;

the ARM embedded device acquires monitoring data and stores the monitoring data in a memory, and comprises the following steps:

step A: the ARM embedded device acquires monitoring data, and if the monitoring data is frequency spectrum data, the step B is switched to; if the monitoring data is IQ data or audio/demodulation data, turning to step C; if the monitoring data is statistical data, turning to step D;

and B: the ARM embedded device stores the current spectrum data into a spectrum data cache region; replacing the spectrum data before the spectrum data buffer area; returning to the step A;

and C: monitoring the free storage space of the corresponding queue buffer area by the ARM embedded device, and if the capacity of the free storage space can accommodate the current IQ data or audio/demodulation data, turning to the step D; if the capacity of the free storage space is not enough to accommodate the current IQ data or audio/demodulation data, turning to step E;

step D: the ARM embedded device stores IQ data or audio/demodulation data in a free storage space in sequence; returning to the step A;

step E: the ARM embedded device removes data from the head of the queue buffer, the length of the removed data is equal to that of current IQ data or audio/demodulation data, then, the rest historical IQ data or audio/demodulation data are moved forward, and the current IQ data or audio/demodulation data are sequentially stored in an idle storage space; returning to the step A;

step F: and if the monitoring data is statistical data, sampling through a sampling algorithm, storing in a statistical cache region, and returning to the step A. The ARM embedded device is provided with a microprocessor. The ARM embedded device is connected with a subsequent host, and the subsequent host can call data from the ARM embedded device when needed.

The data in the queue buffer area is stored from beginning to end in sequence, and the data acquired later is stored at the tail of the data acquired earlier. If the data in the queue buffer is not full, the tail part of the queue buffer is free storage space.

In general spectrum monitoring, frequency spectrum data, ITU measurement data, IQ data, demodulation/audio data and statistical data are mainly considered, wherein IQ data and demodulation/audio data are expected to have certain continuity so as to meet the requirement of subsequent service, and other data can be sampled and stored.

One path of the IQ signal is called an I path, and the other path is called a Q path, and the IQ signal and the Q path are two paths of orthogonal signals.

The key of the storage method of the spectrum monitoring device is that the queue buffer area is divided into an IQ data queue buffer area and an audio/demodulation data queue buffer area, the IQ data queue buffer area is used for storing IQ data, and the audio/demodulation data queue buffer area is used for storing audio/demodulation data; the statistical data are divided into ITU data and occupancy rate data, the statistical cache region is divided into an ITU statistical cache region and an occupancy rate statistical cache region, and the ITU statistical cache region is used for storing the ITU data; and the occupancy rate counting cache region is used for storing the occupancy rate data.

In the step F, if the statistical data is ITU data, the sampling algorithm adopts a logarithm extraction algorithm; and if the statistical data are the occupancy rate data, the sampling algorithm adopts an average sampling algorithm.

The size of the frequency spectrum data is related to the frequency spectrum scanning range and the frequency resolution, the scanning range of the frequency spectrum monitoring device is 20MHz to 2500MHz, the minimum frequency resolution is 1KHz, and the storage capacity of each frequency point is 2 bytes (2: (_sh_ort type); (2500-20) × 1000KHz/1KHz × 2 ═ 4960000 bytes;

the number of the frequency spectrum data is N1, and the length of N1 is 4 bytes; each spectrum data is 2 bytes in length; the storage capacity of the spectrum data buffer is 5 MB. N1 is equal to 2480000 in this embodiment.

The (2500-20) × 1000(KHz)/1(KHz) × 2 is 4960000 bytes, so the storage size of the spectrum data buffer is set to 5MB, and the storage format is: data length N1(4 bytes) data 1(2 bytes) data 2(2 bytes).. data N1(2 bytes).

The data length of each sampling point of the IQ data is 2 bytes in an I path and 2 bytes in a Q path, and the data length is 4 bytes in total; the IQ data uses the integer multiple data of 1024 for subsequent analysis or processing, and the storage of the IQ data adopts a 1024 × 4 × n mode for storage; the size of n depends on the minimum continuous IQ data point number requirement required by subsequent analysis or processing, the maximum value of n is 1000, and the storage capacity of the IQ data queue buffer is 5 MB. n is an integer multiple.

The size of n depends on the minimum continuous IQ data point number requirement required by subsequent services, in the general monitoring module, the maximum value of planning n is 1000, namely the storage size of IQ data is 4096000B, the maximum value of a planning IQ storage area is 5MB, and the storage format is as follows:

number of data n	Data	1	Data 2	......	Data n
						4 bytes	4 bytes	4 bytes	...	4 bytes

TABLE 1

The audio/demodulation data is stored by adopting a PCM format with 16 bits, single sound channel and 8000 sampling rates, the data length of each sampling point is 2 bytes, and the data volume per second is 8000 multiplied by 2 multiplied by 1 which is 16 KB; the maximum buffer 1 minute of audio/demodulation data is designed to be used for analyzing and processing subsequent services, the maximum audio/demodulation data storage amount is 16 Kx 60 ═ 960KB data, and the capacity of the audio/demodulation data queue buffer area is 1 MB.

The storage format is shown in table 2:

number of data N4	Data	1	Data 2	......	Data N4
						4 bytes	2 bytes	2 bytes	......	2 bytes

TABLE 2

The ITU measurement data is stored in a statistical storage mode, N2 groups of values are stored every hour, N2 is more than or equal to 1 and less than or equal to 60, and historical ITU measurement data are stored in a hard disk; the ITU measurement data includes center frequency, bandwidth (xdB bandwidth and β bandwidth), power, AM modulation depth, and FM modulation frequency offset, and the data capacity of each ITU measurement storage unit is set to 200B, the maximum data amount of 1 hour of ITU measurement data is 8+1+60 × 200 ═ 12009B, the maximum storage space is 12009 × 24 ═ 288216B, and therefore the storage space capacity of the ITU statistics buffer is 500 KB.

Considering the compatibility of signal measurement parameters, the data volume of each ITU measurement unit is designed to be 200B, and the storage format is planned as table 3:

TABLE 3

The occupancy rate data adopts a statistical storage mode, N3 groups of values are stored every hour, and N3 is more than or equal to 1 and less than or equal to 6; each time there are M channels counted, the value of M being related to the scanning range and the frequency resolution, the value of M being:

2480000 channels of (2500-20) multiplied by 1000KHz/1KHz, and storing the historical occupancy rate data into a hard disk; occupancy data 1 hour maximum data volume is: 8+1+4+2 × 2480000 × 6 ═ 29760013B, the maximum 24-hour data is reserved, the data volume of 29760013 × 24 × 1 ═ 714240312B is needed, and the storage space capacity of the occupancy rate statistic buffer area is 1 GB.

According to the maximization requirement of the general monitoring module, the value of M is (2500-20) multiplied by 1000(KHz)/1(KHz) which is 2480000 channels in total, and the historical occupancy rate data is stored in the hard disk. The occupancy data storage format is as shown in table 4:

TABLE 4

In summary, the storage is divided into three ways, one is real-time replacement data caching, and the method is adopted for the spectrum data; firstly, caching in a real-time queue mode, wherein IQ data and audio data adopt the method, after the queue is full, the data at the head of the queue is removed, and new data is inserted at the tail of the queue; the last one is a sampling buffer mode, and buffer data is required to be written into a hard disk under certain conditions, and ITU measurement data and occupancy rate data adopt the method.

The hard disk storage area is divided as shown in table 5:

TABLE 5

The storage processing flow is shown in the attached figure 2 of the specification.

1. After the system parameter command is issued, buffer allocation can be performed according to the specific content of the parameter.

2. After the spectrum data in the monitoring data is transmitted, the previous spectrum data is directly replaced in the corresponding spectrum data buffer area.

3. IQ data, audio/demodulation data and the like in the monitoring data need to have a certain number of data continuous requirements, after the IQ data, the audio/demodulation data and the like are transmitted, free space monitoring is carried out on a corresponding buffer queue, and if the free space can contain the current data, the data is directly added behind a buffer area; if the free space is not enough to accommodate the current data, the data at the head of the queue is removed until the free space is enough to accommodate the current data, and then the data is appended at the tail of the queue. In consideration of performance, it is better to adopt a circular queue for the queue.

4. Statistical data of the processed monitoring data, such as: occupancy, ITU measurement data, etc. The sampling can be carried out, and then the sampling is buffered and stored in a hard disk according to a disk storage strategy, so that the sampling can be acquired by an external system at any time.

The sampling strategy can adopt a plurality of implementation methods such as logarithmic extraction, average extraction and the like, the logarithmic extraction has the advantages that enough data can be quickly acquired, and the stabilized data is only used as reference, such as ITU measurement data.

The average extraction is processed according to time, such as extracting result data 4 times per hour and extracting every 15 minutes; the advantage of the average extraction is that statistical data within a specified time range, such as 0-15 minutes of statistical results, 15-30 minutes of statistical results, etc., can be obtained; the method is suitable for processing occupancy data.

The ARM embedded device is connected with a digital processor, and the digital processor is connected with a radio frequency front end.

The radio frequency front end comprises an amplitude limiter, the signal input end of the amplitude limiter is used for connecting a radio frequency interface, the signal output end of the amplitude limiter is connected with a first program-controlled attenuator, the first program-controlled attenuator is connected with the input end group of a sub-octave preselection filter group through a first single-pole multi-throw switch, the output end group of the sub-octave preselection filter group is connected with the signal input end of a first low noise amplifier through a second single-pole multi-throw switch, the signal output end of the first low noise amplifier is connected with the first signal input end of a first mixer through a first low pass filter, the second signal input end of the first mixer is connected with a first local oscillator, the signal output end of the first mixer is connected with the signal input end of a second low noise amplifier through a first band pass filter, the signal output end of the second low noise amplifier is connected with the first signal input end of a second mixer through a second band pass filter, the second signal input end of the second mixer, the signal output end of the second frequency mixer is connected with the signal input end of a third band-pass filter through a second program-controlled attenuator, the signal output end of the third band-pass filter is connected with the signal input end of a second low-pass filter through a third low-noise amplifier, and the signal output end of the second low-pass filter is connected with an ADC (analog-to-digital converter) through an operational amplifier; the ADC converter is connected with a digital processor; the digital processor is also connected with the first program-controlled attenuator, the first single-pole multi-throw switch, the second single-pole multi-throw switch and the second program-controlled attenuator;

the method comprises the following steps:

step A1: the digital processor acquires an input signal through the ADC;

step B1: the digital processor judges whether the input signal power is within the full range, if so, the step C1 is carried out, otherwise, the step I1 is carried out;

if the input signal power is greater than the full range, the signal overflow flag is valid;

step C1: the digital processor calculates the absolute value of the amplitude of the input signal;

step D1: the digital processor looks up a table to obtain the power corresponding to the amplitude absolute value;

step E1: the digital processor judges whether the power is larger than or equal to the set power tolerance, if so, the step F1 is carried out; if not, go to step H1;

step F1: finishing gain control, outputting a signal, and returning to the step A1;

step H1: the digital processor judges whether the attenuation value is minimum, if yes, go to step F1; if not, go to step I1;

step I1: the digital processor controls the attenuation of the attenuation value from the minimum value and gradually increases the attenuation value in a stepping manner;

the step I1 is that the digital processor starts attenuation control from the minimum value, for example, attenuation is first performed by 1db, the step B1 is returned, whether the input signal power is within the full range is determined, if yes, the step C1 is returned, otherwise, the attenuation value is increased step by step, for example, attenuation is performed by 2 db, the step B1 is returned, whether the input signal power is within the full range is determined, if yes, the step C1 is returned, otherwise, the attenuation value is increased step by step again, for example, attenuation is performed by 3db, attenuation is performed by 4 db … …, and the like, and the attenuation amount is gradually increased, so that the input signal power is smaller and smaller until the input signal power is within the full range.

The full scale corresponds to an upper power limit and the power margin corresponds to a lower power limit.

When a program is written, the attenuation value is stored in a variable storage unit, the value of the variable storage unit is set as the minimum value of the attenuation amount when the program circulates for the first time, and the value of the variable storage unit is controlled to increase step by step when the program circulates once every time;

step J1: the digital processor waits for the gain control to be completed; return to step B1.

The digital processor controls the first program-controlled attenuator, the first single-pole multi-throw switch, the second single-pole multi-throw switch and the second program-controlled attenuator through the FPGA device.

Automatic Gain Control (AGC), i.e., the Automatic attenuation Control described in the present invention, means to Control a signal in a relatively stable output state according to the strength of an input signal.

The scheme adopts a mode of dynamically adjusting radio frequency attenuation to stabilize the level of the input digital front end within a reasonable range (namely within a full range). The common AGC control is completed by an AGC control chip, but the scheme completes the control of gain (namely attenuation) through an FPGA, and dynamically adjusts the radio frequency gain (namely attenuation) value by detecting the relation between the amplitude and the full-scale range of the input signal of the ADC converter, so that the signal acquired by the ADC converter is controlled in a relatively stable range.

The control flow is illustrated as follows:

the AGC control flow can control signals within a full range in a mode of increasing attenuation when the input signals are too large, and can also carry out dynamic control according to dynamic changes of the power of the input signals, namely, the signals are adjusted in real time in the working process, the attenuation is increased when the input signals are too large, and the attenuation is reduced when the input signals are too small, so that the signals are controlled at a proper sampling level.

It can be seen from the flow chart that when the input signal is too large or too small, the control flows are basically consistent, two control flows are not required, only the power of the input signal and the overflow flag need to be judged, and the control flows are simplified. When the power of the input signal is greater than the full scale, the overflow flag is valid, and when the power of the input signal is less than or equal to the full scale, the overflow flag is invalid.

When a large signal is input, gradually increasing the attenuation amount from the minimum attenuation amount until the signal is controlled within the full range;

when small signals are input, whether the signal amplitude is too small is judged according to the signal amplitude and an AGC (automatic gain control) adjustment threshold, if the signal amplitude is smaller than the minimum threshold, a power margin is set, the attenuation value can be properly reduced when the signal power is low, and if the signal power is larger than or equal to the minimum threshold, the signal power is within an acceptable range, and the current attenuation is proper.

As can be seen from the above control flow, the attenuation is controlled from the minimum attenuation amount regardless of whether the input signal is too large or too small.

If the signal is too large, gradually increasing the attenuation from the minimum attenuation position until the signal power is controlled within the full range, if the signal is too small, firstly maximizing the signal from the minimum attenuation position, and if the signal power is too large at the moment, the control flow is consistent with that when a large signal is input, and gradually increasing the attenuation until the signal is within the full range.

If the attenuation is set to be the minimum and the signal power is still small, the attenuation is not controlled any more, which means that the signal is too small and exceeds the control range.

The automatic gain control algorithm can meet the power control of various modulation (AM, FM, SSB and the like) input signals, and when the signals are too large or too small, the radio frequency gain (attenuation) can be controlled by using the same control flow only through simple control sentences, so that the convergence time is short, and the control precision is high.

In the step I, when attenuation is controlled, the second programmable attenuator is used for controlling attenuation, and when the attenuation of the second programmable attenuator reaches the maximum control amount, the first programmable attenuator is used for controlling attenuation.

The radio frequency interface is connected with a radio frequency antenna and inputs radio frequency signals.

1. An amplitude limiter: the amplitude limitation of the high-power signal is completed, and the burning resistance of the product is improved;

2. the first programmable attenuator and the second programmable attenuator respectively perform attenuation control aiming at a radio frequency band and a medium frequency band, so that a product is guaranteed to realize a large dynamic range, and the signal can be ensured to work in a linear region by adjusting attenuation under the condition of a large input signal; when the attenuation is controlled, the intermediate frequency attenuator, namely the second programmable attenuator is controlled firstly, and when the intermediate frequency attenuator reaches the maximum control quantity, the radio frequency attenuator, namely the first programmable attenuator is controlled again.

3. A sub-octave preselection filter bank: through the suppression of the filter on the point of the sub-frequency range and the point of the octave, a better second-order input intercept point is realized, and the second-order intermodulation suppression is improved.

The product is used for the electromagnetic spectrum investigation and perception of the system communication frequency band and can be used for covering signals with the frequency band of 20 MHz-2500 MHz. The method mainly completes the filtering, amplification and radio frequency acquisition of signals.

The whole link comprises 4 amplifying devices including a first low noise amplifier, a second low noise amplifier, a third low noise amplifier and an operational amplifier, and a good gain effect can be achieved.

The digital processor is also used for processing digital baseband signals, forming frequency spectrums and the like, and reporting results.

The digital processor is connected with the first single-pole multi-throw switch and the second single-pole multi-throw switch and can control the first single-pole multi-throw switch and the second single-pole multi-throw switch to act so as to select the corresponding filter of the sub-octave preselection filter group.

When the digital processor controls attenuation, the second programmable attenuator can perform attenuation control on the intermediate frequency signal, and the second programmable attenuator can perform attenuation control on the radio frequency signal.

The frequency of the first local oscillator is 3490-5960 MHz, and the frequency of the second local oscillator is 3560 MHz.

The digital processor controls the first program-controlled attenuator, the first single-pole multi-throw switch, the second single-pole multi-throw switch and the second program-controlled attenuator through the FPGA device. An FPGA is a field programmable gate array.

FPGA (field Programmable Gate array) is a product of further development on the basis of Programmable devices such as PAL, GAL and the like. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.

As shown in fig. 6-8, the spectrum monitor further includes a housing 1 made of metal, the housing 1 is rectangular, the upper and lower ends of the housing 1 are open, a partition plate 13 is integrally formed in the housing 1, the partition plate 13 divides the housing 1 into an upper chamber 11 and a lower chamber 12, the upper chamber 11 is detachably provided with a first PCB 2, and the lower chamber 12 is detachably provided with a second PCB 13; the partition plate 13 is provided with a lead through hole;

the wire through-holes facilitate the electrical components connecting the upper and

lower chambers

11 and 12 by wires.

The amplitude limiter, the first program-controlled attenuator, the first single-pole multi-throw switch, the sub-octave preselection filter bank, the second single-pole multi-throw switch, the first low-noise amplifier, the first low-pass filter, the first frequency mixer, the first local oscillator, the first band-pass filter, the second low-noise amplifier and the second band-pass filter are arranged on the upper surface of the first PCB 2;

the second frequency mixer, the second local oscillator, the second program-controlled attenuator, the third band-pass filter, the third low-noise amplifier, the second low-pass filter and the operational amplifier are arranged on the lower surface of the first PCB 2;

the upper chamber 11 is provided with a cover plate 4, the cover plate 4 covers an upper end opening of the upper chamber 11, and the cover plate 4 is detachably connected with the shell 1;

the ADC, the digital processor and the ARM embedded device are arranged on the second PCB 13; the ARM embedded device is connected with a data interface;

the radio frequency interface and the data interface penetrate out of the shell 1.

The housing 1 has a substantially rectangular parallelepiped shape.

The cover plate 4 is made of stainless steel, so that heat dissipation is facilitated and grounding is achieved. The lower chamber 12 is provided with a heat radiation fan and heat radiation holes, which is convenient for the heat radiation of the ADC converter, the digital processor and the ARM embedded device.

Preferably, the ARM embedded device is connected with a wireless communication module, and can be connected with an upper computer or other spectrum monitoring devices through the wireless communication module, so that large-area arrangement and network establishment are facilitated.

The radio frequency interface is also grounded via a lightning protection circuit. The lightning protection circuit is a lightning arrester, and prevents an external antenna from introducing overvoltage through a radio frequency interface to damage an internal circuit.

The lower surface of the first PCB board 2 is also provided with a power supply control unit which supplies power for the circuit elements.

In the prior art, the radio frequency front end, the ADC, the digital processor and the ARM embedded device are arranged in different shells, and the integrated structure is adopted, so that the size of the whole spectrum monitor is favorably reduced, and the product integration is favorably realized.

Finally, it is noted that: the above-mentioned embodiments are only examples of the present invention, and it is a matter of course that those skilled in the art can make modifications and variations to the present invention, and it is considered that the present invention is protected by the modifications and variations if they are within the scope of the claims of the present invention and their equivalents.

Claims

1. A spectrum monitor is characterized by comprising an amplitude limiter, wherein a signal input end of the amplitude limiter is used for being connected with a radio frequency interface, a signal output end of the amplitude limiter is connected with a first program-controlled attenuator, the first program-controlled attenuator is connected with an input end group of a sub-octave preselection filter group through a first single-pole multi-throw switch, an output end group of the sub-octave preselection filter group is connected with a signal input end of a first low-noise amplifier through a second single-pole multi-throw switch, a signal output end of the first low-noise amplifier is connected with a first signal input end of a first mixer through a first low-pass filter, a second signal input end of the first mixer is connected with a first local oscillator, a signal output end of the first mixer is connected with a signal input end of a second low-noise amplifier through a first band-pass filter, a signal output end of the second low-noise amplifier is connected with a first signal input end of a second mixer through a second band-pass filter, the second signal input end of the second frequency mixer is connected with a second local oscillator, the signal output end of the second frequency mixer is connected with the signal input end of a third band-pass filter through a second programmable attenuator, the signal output end of the third band-pass filter is connected with the signal input end of a second low-pass filter through a third low-noise amplifier, and the signal output end of the second low-pass filter is connected with an ADC (analog-to-digital converter) through an operational amplifier.

2. The spectrum monitor as set forth in claim 1, wherein: the ADC converter is connected with a digital processor.

3. The spectrum monitor as set forth in claim 2, wherein: the digital processor is also connected with the first program-controlled attenuator, the first single-pole multi-throw switch, the second single-pole multi-throw switch and the second program-controlled attenuator.

4. The spectrum monitor as set forth in claim 2, wherein: the PCB packaging structure is characterized by further comprising a shell (1) made of metal, wherein the shell (1) is rectangular, the upper end and the lower end of the shell (1) are open, a partition plate (13) is integrally formed in the shell (1), the shell (1) is divided into an upper cavity (11) and a lower cavity (12) by the partition plate (13), a first PCB (2) is detachably arranged in the upper cavity (11), and a second PCB (13) is detachably arranged in the lower cavity (12); the partition plate (13) is provided with a lead through hole;

the amplitude limiter, the first program-controlled attenuator, the first single-pole multi-throw switch, the sub-octave preselection filter bank, the second single-pole multi-throw switch, the first low-noise amplifier, the first low-pass filter, the first frequency mixer, the first local oscillator, the first band-pass filter, the second low-noise amplifier and the second band-pass filter are arranged on the upper surface of the first PCB (2);

the second frequency mixer, the second local oscillator, the second program-controlled attenuator, the third band-pass filter, the third low-noise amplifier, the second low-pass filter and the operational amplifier are arranged on the lower surface of the first PCB (2);

the upper chamber (11) is provided with a cover plate (4), and the cover plate (4) is detachably connected with the shell (1);

the ADC converter and the digital processor are arranged on the second PCB (13);

the radio frequency interface penetrates out of the shell (1).

5. The spectrum monitor as set forth in claim 2, wherein an ARM embedded device is coupled to the digital processor, the ARM embedded device having a memory coupled thereto.

6. The control method of a spectrum monitor according to claim 5, wherein the memory is provided with a spectrum data buffer, a queue buffer and a statistics buffer;

step F: and if the monitoring data is statistical data, sampling through a sampling algorithm, storing in a statistical cache region, and returning to the step A.

7. The method as claimed in claim 6, wherein the queue buffer is further divided into an IQ data queue buffer for storing IQ data and an audio/demodulation data queue buffer for storing audio/demodulation data; the statistical data are divided into ITU data and occupancy rate data, the statistical cache region is divided into an ITU statistical cache region and an occupancy rate statistical cache region, and the ITU statistical cache region is used for storing the ITU data; and the occupancy rate counting cache region is used for storing the occupancy rate data.