CN104078517B - Groove type schottky semiconductor device - Google Patents
Groove type schottky semiconductor device Download PDFInfo
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- CN104078517B CN104078517B CN201410349022.9A CN201410349022A CN104078517B CN 104078517 B CN104078517 B CN 104078517B CN 201410349022 A CN201410349022 A CN 201410349022A CN 104078517 B CN104078517 B CN 104078517B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 230000004888 barrier function Effects 0.000 claims abstract description 14
- 239000002184 metal Substances 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 20
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 241000790917 Dioxys <bee> Species 0.000 claims 1
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 3
- 238000007254 oxidation reaction Methods 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 2
- 230000005684 electric field Effects 0.000 description 16
- 230000000903 blocking effect Effects 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
- H01L29/8725—Schottky diodes of the trench MOS barrier type [TMBS]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a groove type schottky semiconductor device. In the device, a conductive polycrystalline silicon body is embedded in a bar groove, wherein a polycrystalline silicon middle lower part positioned at the middle lower part of the conductive polycrystalline silicon body is positioned in the bar groove; a first silicon oxide oxidation layer is arranged between an epitaxial layer and the polycrystalline silicon middle lower part; a second conductive type doping area is positioned in a polycrystalline silicon lug boss and arranged on the side surfaces of the periphery of the groove; a heavy doping second conductive type doping area is arranged between the top of the second conductive type doping area and the upper surface of the epitaxial layer; an epitaxial divided layer which is located between respective second conductive type doping areas of adjacent schottky barrier diode unit cells and provided with the first conductive type ; the depth of the epitaxial divided layer is smaller than that of the second conductive type doping area; positioned at the upper part of the epitaxial layer, the doping density of the epitaxial divided layer is larger than that of the epitaxial layer. According to the invention, the reliability of the device is improved, the electric potential is reduced at the top of the groove, the forward voltage drop and loss of the device are reduced, and moreover, when the device is cut off reversely, the electric leakage of the device is further reduced.
Description
Technical field
The present invention relates to rectifying device, more particularly to a kind of channel schottky semiconductor devices.
Background technology
Schottky-barrier diode has used many decades as rectifying device in power supply application.Relative to PN junction
For diode, Schottky-barrier diode has the advantages that positive cut-in voltage is low and switching speed is fast, and this makes it fit very much
Conjunction is applied to Switching Power Supply and high frequency occasion.The reverse recovery time of Schottky-barrier diode is very short, and the time is main
Determined by the parasitic capacitance of device, and determined by sub- recombination time less unlike PN junction diode.Therefore, Schottky barrier two
Pole pipe rectifying device can effectively reduce switch power loss.
Schottky-barrier diode is that the metal-semiconductor junction principle formed using metal and semiconductor contact is made.
Traditional planar type Schottky barrier diode device is generally by the N+substrate of underlying high-dopant concentration and above
The N- epitaxially grown layers of low doping concentration constitute, the N of high-dopant concentration+substrate floor deposition lower metal layer forms ohm and connects
Touch, constitute the negative electrode of Schottky-barrier diode；The upper metal level of N- epitaxially grown layers top surface deposition of low doping concentration forms Xiao
Special base barrier contact, constitutes the anode of Schottky-barrier diode.Metal forms potential barrier with the work function difference of n type single crystal silicon, should
The height of potential barrier determines the characteristic of Schottky-barrier diode, and relatively low potential barrier can reduce forward conduction cut-in voltage, but
It is to increase can reverse leakage, reverse BV is reduced；Conversely, higher potential barrier can increase forward conduction cut-in voltage, together
When reduce reverse leakage, reverse blocking capability strengthen.However, compared with pn-junction diode, traditional Planar Schottky gesture
On the whole reverse leakage is big to build diode, and reverse BV is low.
The distinguishing feature of channel schottky barrier diode is the presence of similar groove MOS device in N- epitaxial layers
Grid structure, i.e., perpendicular to silicon chip surface, the groove extended in N- epitaxial layers, be covered in the gate oxide of flute surfaces, and
Fill the grid that conductive material therein is constituted.Device architecture as shown in figure 1, making devices silicon chip by highly doped N+ substrates and
More low-doped N- epitaxial layers 2 are constituted, and a series of grooves 3 are prepared in N- epitaxial layers 2, convex for n type single crystal silicon between groove 3
Platform structure 4, the sidewall growth of groove 3 has silicon dioxide layer 5, and upper metal level 6 is covered in the upper surface of total, and and monocrystalline silicon
The top surface of boss structure 4 contacts to form schottky junctions contacting surface, constitutes the anode of Schottky diode rectifying device.At N+ substrates bottom
Face deposition has lower metal layer 8 to constitute the negative electrode of Schottky diode rectifying device.Device architecture and electric-field intensity distribution curve are such as
Shown in Fig. 2, for different gash depths, electric-field intensity distribution curve when device reverse bias is computed.Electric field
The backward voltage blocking ability of the area respective devices that intensity curve is surrounded.Due to the presence of trench gate structure, device is reverse
Electric Field Distribution changes during biasing, and most strong, the electric-field intensity reduction of arrival schottky barrier interface is reached in gate groove bottom,
So as to enhance the voltage reversal blocking ability of the device, reverse leakage current is reduced.Except gate groove depth, gate oxidation thickness
Degree and boss structure region dopant concentration can modulation device reverse bias when Electric Field Distribution.
However, the subject matter that this structure design is exposed is that the lifting of device reverse voltage blocking ability is limited.Such as
In Fig. 2 shown in electric field strength profile, change with gash depth, maximum field strength position changes therewith, but electric-field strength is write music
It is not notable that line surrounds area change, i.e. device reverse voltage blocking ability is without significantly changing.In addition, the metal filled in groove
It is identical with upper metal level, when groove width is narrower, due to the gap filling capability of upper metal layer material it is bad, it is possible to stay
Cavity, affects the reliability of device.For this purpose, how to solve the above problems becoming the direction of those of ordinary skill in the art's effort.
The content of the invention
It is an object of the present invention to provide a kind of channel schottky semiconductor devices, the channel schottky semiconductor devices changes
The reliability of device has been apt to it, potential line density will be reduced at the top of groove, and cause device forward voltage drop and device loss equal
Reduced, and when device is reversely turned off, reduce further the electric leakage of device.
To reach above-mentioned purpose, the technical solution used in the present invention is：A kind of channel schottky semiconductor devices, is bowing
On view plane, the active area of the device is made up of several Schottky-barrier diode unit cell parallel connections, this pole of Schottky barrier two
On the longitudinal cross-section of pipe unit cell, each Schottky-barrier diode unit cell includes being located at silicon chip back side lower metal layer, positioned at described
The substrate layer of the lower metal layer top conduction type of heavy doping first, forms Ohmic contact, position between this substrate layer and lower metal layer
The epitaxial layer that the first conduction type is lightly doped is provided with substrate layer top, positioned at epitaxial layer top upper metal is provided with
Layer, a groove is from the epitaxial layer upper surface and extends to epitaxial layer middle part, and epitaxial layer region forms first between adjacent trenches
The monocrystalline silicon boss of conduction type, forms Schottky Barrier Contact face between this monocrystalline silicon boss top surface and upper metal level；It is special
Levy and be：One gate groove is located in the groove, and a conductive polycrystalline silicon body is embedded in the gate groove, positioned at conductive polycrystalline silicon body
The polysilicon middle and lower part of middle and lower part is located in gate groove and the first silica oxide layer is provided between epitaxial layer, positioned at conduction
The polysilicon top on polysilicon body top is located in upper metal level, and is provided with second between polysilicon top surrounding and upper metal level
Silica oxide layer, forms Ohmic contact face between polysilicon top upper surface and upper metal level；
There is the second conduction type doped region in the monocrystalline silicon boss and in groove surrounding side surface, this second leads
There is heavy doping the second conduction type doped region, second conductive-type between electric type doped region top and epitaxial layer upper surface
Type doped region and the second conduction type of heavy doping doped region form pn-junction interface with epitaxial layer；
Lead between the respective second conduction type doped region of adjacent Schottky-barrier diode unit cell and with first
The extension layering of electric type, this extension depth of seam division is less than the second conduction type doped region depth, and this extension layering is located at
Doping content of the doping content of epitaxial layer top and extension layering more than epitaxial layer.
Further improved technical scheme is as follows in above-mentioned technical proposal：
1. preferably, the second conduction type doped region and the contact surface of single-crystal Si epitaxial layers are arcwall face.
2. preferably, depth of the depth of the second conduction type doped region less than gate groove.
3. preferably, polysilicon top is with the height ratio of polysilicon middle and lower part in the conductive polycrystalline silicon body
1：5~7.
Because above-mentioned technical proposal is used, the present invention has compared with prior art following advantages and effect：
1. channel schottky semiconductor devices of the present invention, it is introduced in the monocrystalline silicon boss side higher than channel bottom
Between second conduction type doped region, and the respective second conduction type doped region of Schottky-barrier diode unit cell and positioned at tool
There is the extension layering of the first conduction type, Electric Field Distribution when modulation device reverse bias strengthens device reverse voltage blocking
Ability, meanwhile, the second different conduction type doped region doping contents can be directed to, adjust corresponding monocrystalline silicon boss in addition
The N-type region dopant concentration of side, for device performance adjustment more flexibilities are provided；Secondly, present configuration is to Electric Field Distribution
Further modulation, after electric-field intensity peak value occurs near channel bottom, can continue to higher value, improve direction resistance
Power-off pressure.
2. channel schottky semiconductor devices of the present invention, more positioned at conduction in the embedded gate groove of its conductive polycrystalline silicon body
The polysilicon middle and lower part of crystal silicon body middle and lower part is located in gate groove and is provided between epitaxial layer the first silica oxide layer, position
It is located in upper metal level in the polysilicon top on conductive polycrystalline silicon body top, and sets between polysilicon top surrounding and upper metal level
There is the second silica oxide layer, Ohmic contact face is formed between polysilicon top upper surface and upper metal level, improve device
Reliability, potential line density will the top of groove reduce, reduce further the electric leakage of device；Secondly, positioned at the list
There is the second conduction type doped region in crystal silicon boss and in groove surrounding side surface, this second conduction type doped region top with
There is heavy doping the second conduction type doped region, the second conduction type doped region and heavy doping second are led between epitaxial layer upper surface
Electric type doped region forms pn-junction interface with epitaxial layer so that device forward voltage drop and device loss are reduced, and
When device is reversely turned off, the second conductivity type regions exhaust pinch off, protect the Schottky barrier of device surface, element leakage
Stream is reduced.
Description of the drawings
Accompanying drawing 1 is the structural representation of existing Schottky semiconductor device；
Accompanying drawing 2 is electric-field intensity distribution curve map in existing device；
Accompanying drawing 3 is channel schottky semiconductor device structure schematic diagram of the present invention；
Accompanying drawing 4 is device of the present invention and existing groove structure device reverse bias electric-field intensity distribution curve comparison figure.
Specific embodiment
Below in conjunction with the accompanying drawings and embodiment the invention will be further described：
Embodiment：A kind of channel schottky semiconductor devices, in top plan view, the active area of the device is by several
Schottky-barrier diode unit cell 1 is in parallel to be constituted, on the longitudinal cross-section of this Schottky-barrier diode unit cell 1, each Schottky
Barrier diode unit cell 1 includes being located at silicon chip back side lower metal layer 2, conductive positioned at the top heavy doping first of the lower metal layer 2
The substrate layer 3 of type, between this substrate layer 3 and lower metal layer 2 Ohmic contact is formed, and is provided with light positioned at the top of the substrate layer 3
Adulterate the epitaxial layer 4 of the first conduction type, and positioned at the top of the epitaxial layer 4 upper metal level 5 is provided with, and a groove 6 is from the extension
4 upper surface of layer simultaneously extend to the middle part of epitaxial layer 4, and the region of epitaxial layer 4 forms the monocrystalline silicon of the first conduction type between adjacent trenches 6
Boss 7, forms Schottky Barrier Contact face 15 between this top surface of monocrystalline silicon boss 7 and upper metal level 5；One gate groove 8 is located at institute
State in groove 6, a conductive polycrystalline silicon body 9 is embedded in the gate groove 8, in the polysilicon of the middle and lower part of conductive polycrystalline silicon body 9
Bottom 91 is located in gate groove 8 and the first silica oxide layer 101 is provided between epitaxial layer 4, positioned at conductive polycrystalline silicon body 9
The polysilicon top 92 on top is located in upper metal level 5, and is provided with the two or two between the surrounding of polysilicon top 92 and upper metal level 5
Oxidation silicon oxide layer 102, forms Ohmic contact face 14 between the upper surface of polysilicon top 92 and upper metal level 5；
There is the second conduction type doped region 11 in the monocrystalline silicon boss 7 and in the surrounding side surface of groove 6, this
There is the second conduction type of heavy doping doped region 12 between the top of two conduction type doped region 11 and the upper surface of epitaxial layer 4, it is described
Second conduction type doped region 11 and the second conduction type of heavy doping doped region 12 form pn-junction interface with epitaxial layer 4；
Between the respective second conduction type doped region 11 of adjacent Schottky-barrier diode unit cell 1 and with first
The extension layering 13 of conduction type, this extension is layered 13 depth and is less than the depth of the second conduction type doped region 11, this extension
Layering 13 be located at the top of epitaxial layer 4 and extension layering 13 doping content more than epitaxial layer 4 doping content.
Above-mentioned second conduction type doped region 11 is arcwall face with the contact surface of the epitaxial layer 4 of monocrystalline silicon.
Depth of the depth of above-mentioned second conduction type doped region 11 less than gate groove 8.
Polysilicon top 92 and the height ratio of polysilicon middle and lower part 91 are 1 in above-mentioned conductive polycrystalline silicon body 9：6.
During using above-mentioned channel schottky semiconductor devices, Electric Field Distribution when modulation device reverse bias strengthens
Device reverse voltage blocking ability, for device performance adjustment more flexibilities are provided, and present configuration is further to Electric Field Distribution
Modulation, after electric-field intensity peak value occurs near channel bottom, can continue to higher value, improve direction blocking electricity
Pressure；Secondly, the reliability of device is which improved, potential line density will be reduced at the top of groove, reduce further device
Electric leakage；Again, it causes device forward voltage drop and device loss to be reduced, and when device is reversely turned off, second leads
Electric type area exhausts pinch off, protects the Schottky barrier of device surface, device creepage to reduce.
Above-described embodiment technology design only to illustrate the invention and feature, its object is to allow person skilled in the art
Scholar will appreciate that present disclosure and implement according to this, can not be limited the scope of the invention with this.It is all according to the present invention
Equivalence changes or modification that Spirit Essence is made, all should be included within the scope of the present invention.
Claims (1)
1. a kind of channel schottky semiconductor devices, in top plan view, the active area of the device is by several Schottky gesture
Build diode unit cell（1）Parallel connection is constituted, this Schottky-barrier diode unit cell（1）Longitudinal cross-section on, each Schottky barrier
Diode unit cell（1）Including positioned at silicon chip back side lower metal layer（2）, positioned at the lower metal layer（2）Top heavy doping first is led
The substrate layer of electric type（3）, this substrate layer（3）With lower metal layer（2）Between form Ohmic contact, positioned at the substrate layer（3）
Top is provided with the epitaxial layer that the first conduction type is lightly doped（4）, positioned at the epitaxial layer（4）Top is provided with metal level（5）, one
Groove（6）From the epitaxial layer（4）Upper surface simultaneously extends to epitaxial layer（4）Middle part, adjacent trenches（6）Between epitaxial layer（4）Area
Domain forms the monocrystalline silicon boss of the first conduction type（7）, this monocrystalline silicon boss（7）Top surface and upper metal level（5）Between form Xiao
Special base barrier contact face（15）；It is characterized in that：One gate groove（8）Positioned at the groove（6）It is interior, a conductive polycrystalline silicon body（9）
It is embedded in the gate groove（8）It is interior, positioned at conductive polycrystalline silicon body（9）The polysilicon middle and lower part of middle and lower part（91）Positioned at gate groove（8）
Interior and and epitaxial layer（4）Between be provided with the first silica oxide layer（101）, positioned at conductive polycrystalline silicon body（9）The polycrystalline on top
Silicon top（92）Positioned at upper metal level（5）It is interior, and polysilicon top（92）Surrounding and upper metal level（5）Between be provided with the second dioxy
SiClx oxide layer（102）, the polysilicon top（92）Upper surface and upper metal level（5）Between form Ohmic contact face（14）；
Positioned at the monocrystalline silicon boss（7）It is interior and in groove（6）Surrounding side surface has the second conduction type doped region（11）, this
Second conduction type doped region（11）Top and epitaxial layer（4）There is heavy doping the second conduction type doped region between upper surface
（12）, the second conduction type doped region（11）With heavy doping the second conduction type doped region（12）And epitaxial layer（4）Shape
Into pn-junction interface；
Positioned at adjacent Schottky-barrier diode unit cell（1）Respective second conduction type doped region（11）Between and with first
The extension layering of conduction type（13）, this extension layering（13）Depth is less than the second conduction type doped region（11）Depth,
This extension layering（13）Positioned at epitaxial layer（4）Top and extension layering（13）Doping content be more than epitaxial layer（4）Doping it is dense
Degree.
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| CN201410349022.9A CN104078517B (en) | 2014-07-22 | 2014-07-22 | Groove type schottky semiconductor device |
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| CN201410349022.9A CN104078517B (en) | 2014-07-22 | 2014-07-22 | Groove type schottky semiconductor device |
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| CN104078517B true CN104078517B (en) | 2017-05-10 |
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| CN105789334B (en) * | 2016-03-16 | 2018-11-23 | 杭州立昂微电子股份有限公司 | A kind of Schottky barrier semiconductor rectifier and its manufacturing method |
| CN109390336B (en) * | 2018-12-10 | 2024-03-26 | 西安电子科技大学 | Novel wide forbidden band power semiconductor device and manufacturing method thereof |
| CN114927561B (en) * | 2022-06-30 | 2023-05-02 | 电子科技大学 | Silicon carbide MOSFET device |
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| US7186609B2 (en) * | 1999-12-30 | 2007-03-06 | Siliconix Incorporated | Method of fabricating trench junction barrier rectifier |
| CN1520616A (en) * | 2001-04-11 | 2004-08-11 | ��˹�������뵼�幫˾ | Power semiconductor devices having laterally extending base shielding regions that inhibit base reach through and methodds of forming same |
| JP4047153B2 (en) * | 2002-12-03 | 2008-02-13 | 株式会社東芝 | Semiconductor device |
| US20050199918A1 (en) * | 2004-03-15 | 2005-09-15 | Daniel Calafut | Optimized trench power MOSFET with integrated schottky diode |
| TWI384625B (en) * | 2008-06-30 | 2013-02-01 | Alpha & Omega Semiconductor | Enhancing schottky breakdown voltage (bv) without affecting an integrated mosfet-schottky device layout |
| CN101901807B (en) * | 2010-06-23 | 2011-11-09 | 苏州硅能半导体科技股份有限公司 | Channel schottky barrier diode rectifying device and manufacturing method |
| CN203983296U (en) * | 2014-07-22 | 2014-12-03 | 苏州硅能半导体科技股份有限公司 | Channel schottky semiconductor device |
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