CN203983296U - Channel schottky semiconductor device - Google Patents
Channel schottky semiconductor device Download PDFInfo
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- CN203983296U CN203983296U CN201420407588.8U CN201420407588U CN203983296U CN 203983296 U CN203983296 U CN 203983296U CN 201420407588 U CN201420407588 U CN 201420407588U CN 203983296 U CN203983296 U CN 203983296U
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Abstract
The utility model discloses a kind of channel schottky semiconductor device, and its conductive polycrystalline silicon body embeds in described gate groove, in the polysilicon middle and lower part of conductive polycrystalline silicon body middle and lower part in gate groove and and epitaxial loayer between be provided with the first silicon dioxide oxide layer; Be positioned at described monocrystalline silicon boss and there is the second conduction type doped region at groove surrounding side surface, between this top, the second conduction type doped region and epitaxial loayer upper surface, there is heavy doping the second conduction type doped region, between adjacent Schottky barrier diode unit cell the second conduction type doped region separately and be positioned at the extension layering with the first conduction type, this extension depth of seam division is less than the described second conduction type doped region degree of depth, and the doping content that this extension layering is positioned at epitaxial loayer top and extension layering is greater than the doping content of epitaxial loayer.The utility model has improved the reliability of device, and potential lines density reduces the top at groove, and makes device forward voltage drop and device loss all obtain reducing, and when device oppositely turn-offs, has further reduced the electric leakage of device.
Description
Technical field
The utility model relates to rectifying device, particularly a kind of channel schottky semiconductor device.
Background technology
Schottky barrier diode has been used many decades in application of power field as rectifying device.For PN junction diode, Schottky barrier diode has advantages of that forward cut-in voltage is low and switching speed is fast, and this makes it be applicable to being very much applied to Switching Power Supply and high frequency occasion.The reverse recovery time of Schottky barrier diode is very short, and this time is mainly determined by the parasitic capacitance of device, and by less, determines sub-recombination time unlike PN junction diode.Therefore, Schottky-barrier diode rectifier can effectively reduce switch power loss.
Schottky barrier diode is that the metal-semiconductor junction principle of utilizing metal to contact formation with semiconductor is made.Traditional planar type Schottky barrier diode device consists of with the N-epitaxially grown layer that is positioned at the low doping concentration of top the N+substrate that is positioned at the high-dopant concentration of below conventionally, N+substrate bottom surface deposition lower metal layer of high-dopant concentration forms ohmic contact, forms the negative electrode of Schottky barrier diode; The upper metal level of N-epitaxially grown layer end face deposition of low doping concentration forms Schottky Barrier Contact, forms the anode of Schottky barrier diode.The work function difference of metal and n type single crystal silicon forms potential barrier, and the height of this potential barrier has determined the characteristic of Schottky barrier diode, and lower potential barrier can reduce forward conduction cut-in voltage, but can make reverse leakage increase, reverse blocking lower voltage; Otherwise higher potential barrier can increase forward conduction cut-in voltage, make reverse leakage reduce simultaneously, reverse blocking capability strengthens.Yet, to compare with pn junction diode, traditional planar type Schottky barrier diode on the whole reverse leakage is large, and reverse blocking voltage is low.
The distinguishing feature of channel schottky barrier diode is the grid structure that has similar groove MOS device in N-epitaxial loayer, perpendicular to silicon chip surface, extend into the groove in N-epitaxial loayer, cover the gate oxide of flute surfaces, and fill the grid that electric conducting material wherein forms.Device architecture as shown in Figure 1, the silicon chip of making device consists of highly doped N+ substrate 1 and more low-doped N-epitaxial loayer 2, a series of grooves 3 are prepared in N-epitaxial loayer 2, it between groove 3, is n type single crystal silicon boss structure 4, groove 3 sidewall growths have silicon dioxide layer 5, upper metal level 6 covers the upper surface of total, and contacts formation Schottky contacts face with the end face of monocrystalline silicon boss structure 4, forms the anode of Schottky diode rectifying device.In N+ substrate 1 bottom surface, deposit the negative electrode that lower metal layer 8 forms Schottky diode rectifying device.As shown in Figure 2, for different gash depths, the electric-field intensity distribution curve in the time of device reverse bias is calculated for device architecture and electric-field intensity distribution curve.The reverse voltage blocking ability of the area respective devices that electric field strength Curves surrounds.Due to the existence of trench gate structure, during device reverse bias, Electric Field Distribution changes, and in gate groove bottom, reaches the strongest, and the electric field strength that arrives schottky barrier interface reduces, thereby has strengthened the voltage reversal blocking ability of this device, has reduced reverse leakage current.Except the gate groove degree of depth, Electric Field Distribution when gate oxide thickness and boss structure region doping concentration can modulation device reverse bias.
Yet the subject matter that this structural design exposes is that the lifting of device reverse voltage blocking ability is limited.As shown in electric field strength curve in Fig. 2, with gash depth, change, electric field strength peak changes thereupon, but electric field strength Curves encirclement area change is not remarkable, and device reverse voltage blocking ability is without remarkable change.In addition, the metal of filling in groove is identical with upper metal level, when groove width is narrower, because the gap filling ability of upper metal layer material is bad, likely leaves cavity, affects the reliability of device.For this reason, how to address the above problem and become the direction that those of ordinary skills make great efforts.
Summary of the invention
The utility model object is to provide a kind of channel schottky semiconductor device, this channel schottky semiconductor device has improved the reliability of device, potential lines density reduces the top at groove, and make device forward voltage drop and device loss all obtain reducing, and when device oppositely turn-offs, further reduced the electric leakage of device.
For achieving the above object, the technical solution adopted in the utility model is: a kind of channel schottky semiconductor device, in top plan view, the active area of this device consists of several Schottky barrier diode unit cell parallel connections, on the longitudinal cross-section of this Schottky barrier diode unit cell, each Schottky barrier diode unit cell comprises and is positioned at silicon chip back side lower metal layer, be positioned at the substrate layer of described lower metal layer top heavy doping the first conduction type, between this substrate layer and lower metal layer, form ohmic contact, be positioned at the epitaxial loayer that described substrate layer top is provided with light dope the first conduction type, be positioned at described epitaxial loayer top and be provided with metal level, one groove is from described epitaxial loayer upper surface and extend to epitaxial loayer middle part, between adjacent trenches, epitaxial loayer region forms the monocrystalline silicon boss of the first conduction type, between this monocrystalline silicon boss end face and upper metal level, form Schottky Barrier Contact face, it is characterized in that: a gate groove is positioned at described groove, one conductive polycrystalline silicon body embeds in described gate groove, in the polysilicon middle and lower part of conductive polycrystalline silicon body middle and lower part in gate groove and and epitaxial loayer between be provided with the first silicon dioxide oxide layer, the polysilicon top that is positioned at conductive polycrystalline silicon body top is positioned at metal level, and between polysilicon top surrounding and upper metal level, be provided with the second silicon dioxide oxide layer, between described polysilicon top upper surface and upper metal level, form ohmic contact face,
Be positioned at described monocrystalline silicon boss and there is the second conduction type doped region at groove surrounding side surface, between this top, the second conduction type doped region and epitaxial loayer upper surface, have heavy doping the second conduction type doped region, described the second conduction type doped region and heavy doping the second conduction type doped region all form pn junction interface with epitaxial loayer;
Between adjacent Schottky barrier diode unit cell the second conduction type doped region separately and be positioned at the extension layering with the first conduction type, this extension depth of seam division is less than the described second conduction type doped region degree of depth, and the doping content that this extension layering is positioned at epitaxial loayer top and extension layering is greater than the doping content of epitaxial loayer.
In technique scheme, further improved technical scheme is as follows:
1. as preferred version, the contact-making surface of described the second conduction type doped region and single-crystal Si epitaxial layers is arcwall face.
2. as preferred version, the degree of depth of described the second conduction type doped region is less than the degree of depth of gate groove.
3. as preferred version, in described conductive polycrystalline silicon body, the aspect ratio of polysilicon top and polysilicon middle and lower part is 1:5 ~ 7.
Because technique scheme is used, the utility model compared with prior art has following advantages and effect:
1. the utility model channel schottky semiconductor device, it introduces the second conduction type doped region in monocrystalline silicon boss one side higher than channel bottom, and between Schottky barrier diode unit cell the second conduction type doped region separately and be positioned at the extension layering with the first conduction type, Electric Field Distribution in the time of modulation device reverse bias, enhance device reverse voltage blocking ability, simultaneously, can be for the second different conduction type doped region doping contents, adjust the N-type region doping concentration of the corresponding with it other side of monocrystalline silicon boss, for device performance adjustment provides more flexibilities, secondly, the utility model structure is further modulated Electric Field Distribution, and electric field strength occurring near channel bottom after peak value, can continue the value that remains higher, has improved direction blocking voltage.
2. the utility model channel schottky semiconductor device, its conductive polycrystalline silicon body embeds in gate groove, in the polysilicon middle and lower part of conductive polycrystalline silicon body middle and lower part in gate groove and and epitaxial loayer between be provided with the first silicon dioxide oxide layer, the polysilicon top that is positioned at conductive polycrystalline silicon body top is positioned at metal level, and between polysilicon top surrounding and upper metal level, be provided with the second silicon dioxide oxide layer, between polysilicon top upper surface and upper metal level, form ohmic contact face, improved the reliability of device, potential lines density reduces the top at groove, further reduced the electric leakage of device, secondly, be positioned at described monocrystalline silicon boss and there is the second conduction type doped region at groove surrounding side surface, between this top, the second conduction type doped region and epitaxial loayer upper surface, there is heavy doping the second conduction type doped region, the second conduction type doped region and heavy doping the second conduction type doped region all form pn junction interface with epitaxial loayer, make device forward voltage drop and device loss all obtain reducing, and when device oppositely turn-offs, the second conductivity type regions exhausts pinch off, protected the Schottky barrier of device surface, device creepage reduces.
Accompanying drawing explanation
Accompanying drawing 1 is the structural representation of existing Schottky semiconductor device;
Accompanying drawing 2 is electric-field intensity distribution curve chart in existing device;
Accompanying drawing 3 is the utility model channel schottky semiconductor device structure schematic diagram;
Accompanying drawing 4 is the utility model device and existing groove structure device reverse bias electric-field intensity distribution curve comparison figure.
In above accompanying drawing, 1, Schottky barrier diode unit cell; 2, lower metal layer; 3, substrate layer; 4, epitaxial loayer; 5, upper metal level; 6, groove; 7, monocrystalline silicon boss; 8, gate groove; 9, conductive polycrystalline silicon; 91, polysilicon middle and lower part; 92, polysilicon top; 101, the first silicon dioxide oxide layer; 102, the second silicon dioxide oxide layer; 11, the second conduction type doped region; 12, heavy doping the second conduction type doped region; 13, extension layering; 14, ohmic contact face; 15, Schottky Barrier Contact face.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described:
Embodiment: a kind of channel schottky semiconductor device, in top plan view, the active area of this device consists of several Schottky barrier diode unit cell 1 parallel connections, on the longitudinal cross-section of this Schottky barrier diode unit cell 1, each Schottky barrier diode unit cell 1 comprises and is positioned at silicon chip back side lower metal layer 2, be positioned at the substrate layer 3 of described lower metal layer 2 top heavy doping the first conduction types, between this substrate layer 3 and lower metal layer 2, form ohmic contact, be positioned at the epitaxial loayer 4 that described substrate layer 3 tops are provided with light dope the first conduction type, be positioned at described epitaxial loayer 4 tops and be provided with metal level 5, one groove 6 is from described epitaxial loayer 4 upper surfaces and extend to epitaxial loayer 4 middle parts, between adjacent trenches 6, epitaxial loayer 4 regions form the monocrystalline silicon boss 7 of the first conduction type, between these monocrystalline silicon boss 7 end faces and upper metal level 5, form Schottky Barrier Contact face 15, one gate groove 8 is positioned at described groove 6, one conductive polycrystalline silicon body 9 embeds in described gate groove 8, in the polysilicon middle and lower part 91 of conductive polycrystalline silicon body 9 middle and lower parts in gate groove 8 and and epitaxial loayer 4 between be provided with the first silicon dioxide oxide layer 101, the polysilicon top 92 that is positioned at conductive polycrystalline silicon body 9 tops is positioned at metal level 5, and between polysilicon top 92 surroundings and upper metal level 5, be provided with the second silicon dioxide oxide layer 102, between described polysilicon top 92 upper surfaces and upper metal level 5, form ohmic contact face 14,
Be positioned at described monocrystalline silicon boss 7 and there is the second conduction type doped region 11 at groove 6 surrounding side surfaces, between these 11 tops, the second conduction type doped region and epitaxial loayer 4 upper surfaces, have heavy doping the second conduction type doped region 12, described the second conduction type doped region 11 and heavy doping the second conduction type doped region 12 all form pn junction interface with epitaxial loayer 4;
Between adjacent Schottky barrier diode unit cell 1 the second conduction type doped region 11 separately and be positioned at the extension layering 13 with the first conduction type, these extension layering 13 degree of depth are less than described second conduction type doped region 11 degree of depth, and the doping content that this extension layering 13 is positioned at epitaxial loayer 4 tops and extension layering 13 is greater than the doping content of epitaxial loayer 4.
Above-mentioned the second conduction type doped region 11 is arcwall face with the contact-making surface of the epitaxial loayer 4 of monocrystalline silicon.
The degree of depth of above-mentioned the second conduction type doped region 11 is less than the degree of depth of gate groove 8.
In above-mentioned conductive polycrystalline silicon body 9, polysilicon top 92 is 1:6 with the aspect ratio of polysilicon middle and lower part 91.
While adopting above-mentioned channel schottky semiconductor device, Electric Field Distribution in the time of modulation device reverse bias, enhance device reverse voltage blocking ability, for device performance adjustment provides more flexibilities, the utility model structure is further modulated Electric Field Distribution, electric field strength occurring near channel bottom after peak value, can continue the value that remains higher, improved direction blocking voltage; Secondly, it has improved the reliability of device, and potential lines density reduces the top at groove, has further reduced the electric leakage of device; Again, it makes device forward voltage drop and device loss all obtain reducing, and when device oppositely turn-offs, the second conductivity type regions exhausts pinch off, has protected the Schottky barrier of device surface, and device creepage reduces.
Above-described embodiment is only explanation technical conceive of the present utility model and feature, and its object is to allow person skilled in the art can understand content of the present utility model and implement according to this, can not limit protection range of the present utility model with this.All equivalences of doing according to the utility model Spirit Essence change or modify, within all should being encompassed in protection range of the present utility model.
Claims (4)
1. a channel schottky semiconductor device, in top plan view, the active area of this device forms by several Schottky barrier diode unit cells (1) are in parallel, on the longitudinal cross-section of this Schottky barrier diode unit cell (1), each Schottky barrier diode unit cell (1) comprises and is positioned at silicon chip back side lower metal layer (2), be positioned at the substrate layer (3) of described lower metal layer (2) top heavy doping the first conduction type, between this substrate layer (3) and lower metal layer (2), form ohmic contact, be positioned at the epitaxial loayer (4) that described substrate layer (3) top is provided with light dope the first conduction type, be positioned at described epitaxial loayer (4) top and be provided with metal level (5), one groove (6) is from described epitaxial loayer (4) upper surface and extend to epitaxial loayer (4) middle part, between adjacent trenches (6), epitaxial loayer (4) region forms the monocrystalline silicon boss (7) of the first conduction type, between this monocrystalline silicon boss (7) end face and upper metal level (5), form Schottky Barrier Contact face (15), it is characterized in that: a gate groove (8) is positioned at described groove (6), one conductive polycrystalline silicon body (9) embeds in described gate groove (8), the polysilicon middle and lower part (91) that is positioned at conductive polycrystalline silicon body (9) middle and lower part be positioned at gate groove (8) and and epitaxial loayer (4) between be provided with the first silicon dioxide oxide layer (101), the polysilicon top (92) that is positioned at conductive polycrystalline silicon body (9) top is positioned at metal level (5), and between polysilicon top (92) surrounding and upper metal level (5), be provided with the second silicon dioxide oxide layer (102), between described polysilicon top (92) upper surface and upper metal level (5), form ohmic contact face (14),
Be positioned at described monocrystalline silicon boss (7) and there is the second conduction type doped region (11) at groove (6) surrounding side surface, between this (11) top, the second conduction type doped region and epitaxial loayer (4) upper surface, have heavy doping the second conduction type doped region (12), described the second conduction type doped region (11) and heavy doping the second conduction type doped region (12) all form pn junction interface (not finding temporarily wrong herein) with epitaxial loayer (4);
Between adjacent Schottky barrier diode unit cell (1) the second conduction type doped region (11) separately and be positioned at the extension layering (13) with the first conduction type, this extension layering (13) degree of depth is less than described second conduction type doped region (11) degree of depth, and the doping content that this extension layering (13) is positioned at epitaxial loayer (4) top and extension layering (13) is greater than the doping content of epitaxial loayer (4).
2. channel schottky semiconductor device according to claim 1, is characterized in that: described the second conduction type doped region (11) is arcwall face with the contact-making surface of epitaxial loayer (4).
3. channel schottky semiconductor device according to claim 1, is characterized in that: the degree of depth of described the second conduction type doped region (11) is less than the degree of depth of gate groove (8).
4. channel schottky semiconductor device according to claim 1, is characterized in that: in described conductive polycrystalline silicon body (9), polysilicon top (92) is 1:5 ~ 7 with the aspect ratio of polysilicon middle and lower part (91).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420407588.8U CN203983296U (en) | 2014-07-22 | 2014-07-22 | Channel schottky semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420407588.8U CN203983296U (en) | 2014-07-22 | 2014-07-22 | Channel schottky semiconductor device |
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| Publication Number | Publication Date |
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| CN203983296U true CN203983296U (en) | 2014-12-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420407588.8U Withdrawn - After Issue CN203983296U (en) | 2014-07-22 | 2014-07-22 | Channel schottky semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078517A (en) * | 2014-07-22 | 2014-10-01 | 苏州硅能半导体科技股份有限公司 | Groove type schottky semiconductor device |
-
2014
- 2014-07-22 CN CN201420407588.8U patent/CN203983296U/en not_active Withdrawn - After Issue
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104078517A (en) * | 2014-07-22 | 2014-10-01 | 苏州硅能半导体科技股份有限公司 | Groove type schottky semiconductor device |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20141203 Effective date of abandoning: 20170510 |