CN108962871A - 半导体装置封装 - Google Patents
半导体装置封装 Download PDFInfo
- Publication number
- CN108962871A CN108962871A CN201710969639.4A CN201710969639A CN108962871A CN 108962871 A CN108962871 A CN 108962871A CN 201710969639 A CN201710969639 A CN 201710969639A CN 108962871 A CN108962871 A CN 108962871A
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- Prior art keywords
- rdl
- dielectric layer
- electronic building
- semiconductor device
- building brick
- Prior art date
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- 229920000642 polymer Polymers 0.000 claims description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- IUYOGGFTLHZHEG-UHFFFAOYSA-N copper titanium Chemical compound [Ti].[Cu] IUYOGGFTLHZHEG-UHFFFAOYSA-N 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
一种半导体装置封装,其包含介电层、第一RDL、第二RDL、电感器、第一电子组件和第二电子组件。所述第一RDL邻近于所述介电层的第一表面,并且所述第一RDL包含第一导电零件。所述第二RDL邻近于所述介电层的第二表面,并且所述第二RDL包含第二导电零件。所述电感器安置于所述介电层中。所述电感器包含感应柱,其中穿过所述介电层安置感应柱中的每一个,并且感应柱中的每一个在第一RDL的第一导电零件中的相应一个与第二RDL的第二导电零件中的相应一个之间互连。第一电子组件和第二电子组件在第一RDL与第二RDL之间,并且通过电感器电连接到彼此。
Description
技术领域
本发明涉及半导体装置封装,且更确切地说,涉及具有减小的物理大小和厚度的半导体装置封装。
背景技术
由于多种电子组件的集成密度的连续改进,半导体行业经历了快速的增长。由于对小型化、更高速度和更低功率消耗的需求的连续地增长,已经开发了堆叠装置封装(例如,三维(3D)装置封装)作为进一步减少装置封装的物理大小的方式。在堆叠装置封装中,有源组件(例如,逻辑电路、存储器、处理器电路等等)和无源组件(例如,电容器、电感器、电阻器等等)是在单独的半导体晶片上制造的。有源组件和无源组件安装在彼此的顶部上以进一步减少装置封装的横向形状因数。堆叠结构可以减少封装装置的面积,但是封装装置的总体厚度和大小可能以另外的方式增大。
发明内容
在一些实施例中,半导体装置封装包含介电层、第一RDL、第二RDL、电感器、第一电子组件和第二电子组件。介电层包含第一表面和与第一表面相对的第二表面。第一RDL邻近于介电层的第一表面,并且第一RDL包含多个第一导电零件。第二RDL邻近于介电层的第二表面,并且第二RDL包含多个第二导电零件。电感器安置于介电层中。电感器包含多个感应柱,其中穿过介电层安置感应柱中的每一个,并且感应柱中的每一个在第一RDL的第一导电零件中的相应一个与第二RDL的第二导电零件中的相应一个之间互连。第一电子组件和第二电子组件在第一RDL与第二RDL之间,并且通过电感器电连接到彼此。
在一些实施例中,半导体装置封装包含介电层、第一电子组件、第二电子组件和电感器。介电层包含第一表面和与第一表面相对的第二表面。第一电子组件和第二电子组件安置于介电层中。电感器安置于介电层中,并且电连接到第一电子组件和第二电子组件。电感器包含基本上垂直于介电层的第一表面或第二表面的至少一个核心区。
在一些实施例中,半导体装置封装包含介电层、电感器、多个导电零件和导线。介电层包含第一表面和与第一表面相对的第二表面。电感器在介电层中,并且电感器包含穿过介电层的多个感应柱。导电零件安置在介电层的第一表面和第二表面上方,并且电连接到感应柱的一部分。导线电连接到感应柱中的至少一个,且经配置以调节电感器的阻抗。
附图说明
当结合附图阅读时,从以下具体实施方式中最好地理解本发明的一些实施例的方面。应注意,各种结构可能未按比例绘制,且各种结构的尺寸可出于论述的清楚起见而任意增大或减小。
图1说明根据本发明的一些实施例的半导体装置封装的截面图;
图2A说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图2B说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图2C说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图2D说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图2E说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图3说明根据本发明的一些实施例的半导体装置封装的截面图;
图4A说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图4B说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图4C说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图4D说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图4E说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图5说明根据本发明的一些实施例的半导体装置封装的截面图;
图6A说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图6B说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图6C说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图6D说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图6E说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图7说明根据本发明的一些实施例的半导体装置封装的截面图;
图8A说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图8B说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图8C说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图8D说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段;
图8E说明根据本发明的一些实施例的半导体装置封装的制造方法的实例的一或多个阶段。
具体实施方式
贯穿图式和具体实施方式使用共参考标号来指示相同或类似组件。本发明的实施例将容易从结合附图进行的以下详细描述中理解。
以下揭示内容提供用于实施所提供的标的物的不同特征的许多不同实施例或实例。下文描述组件和布置的具体实例以解释本发明的某些方面。当然,这些组件以及布置仅为实例且并不意图是限制性的。举例来说,在以下描述中,第一特征在第二特征上方或第二特征上的形成可包含第一特征和第二特征直接接触地形成或安置的实施例,并且还可包含额外特征可在第一特征与第二特征之间形成或安置使得第一特征和第二特征可不直接接触的实施例。此外,本发明可在各种实例中重复参考标号和/或字母。此重复是出于简单和清楚的目的,且本身并不指示所论述的各种实施例和/或配置之间的关系。
除非另外说明,否则例如“上方”、“下方”、“上”、“左”、“右”、“下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“高于”、“低于”、“上部”、“在……上”、“在……下”等等的空间描述是相对于图中所示的取向来指示的。应理解,本文中所使用的空间描述仅是出于说明的目的,且本文中所描述的结构的实际实施方案可以任何取向或方式在空间上布置,其限制条件为本发明的实施例的优点不因此布置而有偏差。
本发明的至少一些实施例涉及半导体装置封装。在一些实施例中,半导体装置封装包含***于两个再分布层(RDL)之间的介电层、电感器以及两个或大于两个电子组件。电感器包含穿透穿过介电层的感应柱。两个或大于两个电子组件安置于介电层中并且通过电感器电连接到彼此。在一些实施例中,电感器包含至少一个基本上垂直于表面(例如,介电层的顶部表面或底部表面)的核心区。在一些实施例中,半导体装置封装包含在介电层的顶部表面和底部表面上方并且电连接到感应柱的一部分的导电零件。在一些实施例中,半导体装置封装包含连接到感应柱的一部分以调节电感器的阻抗的一或多个导线。
在一些实施例中,半导体装置封装包含***于两个RDL之间的介电层。半导体装置封装进一步包含集成电感器,所述集成电感器包含穿透穿过介电层的感应柱和在介电层的两个相对表面上方并且电连接到感应柱的导电零件。半导体装置封装进一步包含通过集成电感器电连接到彼此的两个或大于两个电子组件。集成电感器的感应柱安置在RDL之间并且邻近于电子组件。因此,可以减小半导体装置封装的厚度和大小。在一些实施例中,半导体装置封装可以包含电连接到感应柱的一或多个导线。导线可以在形成电感器之后形成,并且因此可经配置以调节电感器的阻抗。
图1是根据本发明的一些实施例的半导体装置封装1的截面图。如图1中所示,半导体装置封装1包含介电层40、电感器30、一或多个第一电子组件42和一或多个第二电子组件44。介电层40包含第一表面401(例如,顶部表面)和与第一表面401相对的第二表面402(例如,底部表面)。在一些实施例中,介电层40包含聚合物介电层,例如,模制化合物层。借助于实例,聚合物介电层的材料可以包含(但不限于)聚酰亚胺(PI)、聚苯并噁唑(PBO)或其它合适的材料。在一些实施例中,聚合物介电层的材料可以包含(但不限于)光固化材料或可由光固化材料形成(但不限于此),例如光阻剂或类似物。
在一些实施例中,半导体装置封装1可以进一步包含第一再分布层(RDL)20和第二RDL 50。第一RDL 20安置为邻近于介电层40的第一表面401,并且第二RDL 50安置为邻近于介电层40的第二表面402。在一些实施例中,第一RDL 20包含一或多个导电层201和堆叠到彼此的一或多个绝缘层202。导电层201中的一个可以包含从至少一个绝缘层202中暴露且邻近于介电层40的第一表面401的第一导电零件22。在一些实施例中,第一导电零件22的边缘是由介电层40围绕的,而一或多个表面(例如,第一导电零件22的上表面)是从介电层40的第一表面401中暴露的。在一些实施例中,绝缘层202可以包含氧化硅层、氮化硅层或类似物。
在一些实施例中,绝缘层202的硬度大于介电层40的硬度。举例来说,绝缘层202的硬度(测量为凹痕硬度)可以为介电层40的硬度的至少约1.1倍、至少约1.3倍、或至少约1.5倍。在一些实施例中,第二RDL 50包含一或多个导电层501和堆叠到彼此的一或多个绝缘层502,并且导电层501中的一个可以包含从绝缘层502中暴露且邻近于介电层40的第二表面402的第二导电零件52。在一些实施例中,第二导电零件52在介电层40的第二表面402上方。
电感器30安置于介电层40中。在一些实施例中,电感器30包含一或多个感应柱32。感应柱32中的每一个穿透穿过介电层40,并且在第一RDL 20的第一导电零件22中的相应一个与第二RDL 50的第二导电零件52中的相应一个之间互连。在一些实施例中,感应支柱32与第一导电零件22的高度的总和大体上等于介电层40的厚度。在一些实施例中,感应柱32中的至少一些通过第一导电零件22电连接到导电层201中的至少一个和/或通过第二导电零件52电连接到导电层501中的至少一个。在一些实施例中,电感器30包含基本上垂直于介电层40的第一表面401或第二表面402的至少一个核心区,其中所述核心区包含感应柱32中的一或多个。
第一电子组件42和第二电子组件44安置于介电层40中。在一些实施例中,第一电子组件42和第二电子组件44各自可以包含呈集成电路(IC)形式的至少一个半导体裸片。在一些实施例中,第一电子组件42可以包含(但不限于)至少一个有源组件,例如,处理器组件、开关组件、专用IC(ASIC)、现场可编程门阵列(FPGA)、数字信号处理器(DSP)、存储器组件或其它有源组件。在一些实施例中,第二电子组件44可以包含(但不限于)至少一个无源组件,例如,电容器、电阻器或类似物。
在一些实施例中,第一电子组件42和/或第二电子组件44可以为通过表面安装技术(SMT)安装在第二RDL 50上且电连接到第二RDL 50的一或多个倒装芯片组件。在一些实施例中,第一电子组件42和第二电子组件44可以通过(例如)电感器30电连接到彼此。在一些实施例中,第一电子组件42和第二电子组件44可以相应地通过导电结构42C和导电结构44C电连接到第二RDL 50。导电结构42C和导电结构44C可以包含(例如)导电柱、导电桩、接合垫或类似物。
在一些实施例中,半导体装置封装1进一步包含穿透穿过介电层40且电连接到第一RDL 20和第二RDL 50的连接柱46。在一些实施例中,第一电子组件42和第二电子组件44可以通过(例如)电感器30进一步电连接到第一RDL 20,并且通过(例如)连接柱46进一步电连接到第二RDL 50的至少一部分。在一些实施例中,导电结构42C和导电结构44C可以短于感应柱32和连接柱46。在一些实施例中,导电结构42C、导电结构44C、感应柱32和连接柱46中的每一个的至少一端可以基本上在与第二RDL 50相同的水平处并且电连接到第二RDL50。
在一些实施例中,半导体装置封装1可以进一步包含安置在第一RDL 20的上方的一或多个第三电子组件60。至少一个第三电子组件60可以与第一电子组件42和第二电子组件44相对地安置。在一些实施例中,至少一个第三电子组件60可以通过一或多个导电凸块61(例如,焊料凸块、焊料球、焊料膏或类似物)电连接到第一RDL 20。在一些实施例中,至少一个第三电子组件60可以通过第一RDL 20电连接到第一电子组件42和/或第二电子组件44。在一些实施例中,第三电子组件60可包含(但不限于)至少一个有源组件,例如,处理器组件、开关组件、ASIC、FPGA、DSP、存储器组件或其它有源组件。在一些实施例中,半导体装置封装1可以进一步包含安置在第一RDL 20上方且囊封第三电子组件60的囊封物62。
在一些实施例中,半导体装置封装1可以进一步包含安置在第二RDL 50上方的至少一个导线48。导线48可以在导线48的一端处电连接到第二导电零件52中的一个,并且在导线48的另一端处电连接到第二导电零件52中的另一个。在一些实施例中,导线48可以通过(例如)导线接合形成。导线48可以在形成电感器30之后形成,并且因此可经配置以调节电感器30的阻抗(如果电感器30的实际阻抗偏离预先设计的阻抗)。
在一些实施例中,半导体装置封装1可以进一步包含在第二RDL 50上方且囊封导线48的模制层54。在一些实施例中,一或多个导电结构64(例如,凸块下金属化物(UBM))可以安置在模制层54的上方并且电连接到第二RDL 50。在一些实施例中,导电凸块66(例如,焊料凸块、焊料球、焊料膏或类似物)可以安装在导电结构64的上方且电连接到导电结构64,并且经配置以电连接到其它电子装置(例如,电路板或类似物)。
图2A、图2B、图2C、图2D和图2E说明根据本发明的一些实施例的半导体装置封装1的制造方法的实例的各个阶段。如图2A中所描绘,包含第一导电零件22的第一RDL 20形成于载体衬底10的上方。在一些实施例中,载体衬底10可以包含(但不限于)玻璃衬底。
如图2B中所描绘,感应柱32形成于第一RDL 20上方,并且电连接到第一导电零件22。在一些实施例中,连接柱46形成于第一RDL 20上方,并且电连接到第一RDL 20。在一些实施例中,感应柱32和连接柱46在相同的过程中同时形成。在一些其它实施例中,感应柱32在形成连接柱46之前或在形成连接柱46之后形成。在一些实施例中,一或多个第一电子组件42和一或多个第二电子组件44安装在第一RDL 20上并且电连接到第一RDL 20。
如图2C中所描绘,介电层40形成于第一RDL 20上方。在一些实施例中,第一导电零件22、感应柱32、连接柱46、第一电子组件42和第二电子组件44的至少一些部分通过介电层40囊封。在一些实施例中,感应柱32、连接柱46、第一电子组件42和第二电子组件44的至少一些部分是从介电层40的第二表面402中暴露的。
如图2D中所描绘,包含第二导电零件52的第二RDL50形成于介电层40的第二表面402上方。第二导电零件52电连接到感应柱32的至少一部分。第二RDL 50电连接到连接柱46。第二导电零件52、感应柱32和第一导电零件22电连接并且共同地形成电感器30。在一些实施例中,可形成至少一个导线48以在导线48的一端处电连接第二导电零件52中的一个,并且在导线48的另一端处电连接第二导电零件52中的另一个。在一些实施例中,可以通过导线接合形成导线48,但并不限于此。在一些实施例中,模制层54可以在第二RDL 50的上方形成以囊封导线48。在一些实施例中,导电结构64(例如,UBM)可以形成于第二RDL 50上方且电连接到第二RDL 50,并且从模制层54中暴露。在一些实施例中,导电凸块66可以安装在导电结构64的上方,并且电连接到导电结构64。
如图2E中所描绘,第二RDL 50附接到另一载体衬底12,并且从载体衬底10中释放第一RDL 20。在一些实施例中,第二RDL 50通过粘合剂层14附接到载体衬底12。在一些实施例中,一或多个第三电子组件60安置于或形成于第一RDL 20上方,并且通过第一RDL 20电连接到第一电子组件42和/或第二电子组件44。在一些实施例中,囊封物62形成于第一RDL20上方,囊封一或多个第三电子组件60。随后,从第二RDL 50中释放载体衬底12。如图1中所说明,形成半导体装置封装1。
本发明的半导体装置封装和制造方法不限于上述实施例,并且可以包含其它不同实施例。出于简化描述的目的且为了方便在本发明的实施例中的每一个之间进行比较,以下实施例中的每一个中的相同组件标记有相同标号,且不过多地加以描述。
在一些实施例中,第三电子组件60可以安置在半导体装置封装的任一侧上。换句话说,第三电子组件60可以安置为邻近于第一RDL 20或第二RDL 50。图3是根据本发明的一些实施例的半导体装置封装2的截面图。与如图1中所示的半导体装置封装1不同,如图3中所示的半导体装置封装2包含半导体装置封装2的第三电子组件60,所述第三电子组件60安置在第二RDL 50上方并且与第一电子组件42和第二电子组件44相对。在一些实施例中,至少一个第三电子组件60通过第二RDL 50电连接到第一电子组件42和/或第二电子组件44。在一些实施例中,可以省略模制层54,并且半导体装置封装2的囊封物62安置在第二RDL 50上方且囊封至少一个第三电子组件60和导线48。在一些其它实施例中,囊封物62囊封至少一个第三电子组件60的一部分。在一些实施例中,半导体装置封装2的导电结构64可以安置在第一RDL 20上方且电连接到第一RDL 20,并且导电凸块66可以安装在导电结构64上方且电连接到导电结构64。
图4A、图4B、图4C、图4D和图4E说明根据本发明的一些实施例的半导体装置封装2的制造方法的实例的各个阶段。如图4A中所描绘,包含第一导电零件22的第一RDL 20形成于载体衬底10的上方。
如图4B中所描绘,感应柱32形成于第一RDL 20上方,并且电连接到第一导电零件22。在一些实施例中,连接柱46形成于第一RDL 20上方,并且电连接到第一RDL 20。在一些实施例中,感应柱32和连接柱46在相同的过程中同时形成。在一些其它实施例中,感应柱32在形成连接柱46之前或在形成连接柱46之后形成。在一些实施例中,一或多个第一电子组件42和一或多个第二电子组件44安装在第一RDL 20上并且电连接到第一RDL 20。
如图4C中所描绘,介电层40形成于第一RDL 20上方。在一些实施例中,第一导电零件22、感应柱32、连接柱46、第一电子组件42和第二电子组件44的至少一些部分通过介电层40囊封。在一些实施例中,感应柱32、连接柱46、第一电子组件42和第二电子组件44的至少一些部分是从介电层40的第二表面402中暴露的。
如图4D中所描绘,包含第二导电零件52的第二RDL50形成于介电层40的第二表面402上方。第二导电零件52电连接到感应柱32的至少一部分。第二RDL 50电连接到连接柱46。第二导电零件52、感应柱32和第一导电零件22电连接并且共同地形成电感器30。在一些实施例中,可形成至少一个导线48以在导线48的一端处电连接第二导电零件52中的一个,并且在导线48的另一端处电连接第二导电零件52中的另一个。在一些实施例中,可以通过导线接合形成导线48,但不限于此。在一些实施例中,一或多个第三电子组件60安置于或形成于第二RDL 50上方,并且通过第二RDL 50电连接到第一电子组件42和/或第二电子组件44。
如图4E中所描绘,囊封物62形成于第二RDL 50上方,囊封至少一个第三电子组件60和导线48。随后,从载体衬底10中释放第一RDL 20。在一些实施例中,导电结构64(例如,UBM)可以形成于第一RDL 20上方,并且导电凸块66可以安装在导电结构64上方且电连接到导电结构64以形成半导体装置封装2。
在一些实施例中,第一电子组件42和第二电子组件44可以安置于第一RDL 20上方或第二RDL 50上方。图5是根据本发明的一些实施例的半导体装置封装3的截面图。与如图1中所示的半导体装置封装1不同,半导体装置封装3包含如图5中所示的安置在第一RDL 20上方且电连接到第一RDL 20的第一电子组件42和第二电子组件44。在一些实施例中,至少一个导线48安置在第二RDL 50上方,并且通过第二RDL 50电连接到第二导电零件52。在一些实施例中,第三电子组件60安置于或形成于第二RDL 50上方,并且通过第二RDL 50电连接到第一电子组件42和第二电子组件44。在一些实施例中,囊封物62安置在第二RDL 50上方,囊封至少一个第三电子组件60和导线48以及第一电子组件42和第二电子组件44。在一些实施例中,导电凸块66可以安装在第一RDL 20上方,并且电连接到第一RDL 20。
图6A、图6B、图6C、图6D和图6E说明根据本发明的一些实施例的半导体装置封装3的制造方法的实例的各个阶段。如图6A中所描绘,包含第一导电零件22的第一RDL 20形成于载体衬底10的上方。
如图6B中所描绘,感应柱32形成于第一RDL 20上方,并且电连接到第一导电零件22。在一些实施例中,连接柱46形成于第一RDL 20上方,并且电连接到第一RDL 20。在一些实施例中,感应柱32和连接柱46在相同的过程中同时形成。在一些其它实施例中,感应柱32在形成连接柱46之前或在形成连接柱46之后形成。在一些实施例中,介电层40形成于第一RDL 20上方。在一些实施例中,第一导电零件22、感应柱32和连接柱46的至少一些部分通过介电层40囊封。在一些实施例中,感应柱32和连接柱46的至少一些部分从介电层40的第二表面402中暴露。
如图6D中所描绘,包含第二导电零件52的第二RDL50形成于介电层40的第二表面402上方。第二导电零件52电连接到感应柱32的至少一部分。第二RDL 50电连接到连接柱46。第二导电零件52、感应柱32和第一导电零件22电连接并且共同地形成电感器30。
如图6D中所描绘,移除绝缘层502的一部分和介电层40的一部分(例如,通过喷砂)以暴露第一RDL 20的一部分。
如6E图中所描绘,一或多个第一电子组件42和一或多个第二电子组件44安置在第一RDL 20上且电连接到第一RDL 20,所述第一RDL 20从介电层40中暴露。在一些实施例中,一或多个第三电子组件60安置在第二RDL 50上方,并且电连接到第二RDL50。在一些实施例中,可形成至少一个导线48以在导线48的一端处电连接第二导电零件52中的一个,并且在导线48的另一端处电连接第二导电零件52中的另一个。在一些实施例中,囊封物62形成于第二RDL 50上方,囊封第一电子组件42、第二电子组件44、第三电子组件60和导线48的至少一些部分。在一些实施例中,随后,从载体衬底10中释放第一RDL 20。在一些实施例中,导电凸块66可以安装在第一RDL 20上方并且电连接到第一RDL 20以形成半导体装置封装3。
在一些实施例中,半导体装置封装可以包含安置在两个RDL之间的一或多个电子组件和囊封一或多个电子组件的模制层。图7是根据本发明的一些实施例的半导体装置封装4的截面视图。如图7中所示,半导体装置封装4包含介电层40、电感器30、第一RDL 20、第二RDL 50、一或多个第一电子组件42和一或多个第二电子组件44。介电层40包含第一表面401和与第一表面401相对的第二表面402。在一些实施例中,介电层40可以包含(但不限于)光固化材料或可由光固化材料形成(但不限于此),例如光阻剂或类似物。
在一些实施例中,第一RDL 20安置为邻近于介电层40的第一表面401,并且第二RDL 50安置为邻近于介电层40的第二表面402。在一些实施例中,第一RDL 20包含一或多个导电层201和堆叠到彼此的一或多个绝缘层202。导电层201中的一个可以包含从绝缘层202中暴露且邻近于介电层40的第一表面401的第一导电零件22。在一些实施例中,第一导电零件22安置在介电层40的第一表面401上方。在一些实施例中,第二RDL 50包含一或多个导电层501和堆叠到彼此的一或多个绝缘层502。导电层501中的一个可以包含从绝缘层502中暴露且邻近于介电层40的第二表面402的第二导电零件52。在一些实施例中,第二导电零件52安置在介电层40的第二表面402上方。
电感器30安置于介电层40中。在一些实施例中,电感器30包含感应柱32。感应柱32中的每一个穿透穿过介电层40,并且感应柱32中的每一个在第一RDL 20的第一导电零件22中的相应一个与第二RDL 50的第二导电零件52中的相应一个之间互连。在一些实施例中,感应柱32的高度H大体上等于介电层40的厚度T。在一些实施例中,感应柱32中的至少一些通过第一导电零件22和第二导电零件52电连接。在一些实施例中,电感器30包含基本上垂直于介电层40的第一表面401或第二表面402的至少一个核心区,其中所述核心区包含感应柱32中的一或多个。
在一些实施例中,第一电子组件42和第二电子组件44在第一RDL 20与第二RDL50之间。在一些实施例中,半导体装置封装4进一步包含由介电层40围绕的模制层55,并且所述模制层55囊封第一电子组件42和第二电子组件44。在一些实施例中,第一电子组件42和第二电子组件44可以通过电感器30电连接到彼此。在一些实施例中,第一电子组件42和第二电子组件44可以相应地通过导电结构42C和导电结构44C电连接到第一RDL 20。导电结构42C和导电结构44C可以包含导电柱、导电桩、接合垫或类似物。
在一些实施例中,半导体装置封装4进一步包含穿透穿过介电层40且电连接到第一RDL 20和第二RDL 50的连接柱46。在一些实施例中,第一电子组件42和第二电子组件44通过电感器30和连接柱46进一步电连接到第二RDL 50。在一些实施例中,导电结构42C和导电结构44C短于感应柱32和连接柱46。在一些实施例中,导电结构42C、导电结构44C、感应柱32和连接柱46中的每一个的至少一端可以基本上在与第一RDL20相同的水平处并且电连接到第一RDL 20。
在一些实施例中,半导体装置封装4进一步包含安置在第一RDL 20上方且与第一电子组件42和第二电子组件44相对的一或多个第三电子组件60。在一些实施例中,至少一个第三电子组件60通过第一RDL 20电连接到第一电子组件42和第二电子组件44。在一些实施例中,半导体装置封装4可以进一步包含安置在第一RDL 20上方的至少一个导线48。导线48可以在导线48的一端处电连接到第一导电零件22中的一个,并且在导线48的另一端处电连接到第一导电零件22中的另一个。在一些实施例中,可以通过导线接合形成导线48。导线48可以在形成电感器30之后形成,并且因此可经配置以调节电感器30的阻抗(如果电感器30的实际阻抗偏离预先设计的阻抗)。
在一些实施例中,半导体装置封装4可以进一步包含安置在第一RDL 20上方且囊封至少一个第三电子组件60和导线48的囊封物62。在一些实施例中,半导体装置封装4可以进一步包含导电凸块66(例如,焊料凸块、焊料球、焊料膏或类似物),所述导电凸块66安装在第二RDL 50上方且电连接到第二RDL 50,并且经配置以电连接到其它电子装置(例如,电路板或类似物)。
图8A、图8B、图8C、图8D和图8E说明根据本发明的一些实施例的半导体装置封装4的制造方法的实例的各个阶段。如图8A中所描绘,晶种层13形成于载体衬底10上方。在一些实施例中,晶种层13可以包含钛铜晶种层,但并不限于此。介电层40形成于晶种层13上方。在一些实施例中,介电层40可以包含(但不限于)光固化材料或可由光固化材料形成(但不限于此),例如光阻剂或类似物。在一些实施例中,介电层40包含至少部分暴露晶种层13的一或多个开口40H。
如图8B中所描绘,感应柱32穿过至少一些开口40H形成于晶种层13上方,例如,通过电镀。在一些实施例中,连接柱46穿过开口40H中的至少一些形成于晶种层13上方。在一些实施例中,感应柱32和连接柱46在相同的过程中同时形成。在一些其它实施例中,感应柱32在形成连接柱46之前或在形成连接柱46之后形成。在一些实施例中,移除介电层40的一部分(例如,通过喷砂)以暴露晶种层13的一部分。在一些实施例中,一或多个第一电子组件42和一或多个第二电子组件44安装在晶种层13上方,例如,通过在介电层40中形成开口且在开口中安装第一电子组件42和第二电子组件44。
如图8C中所描绘,模制层55形成于暴露的晶种层13上方,且囊封第一电子组件42和第二电子组件44。在一些实施例中,薄化(例如,通过研磨)模制层55以暴露感应柱32、连接柱46、导电结构42C和导电结构44C的至少一些部分。如图8D中所描绘,包含第一导电零件22的第一RDL 20形成于介电层40的第一表面401上方,并且电连接到感应柱32、连接柱46、导电结构42C和导电结构44C。在一些实施例中,一或多个第三电子组件60安置在第一RDL20上方,并且电连接到第一RDL 20。在一些实施例中,可形成至少一个导线48以通过第一RDL 20电连接第一导电零件22的一部分。
如图8E中所描绘,囊封物62形成于第一RDL 20上方,并且囊封至少一个第三电子组件60和导线48。在一些实施例中,随后从载体衬底10和晶种层13中释放介电层40。在一些实施例中,包含第二导电零件52的第二RDL 50形成于介电层40的第二表面402上方,并且电连接到感应柱32和连接柱46。第二导电零件52、感应柱32和第一导电零件22电连接并且共同地形成电感器30。在一些实施例中,导电凸块66可以安装在第二RDL 50上方且电连接到第二RDL 50以形成半导体装置封装4。
除非上下文另外明确规定,否则如本文所用,单数术语“一(a/an)”和“所述”可包含多个指示物。
如本文所使用,术语“导电(conductive、electrically conductive)”和“电导率”指代传递电流的能力。导电材料通常指示呈现对于电流流动的极少或零对抗的那些材料。电导率的一个量度为西门子每米(S/m)。通常,导电材料为电导率大于近似104S/m(例如,至少105S/m或至少106S/m)的一种材料。材料的电导率有时可随温度而变化。除非另外说明,否则材料的电导率是在室温下测量的。
如本文中所使用,术语“近似”、“基本上”、“实质”和“约”用于描述和解释小的变化。当与事件或情况结合使用时,所述术语可指事件或情况精确发生的例子以及事件或情况极近似地发生的例子。举例来说,当结合数值使用时,术语可指小于或等于所述数值的±10%的变化范围,例如,小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%、或小于或等于±0.05%。举例来说,如果两个数值之间的差小于或等于所述值的平均值的±10%(例如小于或等于±5%、小于或等于±4%、小于或等于±3%、小于或等于±2%、小于或等于±1%、小于或等于±0.5%、小于或等于±0.1%,或小于或等于±0.05%),那么可认为所述两个数值“基本上”相同或相等。举例来说,“基本上”平行可指代相对于0°的小于或等于±10°的角度变化范围,例如,小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。举例来说,“基本上”垂直可指代相对于90°的小于或等于±10°的角度变化范围,例如,小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°,或小于或等于±0.05°。
此外,有时在本文中以范围格式呈现量、比率和其它数值。应理解,此类范围格式是用于便利和简洁起见,且应灵活地理解,不仅包含明确地指定为范围界限的数值,且还包含涵盖于所述范围内的所有个体数值或子范围,如同明确地规定每一数值和子范围一般。
尽管已参考本发明的具体实施例描述并说明本发明,但这些描述和说明并不限制本发明。所属领域的技术人员应理解,可在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下,作出各种改变且取代等效物。所述图式可能未必按比例绘制。归因于制造过程及容差,本发明中的艺术再现与实际设备之间可能存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可做出修改,以使特定情况、材料、物质组成、方法或过程适应于本发明的目标、精神以及范围。所有此类修改都意图在所附权利要求书的范围内。虽然本文中所揭示的方法已参考按特定次序执行的特定操作加以描述,但应理解,可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序和分组并非本发明的限制。
Claims (20)
1.一种半导体装置封装,其包括:
介电层,其包括第一表面和与所述第一表面相对的第二表面;
第一再分布层RDL,其邻近于所述介电层的所述第一表面,所述第一RDL包括多个第一导电零件;
第二RDL,其邻近于所述介电层的所述第二表面,所述第二RDL包括多个第二导电零件;
电感器,其安置于所述介电层中,所述电感器包括多个感应柱,其中穿过所述介电层安置所述感应柱中的每一个,并且所述感应柱中的每一个在所述第一RDL的所述第一导电零件中的相应一个与所述第二RDL的所述第二导电零件中的相应一个之间互连;以及
第一电子组件和第二电子组件,其在所述第一RDL与所述第二RDL之间且通过所述电感器电连接到彼此。
2.根据权利要求1所述的半导体装置封装,其中所述第一电子组件包括有源组件,并且所述第二电子组件包括无源组件。
3.根据权利要求1所述的半导体装置封装,其中所述介电层包括聚合物介电层,并且所述聚合物介电层的材料包括光固化材料。
4.根据权利要求1所述的半导体装置封装,其进一步包括穿过所述介电层安置且电连接到所述第一RDL和所述第二RDL的多个连接柱。
5.根据权利要求1所述的半导体装置封装,其中所述第一RDL进一步包括绝缘层,并且所述绝缘层的硬度大于所述介电层的硬度。
6.根据权利要求1所述的半导体装置封装,其进一步包括在所述第一RDL或所述第二RDL上方的第三电子组件,其中所述第三电子组件安置成与所述第一电子组件和所述第二电子组件相对。
7.根据权利要求1所述的半导体装置封装,其进一步包括在所述第一RDL或所述第二RDL上方的导线,其中所述导线在所述导线的一端处电连接到所述第一导电零件或所述第二导电零件中的一个,并且在所述导线的另一端处电连接到所述第一导电零件或所述第二导电零件中的另一个。
8.根据权利要求1所述的半导体装置封装,其进一步包括由所述介电层围绕的模制层,所述模制层囊封所述第一电子组件和所述第二电子组件。
9.一种半导体装置封装,其包括:
介电层,其包括第一表面和与所述第一表面相对的第二表面;
第一电子组件和第二电子组件,其安置于所述介电层中;以及
电感器,其安置于所述介电层中且电连接到所述第一电子组件和所述第二电子组件,所述电感器包括基本上垂直于所述介电层的所述第一表面或所述第二表面的至少一个核心区。
10.根据权利要求9所述的半导体装置封装,其中所述电感器包含穿过所述介电层的多个感应柱,所述感应柱的高度大体上等于所述介电层的厚度。
11.根据权利要求9所述的半导体装置封装,其进一步包括在所述介电层的所述第一表面上方的多个第一导电零件和在所述介电层的所述第二表面上方的多个第二导电零件。
12.根据权利要求11所述的半导体装置封装,其中所述电感器包括穿过所述介电层且通过所述第一导电零件和所述第二导电零件电连接到彼此的多个感应柱。
13.根据权利要求9所述的半导体装置封装,其进一步包括邻近于所述介电层的所述第一表面的第一再分布层RDL和邻近于所述介电层的所述第二表面的第二RDL。
14.根据权利要求13所述的半导体装置封装,其中所述第一RDL和所述第二RDL中的至少一个进一步包括绝缘层,并且所述绝缘层的硬度大于所述介电层的硬度。
15.根据权利要求13所述的半导体装置封装,其进一步包括穿过所述介电层的多个连接柱,所述连接柱电连接到所述第一RDL和所述第二RDL。
16.根据权利要求13所述的半导体装置封装,其进一步包括在所述第一RDL或所述第二RDL上方的第三电子组件,其中所述第三电子组件安置成与所述第一电子组件和所述第二电子组件相对。
17.根据权利要求9所述的半导体装置封装,其中所述第一电子组件包括有源组件,并且所述第二电子组件包括无源组件。
18.一种半导体装置封装,其包括:
介电层,其包括第一表面和与所述第一表面相对的第二表面;
电感器,其安置于所述介电层中,所述电感器包括穿过所述介电层的多个感应柱;
多个导电零件,其在所述介电层的所述第一表面和所述第二表面上方且电连接到所述感应柱的一部分;以及
导线,其电连接到所述感应柱中的至少一个且经配置以调节所述电感器的阻抗。
19.根据权利要求18所述的半导体装置封装,其进一步包括囊封所述导线的模制层。
20.根据权利要求18所述的半导体装置封装,其中所述感应柱的高度大体上等于所述介电层的厚度。
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Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20140312458A1 (en) * | 2013-04-18 | 2014-10-23 | Fairchild Semiconductor Corporation | Methods and apparatus related to an improved package including a semiconductor die |
US20150031184A1 (en) * | 2013-01-23 | 2015-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing a package |
US20150042438A1 (en) * | 2013-08-12 | 2015-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Tunable three dimensional inductor |
US20150364532A1 (en) * | 2014-06-13 | 2015-12-17 | United Microelectronics Corp. | Inductor formed on a semiconductor substrate |
CN105448885A (zh) * | 2014-08-06 | 2016-03-30 | 瑞昱半导体股份有限公司 | 集成电感结构 |
CN106560918A (zh) * | 2015-10-05 | 2017-04-12 | 联发科技股份有限公司 | 半导体封装结构及其形成方法 |
US20180138126A1 (en) * | 2016-11-17 | 2018-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of forming thereof |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8445325B2 (en) * | 2007-05-04 | 2013-05-21 | Stats Chippac, Ltd. | Package-in-package using through-hole via die on saw streets |
US8525344B2 (en) * | 2011-02-24 | 2013-09-03 | Stats Chippac, Ltd. | Semiconductor device and method of forming bond wires between semiconductor die contact pads and conductive TOV in peripheral area around semiconductor die |
CN104334333B (zh) * | 2012-05-24 | 2017-03-01 | 旭硝子株式会社 | 光学构件的制造方法、光学构件、带有保护膜的光学构件以及光学面板的制造方法 |
US9978654B2 (en) | 2012-09-14 | 2018-05-22 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming dual-sided interconnect structures in Fo-WLCSP |
US8975726B2 (en) * | 2012-10-11 | 2015-03-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | POP structures and methods of forming the same |
US9922844B2 (en) * | 2014-03-12 | 2018-03-20 | Mediatek Inc. | Semiconductor package and method for fabricating base for semiconductor package |
US9601463B2 (en) | 2014-04-17 | 2017-03-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out stacked system in package (SIP) and the methods of making the same |
US10424563B2 (en) | 2015-05-19 | 2019-09-24 | Mediatek Inc. | Semiconductor package assembly and method for forming the same |
US9373605B1 (en) * | 2015-07-16 | 2016-06-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | DIE packages and methods of manufacture thereof |
US9837352B2 (en) * | 2015-10-07 | 2017-12-05 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and method for manufacturing the same |
US9953892B2 (en) * | 2015-11-04 | 2018-04-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Polymer based-semiconductor structure with cavity |
US9627365B1 (en) * | 2015-11-30 | 2017-04-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tri-layer CoWoS structure |
-
2017
- 2017-05-18 US US15/599,379 patent/US10475718B2/en active Active
- 2017-10-18 CN CN201710969639.4A patent/CN108962871B/zh active Active
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Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20150031184A1 (en) * | 2013-01-23 | 2015-01-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods of manufacturing a package |
US20140312458A1 (en) * | 2013-04-18 | 2014-10-23 | Fairchild Semiconductor Corporation | Methods and apparatus related to an improved package including a semiconductor die |
US20150042438A1 (en) * | 2013-08-12 | 2015-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Tunable three dimensional inductor |
US20150364532A1 (en) * | 2014-06-13 | 2015-12-17 | United Microelectronics Corp. | Inductor formed on a semiconductor substrate |
CN105448885A (zh) * | 2014-08-06 | 2016-03-30 | 瑞昱半导体股份有限公司 | 集成电感结构 |
CN106560918A (zh) * | 2015-10-05 | 2017-04-12 | 联发科技股份有限公司 | 半导体封装结构及其形成方法 |
US20180138126A1 (en) * | 2016-11-17 | 2018-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method of forming thereof |
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