CN103986323A

CN103986323A - Intelligent power module

Info

Publication number: CN103986323A
Application number: CN201410206541.XA
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd
Current assignee: Midea Group Co Ltd
Priority date: 2014-05-15
Filing date: 2014-05-15
Publication date: 2014-08-13
Anticipated expiration: 2034-05-15
Also published as: CN103986323B

Abstract

The invention discloses an intelligent power module. The intelligent power module comprises a working voltage input end, a maximum voltage end, a U-phase high-voltage area power supply negative terminal, a V-phase high-voltage area power supply negative terminal, a W-phase high-voltage area power supply negative terminal, a U-phase upper bridge arm IGBT, a V-phase upper bridge arm IGBT, a W-phase upper bridge arm IGBT, a U-phase lower bridge arm IGBT, a V-phase lower bridge arm IGBT, a W-phase lower bridge arm IGBT, a U-phase upper bridge arm MOS tube, a V-phase upper bridge arm MOS tube, a W-phase upper bridge arm MOS tube, a U-phase lower bridge arm MOS tube, a V-phase lower bridge arm MOS tube, a W-phase lower bridge arm MOS tube, upper bridge arm driving circuits which are arranged corresponding to the upper bridge arm IGBTs respectively, and lower bridge arm driving circuits which are arranged corresponding to the lower bridge arm IGBTs respectively. The intelligent power module can reduce interference on a power grid, and is good in stability.

Description

Intelligent Power Module

Technical field

The present invention relates to electronic technology field, particularly a kind of Intelligent Power Module.

Background technology

Intelligent Power Module, IPM (Intelligent Power Module) is a kind of by the power drive series products of power electronics and integrated circuit technique combination.Intelligent Power Module integrates device for power switching and high-voltage driving circuit, compared with the discrete scheme of tradition, Intelligent Power Module wins increasing market with advantages such as its high integration, high reliability, be particularly suitable for frequency converter and the various inverter of drive motors, frequency control, metallurgical machinery, electric traction, servo-drive, the desirable power electronic device of one of frequency-conversion domestic electric appliances.

But, Intelligent Power Module in actual applications, while being particularly applied to transducer air conditioning, due to too fast cause very serious to the interference of electrical network of switching speed of the IGBT pipe in Intelligent Power Module.In prior art, in order to weaken the interference of Intelligent Power Module to electrical network, normally equal capacitor in parallel between the collector electrode of each IGBT pipe of Intelligent Power Module and emitter-base bandgap grading, with the switching speed of the IGBT pipe that slows down, thereby reduce its interference to electrical network, but this scheme need to be at six capacitors of the peripheral additional configuration of Intelligent Power Module, thereby increase cost, increase the area of the automatically controlled version in periphery of Intelligent Power Module, meanwhile, the cabling between from Intelligent Power Module to external capacitor has also affected the effect of capacitor to a certain extent.And, in transducer air conditioning industry, in the time of the exploitation of electric-controlled plate of mating Intelligent Power Module, in order to shield the interference of Intelligent Power Module to electrical network, in circuit design, require a great deal of time and manpower, six capacitors of the peripheral institute additional configuration of Intelligent Power Module choose and wiring need to be accomplished its rectifying and improving by the mode of trial and error repeatedly conventionally, this exploitation has uncertainty, and can be because reasons such as the processing of electric-controlled plate, make identical interference shielding scheme also can cause different interference shielding effects, and, the detection of the interference of Intelligent Power Module to electrical network, cannot entirely examine, so disturb large Intelligent Power Module also can be devoted to market to electrical network, consumer's complaint is happened occasionally, and enterprise is to complaining product often can only scrap processing, undoubtedly enterprise is caused to serious loss, simultaneously, also can have influence on the public praise of product, thereby make the application department of Intelligent Power Module produce and resist sense the use of existing Intelligent Power Module, hinder the spread of Intelligent Power Module in frequency conversion field.

Summary of the invention

Main purpose of the present invention is to provide a kind of Intelligent Power Module, is intended to reduce the interference of Intelligent Power Module to electrical network.

The present invention proposes a kind of Intelligent Power Module, comprise operating voltage input, ceiling voltage end, U phase higher-pressure region power supply negative terminal, V phase higher-pressure region power supply negative terminal, W phase higher-pressure region power supply negative terminal, U goes up brachium pontis IGBT pipe mutually, V goes up brachium pontis IGBT pipe mutually, W goes up brachium pontis IGBT pipe mutually, U descends brachium pontis IGBT pipe mutually, V descends brachium pontis IGBT pipe mutually, W descends brachium pontis IGBT pipe mutually, U goes up brachium pontis metal-oxide-semiconductor mutually, V goes up brachium pontis metal-oxide-semiconductor mutually, W goes up brachium pontis metal-oxide-semiconductor mutually, U descends brachium pontis metal-oxide-semiconductor mutually, V descends brachium pontis metal-oxide-semiconductor mutually, W descends brachium pontis metal-oxide-semiconductor mutually, and corresponding each described upper brachium pontis IGBT manages the upper brachium pontis drive circuit of setting and the lower brachium pontis drive circuit of corresponding each described lower brachium pontis IGBT pipe setting, wherein,

The gate pole that U goes up that brachium pontis IGBT pipe, V go up that brachium pontis IGBT manages mutually mutually and W goes up brachium pontis IGBT pipe mutually is all connected with upper brachium pontis drive circuit; U descends brachium pontis IGBT pipe, V to descend mutually brachium pontis IGBT pipe and W to descend mutually the gate pole of brachium pontis IGBT pipe to be all connected with lower brachium pontis drive circuit mutually; The emitter that U goes up brachium pontis IGBT pipe mutually descends the collector electrode of brachium pontis IGBT pipe to be connected with U mutually, and is connected with U phase higher-pressure region power supply negative terminal; The emitter that V goes up brachium pontis IGBT pipe mutually descends the collector electrode of brachium pontis IGBT pipe to be connected with V mutually, and is connected with V phase higher-pressure region power supply negative terminal; The emitter that W goes up brachium pontis IGBT pipe mutually descends the collector electrode of brachium pontis IGBT pipe to be connected with W mutually, and is connected with W phase higher-pressure region power supply negative terminal; The collector electrode that U goes up that brachium pontis IGBT pipe, V go up that brachium pontis IGBT manages mutually mutually and W goes up brachium pontis IGBT pipe mutually is all connected with ceiling voltage end; The equal ground connection of emitter that U descends brachium pontis IGBT pipe, V to descend mutually brachium pontis IGBT pipe and W to descend mutually brachium pontis IGBT pipe mutually; The source electrode that U goes up brachium pontis metal-oxide-semiconductor is mutually connected with the emitter that U goes up brachium pontis IGBT pipe mutually, and the source electrode that V goes up brachium pontis metal-oxide-semiconductor is mutually connected with the emitter that V goes up brachium pontis IGBT pipe mutually, and the source electrode that W goes up brachium pontis metal-oxide-semiconductor is mutually connected with the emitter that W goes up brachium pontis IGBT pipe mutually; U descends the source electrode of brachium pontis metal-oxide-semiconductor to descend mutually the emitter of brachium pontis IGBT pipe to be connected with U mutually, and V descends the source electrode of brachium pontis metal-oxide-semiconductor to descend mutually the emitter of brachium pontis IGBT pipe to be connected with V mutually, and W descends the source electrode of brachium pontis metal-oxide-semiconductor to descend mutually the emitter of brachium pontis IGBT pipe to be connected with W mutually; U goes up mutually brachium pontis metal-oxide-semiconductor, V and goes up mutually the grid that brachium pontis metal-oxide-semiconductor and W go up brachium pontis metal-oxide-semiconductor mutually and be all connected with upper brachium pontis drive circuit with drain electrode, and U descends brachium pontis metal-oxide-semiconductor, V to descend mutually brachium pontis metal-oxide-semiconductor, W to descend mutually the grid of brachium pontis metal-oxide-semiconductor to be all connected with lower brachium pontis drive circuit with draining mutually.

Preferably, described upper brachium pontis drive circuit comprises that U goes up that brachium pontis drive circuit, V go up brachium pontis drive circuit mutually and W goes up brachium pontis drive circuit mutually mutually; Described U goes up mutually brachium pontis drive circuit, V and goes up mutually brachium pontis drive circuit and W and go up mutually brachium pontis drive circuit and include gate signal output, drain signal output and signal output, wherein,

The gate pole that described U goes up brachium pontis IGBT pipe is mutually connected with the gate signal output that described U goes up brachium pontis drive circuit mutually, the gate pole that described V goes up brachium pontis IGBT pipe is mutually connected with the gate signal output that described V goes up brachium pontis drive circuit mutually, and the gate pole that described W goes up brachium pontis IGBT pipe is mutually connected with the gate signal output that described W goes up brachium pontis drive circuit mutually; The drain electrode that described U goes up brachium pontis metal-oxide-semiconductor is mutually connected with the drain signal output that described U goes up brachium pontis drive circuit mutually, the drain electrode that described V goes up brachium pontis metal-oxide-semiconductor is mutually connected with the drain signal output that described V goes up brachium pontis drive circuit mutually, and the drain electrode that described W goes up brachium pontis metal-oxide-semiconductor is mutually connected with the drain signal output that described W goes up brachium pontis drive circuit mutually; The grid that described U goes up brachium pontis metal-oxide-semiconductor is mutually connected with the signal output that described U goes up brachium pontis drive circuit mutually, the grid that described V goes up brachium pontis metal-oxide-semiconductor is mutually connected with the signal output that described V goes up brachium pontis drive circuit mutually, and the grid that described W goes up brachium pontis metal-oxide-semiconductor is mutually connected with the signal output that described W goes up brachium pontis drive circuit mutually.

Preferably, described lower brachium pontis drive circuit comprises that U descends brachium pontis drive circuit, V to descend mutually brachium pontis drive circuit and W to descend mutually brachium pontis drive circuit mutually; Described U descends brachium pontis drive circuit, V to descend mutually brachium pontis drive circuit and W to descend mutually brachium pontis drive circuit to include gate signal output, drain signal output and signal output mutually, wherein,

Described U descends the gate pole of brachium pontis IGBT pipe to descend mutually the gate signal output of brachium pontis drive circuit to be connected with described U mutually, described V descends the gate pole of brachium pontis IGBT pipe to descend mutually the gate signal output of brachium pontis drive circuit to be connected with described V mutually, and described W descends the gate pole of brachium pontis IGBT pipe to descend mutually the gate signal output of brachium pontis drive circuit to be connected with described W mutually; Described U descends the drain electrode of brachium pontis metal-oxide-semiconductor to descend mutually the drain signal output of brachium pontis drive circuit to be connected with described U mutually, described V descends the drain electrode of brachium pontis metal-oxide-semiconductor to descend mutually the drain signal output of brachium pontis drive circuit to be connected with described V mutually, and described W descends the drain electrode of brachium pontis metal-oxide-semiconductor to descend mutually the drain signal output of brachium pontis drive circuit to be connected with described W mutually; Described U descends the grid of brachium pontis metal-oxide-semiconductor to descend mutually the signal output of brachium pontis drive circuit to be connected with described U mutually, described V descends the grid of brachium pontis metal-oxide-semiconductor to descend mutually the signal output of brachium pontis drive circuit to be connected with described V mutually, and described W descends the grid of brachium pontis metal-oxide-semiconductor to descend mutually the signal output of brachium pontis drive circuit to be connected with described W mutually.

Preferably, described U goes up mutually brachium pontis drive circuit and also comprises brachium pontis control signal input, U phase higher-pressure region power supply anode, U phase higher-pressure region power supply negative terminal, dipulse circuit for generating, the first high pressure DMOS pipe, the second high pressure DMOS pipe, bootstrap diode, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the first diode, the second diode, the first electric capacity, the second electric capacity, the first non-gate cell, the second non-gate cell, the 3rd non-gate cell, the first Schmidt trigger, second this schmitt trigger, rest-set flip-flop, the first not gate, the second not gate, the 3rd not gate, the 4th not gate, the first optocoupler, the second optocoupler, the 3rd optocoupler and the 4th optocoupler, wherein,

The input of dipulse circuit for generating is connected with upper brachium pontis control signal input, its first output is connected with the grid of the first high pressure DMOS pipe, its second output is connected with the grid of the second high pressure DMOS pipe, and its power end is connected with described operating voltage input, its ground end ground connection; The substrate of the first high pressure DMOS pipe is connected with source electrode and ground connection, and its drain electrode is connected with higher-pressure region power supply anode through the first resistance; The substrate of the second high pressure DMOS pipe is connected with source and ground connection, and its drain electrode is connected with higher-pressure region power supply anode through the second resistance; The anode of bootstrap diode is connected with described operating voltage input, and negative electrode is connected with higher-pressure region power supply anode; The input of the first non-gate cell is connected with the drain electrode of the first high pressure DMOS pipe, and is connected with the negative electrode of the first diode, and the output of the first non-gate cell is connected with the input of the first not gate through the first Schmidt trigger; The output of the first not gate is connected with the S of rest-set flip-flop end; The anode of the first diode is connected with the output of the first non-gate cell through the first electric capacity; The input of the second non-gate cell is connected with the drain electrode of the second high pressure DMOS pipe, and is connected with the negative electrode of the second diode, and the output of the second non-gate cell is connected with the input of the second not gate through the second Schmidt trigger; The output of the second not gate is connected with the R of rest-set flip-flop end; The anode of the second diode is connected with the output of the second non-gate cell through the second electric capacity; The anode of the anode of the first diode and the second diode is also connected with higher-pressure region power supply negative terminal; The output of rest-set flip-flop is connected with the gate signal output that described U goes up brachium pontis drive circuit mutually through the 3rd non-gate cell; The first end of the 3rd resistance is connected with the input of dipulse circuit for generating, the anodic bonding of the light-emitting diode of its second end and the first optocoupler; The input of the 4th not gate is connected with the first end of the 3rd resistance, and its output is through the anodic bonding of the light-emitting diode of the 4th resistance and the second optocoupler; The input of the 3rd not gate is connected with the first end of the 3rd resistance, and its output is through the anodic bonding of the light-emitting diode of the 5th resistance and the 3rd optocoupler; The first end of the 6th resistance is connected with the first end of the 3rd resistance, the anodic bonding of the light-emitting diode of its second end and the 4th optocoupler; The equal ground connection of negative electrode of the negative electrode of the negative electrode of the negative electrode of the light-emitting diode of the first optocoupler, the light-emitting diode of the second optocoupler, the light-emitting diode of the 3rd optocoupler and the light-emitting diode of the 4th optocoupler; The collector electrode of the triode of the collector electrode of the triode of the first optocoupler and the 3rd optocoupler is all connected with higher-pressure region power supply negative terminal; The collector electrode of the triode of the collector electrode of the triode of the second optocoupler and the 4th optocoupler is all connected with described ceiling voltage end; The drain signal output that the emitter of the triode of the emitter of the triode of the first optocoupler and the second optocoupler is all gone up brachium pontis drive circuit mutually with described U is connected; The signal output that the emitter of the triode of the emitter of the triode of the 3rd optocoupler and the 4th optocoupler is all gone up brachium pontis drive circuit mutually with described U is connected.

Preferably, described the first non-gate cell comprises three not gates of series connection successively, and described the second non-gate cell comprises three not gates of series connection successively, and described the 3rd non-gate cell comprises two not gates of series connection successively.

Preferably, described U descends brachium pontis drive circuit also to comprise lower brachium pontis control signal input, level shifting circuit, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 3rd electric capacity, the 4th electric capacity, the 5th not gate, the 6th not gate, the 7th not gate, the 8th not gate, the 9th not gate, the tenth not gate, the 11 not gate, the 12 not gate, the 5th optocoupler, the 6th optocoupler, the 7th optocoupler and the 8th optocoupler mutually; Wherein,

The input of level shifting circuit is connected with lower brachium pontis control signal input, the output of level shifting circuit descends the gate signal output of brachium pontis drive circuit to be connected through the 5th not gate, the 6th not gate, the 7th not gate, the 8th not gate, the 9th not gate and the tenth not gate of series connection mutually with described U mutually, the power end of level shifting circuit is connected with described operating voltage input, the ground end ground connection of level shifting circuit; The first end of the 3rd electric capacity is connected between the 7th not gate and the 8th not gate, the second end ground connection of the 3rd electric capacity; The first end of the 4th electric capacity is connected between the 8th not gate and the 9th not gate, the second end ground connection of the 4th electric capacity; The 7th first end of resistance and the input of level shifting circuit are connected, the anodic bonding of the light-emitting diode of its second end and the 5th optocoupler; The input of the 11 not gate is connected with the first end of the 7th resistance, and its output is through the anodic bonding of the light-emitting diode of the 8th resistance and the 6th optocoupler; The input of the 12 not gate is connected with the first end of the 7th resistance, and its output is through the anodic bonding of the light-emitting diode of the 9th resistance and the 7th optocoupler; The first end of the tenth resistance is connected with the first end of the 7th resistance, the anodic bonding of the light-emitting diode of its second end and the 8th optocoupler; The equal ground connection of negative electrode of the negative electrode of the negative electrode of the negative electrode of the light-emitting diode of the 5th optocoupler, the light-emitting diode of the 6th optocoupler, the light-emitting diode of the 7th optocoupler and the light-emitting diode of the 8th optocoupler; The equal ground connection of collector electrode of the triode of the collector electrode of the triode of the 5th optocoupler and the 7th optocoupler; The collector electrode of the triode of the collector electrode of the triode of the 6th optocoupler and the 8th optocoupler is all connected with described U phase higher-pressure region power supply negative terminal; The emitter of the triode of the emitter of the triode of the 5th optocoupler and the 6th optocoupler all descends the drain signal output of brachium pontis drive circuit to be connected with described U mutually; The emitter of the triode of the emitter of the triode of the 7th optocoupler and the 8th optocoupler all descends the signal output of brachium pontis drive circuit to be connected with described U mutually.

Preferably, described U goes up mutually brachium pontis metal-oxide-semiconductor, V and goes up mutually brachium pontis metal-oxide-semiconductor, W and go up mutually brachium pontis metal-oxide-semiconductor, U and descend mutually brachium pontis metal-oxide-semiconductor, V to descend mutually brachium pontis metal-oxide-semiconductor and W to descend mutually brachium pontis metal-oxide-semiconductor to be NMOS pipe.

Preferably, described V goes up mutually circuit structure that brachium pontis drive circuit and described W go up brachium pontis drive circuit mutually all to go up mutually the circuit structure of brachium pontis drive circuit identical with described U.

Preferably, described V descends brachium pontis drive circuit and described W to descend mutually the circuit structure of brachium pontis drive circuit all to descend mutually the circuit structure of brachium pontis drive circuit identical with described U mutually.

The Intelligent Power Module that the present invention proposes, comprise operating voltage input, ceiling voltage end, U phase higher-pressure region power supply negative terminal, V phase higher-pressure region power supply negative terminal, W phase higher-pressure region power supply negative terminal, U goes up brachium pontis IGBT pipe mutually, V goes up brachium pontis IGBT pipe mutually, W goes up brachium pontis IGBT pipe mutually, U descends brachium pontis IGBT pipe mutually, V descends brachium pontis IGBT pipe mutually, W descends brachium pontis IGBT pipe mutually, U goes up brachium pontis metal-oxide-semiconductor mutually, V goes up brachium pontis metal-oxide-semiconductor mutually, W goes up brachium pontis metal-oxide-semiconductor mutually, U descends brachium pontis metal-oxide-semiconductor mutually, V descends brachium pontis metal-oxide-semiconductor mutually, W descends brachium pontis metal-oxide-semiconductor mutually, and corresponding each upper brachium pontis IGBT manages the upper brachium pontis drive circuit of setting and the lower brachium pontis drive circuit of corresponding each lower brachium pontis IGBT pipe setting.Wherein, the gate pole that U goes up that brachium pontis IGBT pipe, V go up that brachium pontis IGBT manages mutually mutually and W goes up brachium pontis IGBT pipe mutually is all connected with upper brachium pontis drive circuit; U descends brachium pontis IGBT pipe, V to descend mutually brachium pontis IGBT pipe and W to descend mutually the gate pole of brachium pontis IGBT pipe to be all connected with lower brachium pontis drive circuit mutually; The emitter that U goes up brachium pontis IGBT pipe mutually descends the collector electrode of brachium pontis IGBT pipe to be connected with U mutually, and is connected with U phase higher-pressure region power supply negative terminal; The emitter that V goes up brachium pontis IGBT pipe mutually descends the collector electrode of brachium pontis IGBT pipe to be connected with V mutually, and is connected with V phase higher-pressure region power supply negative terminal; The emitter that W goes up brachium pontis IGBT pipe mutually descends the collector electrode of brachium pontis IGBT pipe to be connected with W mutually, and is connected with W phase higher-pressure region power supply negative terminal; The collector electrode that U goes up that brachium pontis IGBT pipe, V go up that brachium pontis IGBT manages mutually mutually and W goes up brachium pontis IGBT pipe mutually is all connected with ceiling voltage end; The equal ground connection of emitter that U descends brachium pontis IGBT pipe, V to descend mutually brachium pontis IGBT pipe and W to descend mutually brachium pontis IGBT pipe mutually; The source electrode that U goes up brachium pontis metal-oxide-semiconductor is mutually connected with the emitter that U goes up brachium pontis IGBT pipe mutually, and the source electrode that V goes up brachium pontis metal-oxide-semiconductor is mutually connected with the emitter that V goes up brachium pontis IGBT pipe mutually, and the source electrode that W goes up brachium pontis metal-oxide-semiconductor is mutually connected with the emitter that W goes up brachium pontis IGBT pipe mutually; U descends the source electrode of brachium pontis metal-oxide-semiconductor to descend mutually the emitter of brachium pontis IGBT pipe to be connected with U mutually, and V descends the source electrode of brachium pontis metal-oxide-semiconductor to descend mutually the emitter of brachium pontis IGBT pipe to be connected with V mutually, and W descends the source electrode of brachium pontis metal-oxide-semiconductor to descend mutually the emitter of brachium pontis IGBT pipe to be connected with W mutually; U goes up mutually brachium pontis metal-oxide-semiconductor, V and goes up mutually the grid that brachium pontis metal-oxide-semiconductor and W go up brachium pontis metal-oxide-semiconductor mutually and be all connected with upper brachium pontis drive circuit with drain electrode, and U descends brachium pontis metal-oxide-semiconductor, V to descend mutually brachium pontis metal-oxide-semiconductor, W to descend mutually the grid of brachium pontis metal-oxide-semiconductor to be all connected with lower brachium pontis drive circuit with draining mutually.Intelligent Power Module of the present invention can reduce the interference to electrical network, and the stability of Intelligent Power Module of the present invention is better.Meanwhile, the present invention also has advantages of simple in structure and easy realization.

Brief description of the drawings

Fig. 1 is the circuit structure diagram of Intelligent Power Module of the present invention;

Fig. 2 is the circuit structure diagram that in Intelligent Power Module of the present invention, U goes up brachium pontis drive circuit mutually;

Fig. 3 is the circuit structure diagram that in Intelligent Power Module of the present invention, U descends brachium pontis drive circuit mutually.

Realization, functional characteristics and the advantage of the object of the invention, in connection with embodiment, are described further with reference to accompanying drawing.

Embodiment

Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.

The present invention proposes a kind of Intelligent Power Module.

With reference to Fig. 1, Fig. 1 is the circuit structure diagram of Intelligent Power Module of the present invention.

Intelligent Power Module 4100 in the present embodiment comprises that HVIC pipe 4400 (HVIC, high voltage integrated circuits), U go up that brachium pontis IGBT pipe 4121, V go up that brachium pontis IGBT pipe 4122, W go up that brachium pontis IGBT pipe 4123, U descend that brachium pontis IGBT manages 4124 mutually mutually mutually mutually, V descends that brachium pontis IGBT manages 4125 mutually, W descends that brachium pontis IGBT manages 4126 mutually, electric capacity 4133, electric capacity 4132, electric capacity 4131, U are gone up mutually brachium pontis metal-oxide-semiconductor 4111, V and gone up mutually brachium pontis metal-oxide-semiconductor 4112, W and go up mutually brachium pontis metal-oxide-semiconductor 4113, U and descend mutually brachium pontis metal-oxide-semiconductor 4114, V to descend mutually brachium pontis metal-oxide-semiconductor 4115, W to descend mutually brachium pontis metal-oxide-semiconductor 4116.Corresponding U go up mutually brachium pontis IGBT pipe 4121, V and go up mutually that brachium pontis IGBT manages 4122, W goes up mutually brachium pontis IGBT and manages 4123, be provided with U goes up mutually brachium pontis drive circuit 14, V and goes up mutually brachium pontis drive circuit 24, W and go up mutually brachium pontis drive circuit 34 in the inside of above-mentioned HVIC pipe 4400, corresponding U descends brachium pontis IGBT pipe 4124, V to descend mutually brachium pontis IGBT pipe 4125, W to descend mutually brachium pontis IGBT pipe 4126 mutually, is provided with U descends mutually brachium pontis drive circuit 44, V to descend mutually brachium pontis drive circuit 54 to descend mutually brachium pontis drive circuit 64 with W in the inside of above-mentioned HVIC pipe 4400.The power positive end VCC of HVIC pipe 4400 is connected with the operating voltage input VDD (being also the low-pressure area power supply anode of Intelligent Power Module 4100 of the present invention) of Intelligent Power Module of the present invention.VDD is generally 15V;

The upper brachium pontis control signal input that first input end HIN1 (being the control signal input that U goes up brachium pontis drive circuit 14 mutually), the second input HIN2 (being the control signal input that V goes up brachium pontis drive circuit 24 mutually) of HVIC pipe 4400 and the 3rd input HIN3 (being the control signal input that W goes up brachium pontis drive circuit 34 mutually) are Intelligent Power Module 4100 of the present invention.

Wherein the first input end HIN1 (being the control signal input that U goes up brachium pontis drive circuit 14 mutually) of HVIC pipe 4400 goes up brachium pontis input UHIN mutually as the U of Intelligent Power Module 4100 of the present invention;

The second input HIN2 (being the control signal input that V goes up brachium pontis drive circuit 24 mutually) of HVIC pipe 4400 goes up brachium pontis input VHIN mutually as the V of Intelligent Power Module 4100 of the present invention;

The 3rd input HIN3 (being the control signal input that W goes up brachium pontis drive circuit 34 mutually) of HVIC pipe 4400 goes up brachium pontis input WHIN mutually as the W of Intelligent Power Module 4100 of the present invention;

The lower brachium pontis control signal input that four-input terminal LIN1 (being the control signal input that U descends brachium pontis drive circuit 44 mutually), the 5th input LIN2 (being the control signal input that V descends brachium pontis drive circuit 54 mutually) of HVIC pipe 4400 and the 6th input LIN3 (being the control signal input that W descends brachium pontis drive circuit 64 mutually) are Intelligent Power Module 4100 of the present invention.

Wherein, the four-input terminal LIN1 (being the control signal input that U descends brachium pontis drive circuit 44 mutually) of HVIC pipe 4400 descends brachium pontis input ULIN mutually as the U of Intelligent Power Module 4100 of the present invention;

The 5th input LIN2 (being the control signal input that V descends brachium pontis drive circuit 54 mutually) of HVIC pipe 4400 descends brachium pontis input VLIN mutually as the V of Intelligent Power Module 4100 of the present invention;

The 6th input LIN3 (being the control signal input that W descends brachium pontis drive circuit 64 mutually) of HVIC pipe 4400 descends brachium pontis input WLIN mutually as the W of Intelligent Power Module 4100 of the present invention;

The power supply negative terminal GND of HVIC pipe 4400 is as the low-pressure area power supply negative terminal COM of described Intelligent Power Module 4100 of the present invention;

The U phase higher-pressure region power supply anode VB1 of HVIC pipe 4400 is connected with the first end of electric capacity 4133, and as the U phase higher-pressure region power supply anode UVB of Intelligent Power Module 4100 of the present invention;

The U phase higher-pressure region power supply negative terminal VS1 of HVIC pipe 4400 is connected with the second end of described electric capacity 4133, and as the U phase higher-pressure region power supply negative terminal UVS of Intelligent Power Module 4100 of the present invention;

The V phase higher-pressure region power supply anode VB2 of HVIC pipe 4400 is connected with the first end of electric capacity 4132, and as the V phase higher-pressure region power supply anode VVB of Intelligent Power Module 4100 of the present invention;

The V phase higher-pressure region power supply negative terminal VS2 of HVIC pipe 4400 is connected with the second end of described electric capacity 4132, and as the V phase higher-pressure region power supply negative terminal VVS of Intelligent Power Module 4100 of the present invention;

The W phase higher-pressure region power supply anode VB3 of HVIC pipe 4400 is connected with the first end of electric capacity 4131, and as the W phase higher-pressure region power supply anode WVB of Intelligent Power Module 4100 of the present invention;

The W phase higher-pressure region power supply negative terminal VS3 of HVIC pipe 4400 is connected with the second end of electric capacity 4131, and as the W phase higher-pressure region power supply negative terminal WVS of Intelligent Power Module 4100 of the present invention;

The emitter that U goes up brachium pontis IGBT pipe 4121 mutually descends the collector electrode of brachium pontis IGBT pipe 4124 to be connected with U mutually, and is connected with U phase higher-pressure region power supply negative terminal UVS; The emitter that V goes up brachium pontis IGBT pipe 4122 mutually descends the collector electrode of brachium pontis IGBT pipe 4125 to be connected with V mutually, and is connected with V phase higher-pressure region power supply negative terminal VVS; The emitter that W goes up brachium pontis IGBT pipe 4123 mutually descends the collector electrode of brachium pontis IGBT pipe 4126 to be connected with W mutually, and is connected with W phase higher-pressure region power supply negative terminal WVS; U goes up mutually brachium pontis IGBT pipe 4121, V and go up mutually brachium pontis IGBT pipe 4122 and W and goes up mutually brachium pontis IGBT and manage 4123 collector electrode and be all connected with ceiling voltage end P; U descends brachium pontis IGBT pipe 4124, V to descend mutually brachium pontis IGBT pipe 4125 and W to descend mutually the equal ground connection of emitter of brachium pontis IGBT pipe 4126 mutually;

The UHO end (being the gate signal output that U goes up brachium pontis drive circuit 14 mutually) of HVIC pipe 4400 is connected with the grid that U goes up brachium pontis IGBT pipe 4121 mutually, U goes up the collector electrode and the ceiling voltage end P end that connects Intelligent Power Module 4100 of the present invention of brachium pontis IGBT pipe 4121 mutually, and U goes up mutually the emitter of brachium pontis IGBT pipe 4121 and the UVS end of Intelligent Power Module 4100 of the present invention is connected (UVS end is also the U phase high voltage region power supply negative terminal of Intelligent Power Module of the present invention); The UHD end (being the drain signal output that U goes up brachium pontis drive circuit 14 mutually) of HVIC pipe 4400 is connected with the drain electrode that U goes up brachium pontis metal-oxide-semiconductor 4111 mutually; The UHG end (being the signal output that U goes up brachium pontis drive circuit 14 mutually) of HVIC pipe 4400 is connected with the grid that U goes up brachium pontis metal-oxide-semiconductor 4111 mutually; The source electrode that U goes up brachium pontis metal-oxide-semiconductor 4111 is mutually connected with the emitter that U goes up brachium pontis IGBT pipe 4121 mutually;

The VHO end (being the gate signal output that V goes up brachium pontis drive circuit 24 mutually) of HVIC pipe 4400 is connected with the grid that V goes up brachium pontis IGBT pipe 4122 mutually, the collector electrode that V goes up brachium pontis IGBT pipe 4122 mutually connects the ceiling voltage end P end of Intelligent Power Module 4100 of the present invention, and V go up mutually the emitter of brachium pontis IGBT pipe 4122 and the VVS of Intelligent Power Module 4100 of the present invention and holds and be connected (it is also the V phase high voltage region power supply negative terminal of Intelligent Power Module of the present invention that VVS holds); The VHD end (being the drain signal output that V goes up brachium pontis drive circuit 24 mutually) of HVIC pipe 4400 is connected with the drain electrode that V goes up brachium pontis metal-oxide-semiconductor 4112 mutually; The VHG end (being the signal output that V goes up brachium pontis drive circuit 24 mutually) of HVIC pipe 4400 is connected with the grid that V goes up brachium pontis metal-oxide-semiconductor 4112 mutually; The source electrode that V goes up brachium pontis metal-oxide-semiconductor 4112 is mutually connected with the emitter that V goes up brachium pontis IGBT pipe 4122 mutually;

The WHO end (being the gate signal output that W goes up brachium pontis drive circuit 34 mutually) of HVIC pipe 4400 is connected with the grid that W goes up brachium pontis IGBT pipe 4123 mutually, the collector electrode that W goes up brachium pontis IGBT pipe 4123 mutually connects the ceiling voltage end P end of Intelligent Power Module 4100 of the present invention, and W go up mutually the emitter of brachium pontis IGBT pipe 4123 and the WVS of Intelligent Power Module 4100 of the present invention and holds and be connected (it is also the W phase high voltage region power supply negative terminal of Intelligent Power Module of the present invention that WVS holds); The WHD end (being the drain signal output that W goes up brachium pontis drive circuit 34 mutually) of HVIC pipe 4400 is connected with the drain electrode that W goes up brachium pontis metal-oxide-semiconductor 4113 mutually; The WHG end (being the signal output that W goes up brachium pontis drive circuit 34 mutually) of HVIC pipe 4400 is connected with the grid that W goes up brachium pontis metal-oxide-semiconductor 4113 mutually; The source electrode that W goes up brachium pontis metal-oxide-semiconductor 4113 is mutually connected with the emitter that W goes up brachium pontis IGBT pipe 4123 mutually;

The ULO end (being the gate signal output that U descends brachium pontis drive circuit 44 mutually) of HVIC pipe 4400 descends the grid of brachium pontis IGBT pipe 4124 to be connected with U mutually, U descends the collector electrode of brachium pontis IGBT pipe 4124 to connect the UVS end of Intelligent Power Module 4100 mutually, and U descends the emitter of brachium pontis IGBT pipe 4124 to connect the COM end (being also the low-pressure area power supply negative terminal of Intelligent Power Module of the present invention) of Intelligent Power Module 4100 mutually; The ULD end (being the drain signal output that U descends brachium pontis drive circuit 44 mutually) of HVIC pipe 4400 descends the drain electrode of brachium pontis metal-oxide-semiconductor 4114 to be connected with U mutually; The ULG end (being the signal output that U descends brachium pontis drive circuit 44 mutually) of HVIC pipe 4400 descends the grid of brachium pontis metal-oxide-semiconductor 4114 to be connected with U mutually; U descends the source electrode of brachium pontis metal-oxide-semiconductor 4114 to descend mutually the emitter of brachium pontis IGBT pipe 4124 to be connected with U mutually;

The VLO end (being the gate signal output that V descends brachium pontis drive circuit 44 mutually) of HVIC pipe 4400 descends the grid of brachium pontis IGBT pipe 4125 to be connected with V mutually, V descends the collector electrode of brachium pontis IGBT pipe 4125 to connect the VVS end of Intelligent Power Module 4100 mutually, and V descends the emitter of brachium pontis IGBT pipe 4125 to connect the COM end of Intelligent Power Module 4100 mutually; The VLD end (being the drain signal output that V descends brachium pontis drive circuit 54 mutually) of HVIC pipe 4400 descends the drain electrode of brachium pontis metal-oxide-semiconductor 4115 to be connected with V mutually; The VLG end (being the signal output that V descends brachium pontis drive circuit 54 mutually) of HVIC pipe 4400 descends the grid of brachium pontis metal-oxide-semiconductor 4115 to be connected with V mutually; V descends the source electrode of brachium pontis metal-oxide-semiconductor 4115 to descend mutually the emitter of brachium pontis IGBT pipe 4125 to be connected with V mutually;

The WLO end (being the gate signal output that W descends brachium pontis drive circuit 44 mutually) of HVIC pipe 4400 descends the grid of brachium pontis IGBT pipe 4126 to be connected with W mutually, W descends the collector electrode of brachium pontis IGBT pipe 4126 to connect the WVS end of Intelligent Power Module 4100 mutually, and W descends the emitter of brachium pontis IGBT pipe 4126 to connect the COM end of Intelligent Power Module 4100 mutually; The WLD end (being the drain signal output that W descends brachium pontis drive circuit 64 mutually) of HVIC pipe 4400 descends the drain electrode of brachium pontis metal-oxide-semiconductor 4116 to be connected with W mutually; The WLG end (being the signal output that W descends brachium pontis drive circuit 64 mutually) of HVIC pipe 4400 descends the grid of brachium pontis metal-oxide-semiconductor 4116 to be connected with W mutually; W descends the source electrode of brachium pontis metal-oxide-semiconductor 4116 to descend mutually the emitter of brachium pontis IGBT pipe 4126 to be connected with W mutually;

Manage 4400 inside at HVIC, VCC end is connected with the low-pressure area power supply anode of the each drive circuit of upper and lower brachium pontis; GND end is connected with the low-pressure area power supply negative terminal of the each drive circuit of upper and lower brachium pontis;

The higher-pressure region power supply anode that U goes up brachium pontis drive circuit 14 is mutually connected with VB1 end, and the higher-pressure region power supply negative terminal that U goes up brachium pontis drive circuit 14 is mutually connected with VS1;

The higher-pressure region power supply anode that V goes up brachium pontis drive circuit 24 is mutually connected with VB2, and the higher-pressure region power supply negative terminal that V goes up brachium pontis drive circuit 24 is mutually connected with VS2;

The higher-pressure region power supply anode that W goes up brachium pontis drive circuit 34 is mutually connected with VB3, and the higher-pressure region power supply negative terminal that W goes up brachium pontis drive circuit 34 is mutually connected with VS3.

Fig. 2 is the circuit structure diagram that in Intelligent Power Module of the present invention, U goes up brachium pontis drive circuit mutually.

See figures.1.and.2 in the lump, the U in Intelligent Power Module of the present invention go up mutually brachium pontis drive circuit 14 comprise brachium pontis control signal input (being that above-mentioned U goes up brachium pontis input UHIN mutually), ceiling voltage input P1, U phase higher-pressure region power supply anode VB1, U phase higher-pressure region power supply negative terminal VS1, gate signal output UHO (being the UHO end of above-mentioned HVIC pipe 4400), drain signal output UHD (being the UHD end of above-mentioned HVIC pipe 4400), signal output UHG (being the UHG end of above-mentioned HVIC pipe 4400),

Dipulse circuit for generating 1401, the first high pressure DMOS pipe 1402, the second high pressure DMOS pipe 1403, bootstrap diode 1444, the first resistance 1404, the second resistance 1405, the 3rd resistance 1455, the 4th resistance 1456, the 5th resistance 1457, the 6th resistance 1458, the first diode 1406, the second diode 1407, the first electric capacity 1412, the second electric capacity 1418, the first non-gate cell 100, the second non-gate cell 200, the 3rd non-gate cell 300, the first Schmidt trigger 1411, second this schmitt trigger 1417, rest-set flip-flop 400, the first not gate 1413, the second not gate 1419, the 3rd not gate 1459, the 4th not gate 1460, the first optocoupler 1451, the second optocoupler 1452, the 3rd optocoupler 1453 and the 4th optocoupler 1454.

Particularly, the input of dipulse circuit for generating 1401 is connected with upper brachium pontis control signal input UHIN, the first output of dipulse circuit for generating 1401 is connected with the grid of the first high pressure DMOS pipe 1402, the second output of dipulse circuit for generating 1401 is connected with the grid of the second high pressure DMOS pipe 1403, the power end of dipulse circuit for generating 1401 is connected the ground end ground connection of dipulse circuit for generating 1401 with the power positive end VCC (being also the operating voltage input VDD of Intelligent Power Module of the present invention) of above-mentioned HVIC pipe 4400; The substrate of the first high pressure DMOS pipe 1402 is connected with source electrode and ground connection, and the drain electrode of the first high pressure DMOS pipe 1402 is connected with U phase higher-pressure region power supply anode VB1 through the first resistance 1404; The substrate of the second high pressure DMOS pipe 1403 is connected with source and ground connection, and the drain electrode of the second high pressure DMOS pipe 1403 is connected with U phase higher-pressure region power supply anode VB1 through the second resistance 1405; The anode of bootstrap diode 1444 is connected with the power positive end VCC (being also the operating voltage input VDD of Intelligent Power Module of the present invention) of above-mentioned HVIC pipe 4400, and the negative electrode of bootstrap diode 1444 is connected with U phase higher-pressure region power supply anode VB1; The input of the first non-gate cell 100 is connected with the drain electrode of the first high pressure DMOS pipe 1402, and is connected with the negative electrode of the first diode 1406, and the output of the first non-gate cell 100 is connected with the input of the first not gate 1413 through the first Schmidt trigger 1411; The output of the first not gate 1413 is connected with the S end of rest-set flip-flop 400; The anode of the first diode 1406 is connected with the output of the first non-gate cell 100 through the first electric capacity 1412; The input of the second non-gate cell 200 is connected with the drain electrode of the second high pressure DMOS pipe 1403, and is connected with the negative electrode of the second diode 1407, and the output of the second non-gate cell 200 is connected with the input of the second not gate 1419 through the second Schmidt trigger 1417; The output of the second not gate 1419 is connected with the R end of rest-set flip-flop 400; The anode of the second diode 1407 is connected with the output of the second non-gate cell 200 through the second electric capacity 1418; The anode of the anode of the first diode 1406 and the second diode 1407 is also connected with U phase higher-pressure region power supply negative terminal VS1; The output of rest-set flip-flop 400 is connected with the gate signal output UHO that U goes up brachium pontis drive circuit mutually through the 3rd non-gate cell 300; The first end of the 3rd resistance 1455 is connected with the input of dipulse circuit for generating 1401, the anodic bonding of the second end of the 3rd resistance 1455 and the light-emitting diode of the first optocoupler 1451; The input of the 4th not gate 1460 is connected with the first end of the 3rd resistance 1455, and the output of the 4th not gate 1460 is through the anodic bonding of the light-emitting diode of the 4th resistance 1456 and the second optocoupler 1452; The input of the 3rd not gate 1459 is connected with the first end of the 3rd resistance 1455, and the output of the 3rd not gate 1459 is through the anodic bonding of the light-emitting diode of the 5th resistance 1457 and the 3rd optocoupler 1453; The first end of the 6th resistance 1458 is connected with the first end of the 3rd resistance 1455, the anodic bonding of the second end of the 6th resistance 1458 and the light-emitting diode of the 4th optocoupler 1454; The equal ground connection of negative electrode of the negative electrode of the negative electrode of the negative electrode of the light-emitting diode of the first optocoupler 1451, the light-emitting diode of the second optocoupler 1452, the light-emitting diode of the 3rd optocoupler 1453 and the light-emitting diode of the 4th optocoupler 1454; The collector electrode of the triode of the collector electrode of the triode of the first optocoupler 1451 and the 3rd optocoupler 1453 is all connected with U phase higher-pressure region power supply negative terminal VS1; The collector electrode of the triode of the collector electrode of the triode of the second optocoupler 1452 and the 4th optocoupler 1454 is all connected (being also connected with the ceiling voltage end P of Intelligent Power Module of the present invention) with ceiling voltage input P1; The drain signal output (being the UHD end of above-mentioned HVIC pipe 4400) that the emitter of the triode of the emitter of the triode of the first optocoupler 1451 and the second optocoupler 1452 is all gone up brachium pontis drive circuit 14 mutually with U is connected; The signal output (being the UHG end of above-mentioned HVIC pipe 4400) that the emitter of the triode of the emitter of the triode of the 3rd optocoupler 1453 and the 4th optocoupler 1454 is all gone up brachium pontis drive circuit mutually with U is connected.

Above-mentioned the first non-gate cell 100 comprises not gate 1408, not gate 1409 and the not gate 1410 of series connection successively, above-mentioned the second non-gate cell 200 comprises not gate 1414, not gate 1415 and the not gate 1416 of series connection successively, and above-mentioned the 3rd non-gate cell comprises not gate 1433 and the not gate 1434 of series connection successively.

In the present embodiment, descend mutually the rising edge of brachium pontis control signal input LIN1 institute input control signal at U, the first output of dipulse circuit for generating 1401 produces the pulse signal of a 300ns, descend mutually the trailing edge of brachium pontis control signal input LIN1 institute input control signal at U, the second output of dipulse circuit for generating 1401 produces the pulse signal of a 300ns.In the present embodiment, the first high pressure DMOS pipe 1402 and the second high pressure DMOS pipe 1403 can bear the voltage of 600V in the time turn-offing, and the first high pressure DMOS pipe 1402 and the second high pressure DMOS pipe 1403 can flow through the electric current of ampere level in the time of conducting in 300ns.The first high pressure DMOS pipe 1402 is by the high level pulse conducting of 300ns, the input that makes not gate 1408 reduced from high level moment, and due to the clamping action of the first diode 1406, the level of not gate 1408 is controlled in the current potential that is not less than VS1-0.7V, through not gate 1409, the filter circuit that not gate 1410 and the first electric capacity 1412 form, and after the sluggishness of the first Schmidt trigger 1411, and by after the waveform adjustment of the first not gate 1413, one of them input (being also the S end of rest-set flip-flop 400) of NOR gate 1430 in rest-set flip-flop 400 produces the high level pulse of 300ns.The second high pressure DMOS pipe 1403 is by the high level pulse conducting of 300ns, the input that makes not gate 1414 reduced from high level moment, due to the clamping action of the second diode 1407, the level of not gate 1414 is controlled in the current potential that is not less than VS1-0.7V, through not gate 1415, the filter circuit that not gate 1416 and the second electric capacity 1418 form, after the sluggishness of the second Schmidt trigger 1417, and by after the waveform adjustment of the second not gate 1419, one of them input (being also the R end of rest-set flip-flop 400) of NOR gate 1431 in rest-set flip-flop 400 produces the high level pulse of 300ns.

The present embodiment, when the S of rest-set flip-flop 400 end is put at ordinary times for high, the output (being also the output Q of rest-set flip-flop 400) of NOR gate 1431 becomes high level, and after disappearing, the high level of the S of rest-set flip-flop 400 end keep high level constant, when the R of rest-set flip-flop 400 end is put at ordinary times for high, the output (being also the output Q of rest-set flip-flop 400) of NOR gate 1431 becomes low level, and keeps low level constant after the high level of the R of rest-set flip-flop 400 end disappears.Signal is after the two-stage of the 9th not gate 1433 and the tenth not gate 1434 is amplified, in gate signal output UHO output.

In the time that signal HIN1 is high level, U goes up 4121 conductings under the driving of UHO signal of brachium pontis IGBT pipe mutually; And, the first optocoupler 1451 and the 4th optocoupler 1454 are open-minded, UHD end is connected with VS1 end, UHG end is connected with P1, thereby the grid that makes U go up mutually brachium pontis metal-oxide-semiconductor 4111 is connected with P1 end, and the drain electrode that makes U go up mutually brachium pontis metal-oxide-semiconductor 4111 is connected with substrate, source electrode, is equivalent to provide an electric capacity, the rising, the trailing edge that make U go up mutually the conducting waveform of brachium pontis IGBT pipe 4121 slow down, the impact on electrical network while having reduced its conducting;

In the time that signal HIN1 is low level, U goes up mutually brachium pontis IGBT pipe 4121 and ends under the driving of UHO signal; And, the second optocoupler 1452 and the 3rd optocoupler 1453 are open-minded, UHD end is connected with P1, UHG end is connected with VS1 end, thereby the drain electrode that makes U go up mutually brachium pontis metal-oxide-semiconductor 4111 is connected with P1 end, the grid that makes U go up mutually brachium pontis metal-oxide-semiconductor 4111 is connected with substrate, source electrode, is equivalent to provide an anti-paralleled diode structure, and discharge loop is provided while going up mutually 4121 shutoff of brachium pontis IGBT pipe for U.

The rest-set flip-flop 400 that the first high pressure DMOS pipe 1402 and the second high pressure DMOS pipe 1403 signals that transmit consist of NOR gate 1430 and NOR gate 1431 is merged.

The filter circuit that not gate 1410 and the first electric capacity 1412, not gate 1416 and the second electric capacity 1418 form is in order to filter burst pulse voltage noise, avoid R point and S point to produce false triggering voltage signal, the PMOS pipe of not gate 1410, not gate 1416 and the spaciousness ratio of NMOS can be designed to respectively 10 μ m/5 μ m and 5 μ m/5 μ m, and the first electric capacity 1412, the second electric capacity 1418 can be designed to 5pF.

The effect of the first Schmidt circuit 1411, the second Schmidt circuit 1417 is in order to filter long-term low-voltage noise, avoids noise to cause that through less non-being exaggerated behind the door of threshold value S point and R point produce false triggering voltage signal.

Bootstrap diode 1444, in the time that VS1 voltage approaches GND voltage, is charged to VB1 by VCC, and when VS1 voltage transitions becomes after 600V high pressure, bootstrap diode 1444 bears the reverse pressure drop of 600V.

Between the collector and emitter of the triode of the first optocoupler 1451, the second optocoupler 1452, the 3rd optocoupler 1453, the 4th optocoupler 1454, all need to bear the high pressure of 600V.

Not gate 1433 NAND gate 1434 form two-stage output, go up mutually the driving force of brachium pontis drive circuit 14 according to U, forming the PMOS pipe of not gate 1433 and not gate 1434 and the size of NMOS pipe can design greatlyr, in general, form the PMOS pipe of not gate 1433 and the size of NMOS pipe and be taken as 100 μ m/60 μ m, form the PMOS pipe of not gate 1434 and the size of NMOS pipe and be taken as 250 μ m/130 μ m.

In the lump with reference to Fig. 1 and Fig. 3, U in Intelligent Power Module of the present invention descends brachium pontis drive circuit 44 to comprise lower brachium pontis control signal input LIN1 (being the four-input terminal LIN1 of above-mentioned HVIC pipe 4400) mutually, gate signal output ULO (being the ULO end of above-mentioned HVIC pipe 4400), drain signal output ULD (being the ULD end of above-mentioned HVIC pipe 4400), signal output ULG (being the ULG end of above-mentioned HVIC pipe 4400), level shifting circuit 4401, the 7th resistance 4455, the 8th resistance 4456, the 9th resistance 4457, the tenth resistance 4458, the 3rd electric capacity 4412, the 4th electric capacity 4413, the 5th not gate 4408, the 6th not gate 4409, the 7th not gate 4410, the 8th not gate 4411, the 9th not gate 4433, the tenth not gate 4434, the 11 not gate 4460, the 12 not gate 4459, the 5th optocoupler 4451, the 6th optocoupler 4452, the 7th optocoupler 4453 and the 8th optocoupler 4454.

Particularly, the input of level shifting circuit 4401 is connected with lower brachium pontis control signal input LIN1, five not gate 4408 of the output of level shifting circuit 4401 through mutually connecting, the 6th not gate 4409, the 7th not gate 4410, the 8th not gate 4411, the 9th not gate 4433 and the tenth not gate 4434 descend the gate signal output ULO of brachium pontis drive circuit 44 to be connected with U mutually, the power end of level shifting circuit 4401 is connected with the power positive end VCC (being also the operating voltage input VDD of Intelligent Power Module of the present invention) of above-mentioned HVIC pipe 4400, the ground end ground connection of level shifting circuit 4401, the first end of the 3rd electric capacity 4412 is connected between the 7th not gate 4410 and the 8th not gate 4411, the second end ground connection of the 3rd electric capacity 4412, the first end of the 4th electric capacity 4413 is connected between the 8th not gate 4411 and the 9th not gate 4433, the second end ground connection of the 4th electric capacity 4413,

The first end of the 7th resistance 4455 is connected with the input of level shifting circuit 4401, the anodic bonding of the second end of the 7th resistance 4455 and the light-emitting diode of the 5th optocoupler 4451;

The input of the 11 not gate 4460 is connected with the first end of the 7th resistance 4455, and the output of the 11 not gate 4460 is through the anodic bonding of the light-emitting diode of the 8th resistance 4456 and the 6th optocoupler 4452; The input of the 12 not gate 4459 is connected with the first end of the 7th resistance 4455, and the output of the 12 not gate 4459 is through the anodic bonding of the light-emitting diode of the 9th resistance 4457 and the 7th optocoupler 4453; The first end of the tenth resistance 4458 is connected with the first end of the 7th resistance 4455, the anodic bonding of the second end of the tenth resistance 4458 and the light-emitting diode of the 8th optocoupler 4454; The equal ground connection of negative electrode of the negative electrode of the negative electrode of the negative electrode of the light-emitting diode of the 5th optocoupler 4451, the light-emitting diode of the 6th optocoupler 4452, the light-emitting diode of the 7th optocoupler 4453 and the light-emitting diode of the 8th optocoupler 4454; The equal ground connection of collector electrode of the triode of the collector electrode of the triode of the 5th optocoupler 4451 and the 7th optocoupler 4453; The collector electrode of the triode of the collector electrode of the triode of the 6th optocoupler 4452 and the 8th optocoupler 4454 is all connected with U phase higher-pressure region power supply negative terminal VS1; The emitter of the triode of the emitter of the triode of the 5th optocoupler 4451 and the 6th optocoupler 4452 all descends the drain signal output ULD of brachium pontis drive circuit 44 to be connected with U mutually; The emitter of the triode of the emitter of the triode of the 7th optocoupler 4453 and the 8th optocoupler 4454 all descends the signal output ULG of brachium pontis drive circuit 44 to be connected with U mutually.

In the present embodiment, the effect of level shifting circuit 4401 is to descend mutually the signal of the MOS logic OR TTL logic that brachium pontis control signal input LIN1 inputs to convert the in-phase signal of 0-15V to U, the 7th not gate 4410 and the 3rd electric capacity 4412, the 8th not gate 4411 and the 4th electric capacity 4413 form two groups of delay circuits, object be make signal from lower brachium pontis control signal input LIN1 to figure in E time of ordering and signal from lower brachium pontis control signal input LIN1 to figure in the Q time synchronized of ordering, in the present embodiment, the 7th PMOS of not gate 4410 and the breadth length ratio of NMOS can be set to 20 μ m/10 μ m, the capacitance of the 3rd electric capacity 4412 is 20pF, the 8th PMOS of not gate 4411 and the breadth length ratio of NMOS can be set to 40 μ m/20 μ m, the capacitance of the 4th electric capacity 4413 is 40pF,

The present embodiment, in the time that signal LIN1 is high level, U descends 4124 conductings under the driving of ULO signal of brachium pontis IGBT pipe mutually; And, the 5th optocoupler 4451 and the 8th optocoupler 4454 are open-minded, ULD end is connected with GND, ULG end is connected with VS1 end, thereby make U descend mutually the grid of brachium pontis metal-oxide-semiconductor 4114 to be connected with VS1, make U descend mutually the drain electrode of brachium pontis metal-oxide-semiconductor 4114 to be connected with substrate, source electrode, be equivalent to provide an electric capacity, make U descend mutually rising, the trailing edge of the conducting waveform of brachium pontis IGBT pipe 4124 to slow down, the impact on electrical network while having reduced its conducting;

In the time that signal LIN1 is low level, described U descends brachium pontis IGBT pipe 4124 to end under the driving of ULO signal mutually; And, the 6th optocoupler 4452 and the 7th optocoupler 4453 are open-minded, ULD end is connected with VS1 end, ULG end is connected with GND, thereby make U descend mutually the drain electrode of brachium pontis metal-oxide-semiconductor 4114 to be connected with VS1, make U descend mutually the grid of brachium pontis metal-oxide-semiconductor 4114 to be connected with substrate, source electrode, be equivalent to provide an anti-paralleled diode structure, discharge loop is provided while descending mutually brachium pontis IGBT pipe 4124 to turn-off for U.

In the present embodiment, above-mentioned V goes up circuit structure that brachium pontis drive circuit 24 and above-mentioned W go up brachium pontis drive circuit 34 mutually mutually, and all to go up mutually the circuit structure of brachium pontis drive circuit 14 identical with the U described in embodiment above; Above-mentioned V descends circuit structure that brachium pontis drive circuit 54 and above-mentioned W descend brachium pontis drive circuit 64 mutually all to descend mutually the circuit structure of brachium pontis drive circuit 44 identical with U described in embodiment above mutually, repeats no more herein.

The foregoing is only the preferred embodiments of the present invention; not thereby limit the scope of the claims of the present invention; every equivalent structure or conversion of equivalent flow process that utilizes specification of the present invention and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present invention.

Claims

1. an Intelligent Power Module, it is characterized in that, comprise operating voltage input, ceiling voltage end, U phase higher-pressure region power supply negative terminal, V phase higher-pressure region power supply negative terminal, W phase higher-pressure region power supply negative terminal, U goes up brachium pontis IGBT pipe mutually, V goes up brachium pontis IGBT pipe mutually, W goes up brachium pontis IGBT pipe mutually, U descends brachium pontis IGBT pipe mutually, V descends brachium pontis IGBT pipe mutually, W descends brachium pontis IGBT pipe mutually, U goes up brachium pontis metal-oxide-semiconductor mutually, V goes up brachium pontis metal-oxide-semiconductor mutually, W goes up brachium pontis metal-oxide-semiconductor mutually, U descends brachium pontis metal-oxide-semiconductor mutually, V descends brachium pontis metal-oxide-semiconductor mutually, W descends brachium pontis metal-oxide-semiconductor mutually, and corresponding each described upper brachium pontis IGBT manages the upper brachium pontis drive circuit of setting and the lower brachium pontis drive circuit of corresponding each described lower brachium pontis IGBT pipe setting, wherein,

2. Intelligent Power Module according to claim 1, is characterized in that, described upper brachium pontis drive circuit comprises that U goes up that brachium pontis drive circuit, V go up brachium pontis drive circuit mutually and W goes up brachium pontis drive circuit mutually mutually; Described U goes up mutually brachium pontis drive circuit, V and goes up mutually brachium pontis drive circuit and W and go up mutually brachium pontis drive circuit and include gate signal output, drain signal output and signal output, wherein,

3. Intelligent Power Module according to claim 2, is characterized in that, described lower brachium pontis drive circuit comprises that U descends brachium pontis drive circuit, V to descend mutually brachium pontis drive circuit and W to descend mutually brachium pontis drive circuit mutually; Described U descends brachium pontis drive circuit, V to descend mutually brachium pontis drive circuit and W to descend mutually brachium pontis drive circuit to include gate signal output, drain signal output and signal output mutually, wherein,

4. Intelligent Power Module according to claim 3, it is characterized in that, described U goes up mutually brachium pontis drive circuit and also comprises brachium pontis control signal input, U phase higher-pressure region power supply anode, U phase higher-pressure region power supply negative terminal, dipulse circuit for generating, the first high pressure DMOS pipe, the second high pressure DMOS pipe, bootstrap diode, the first resistance, the second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the first diode, the second diode, the first electric capacity, the second electric capacity, the first non-gate cell, the second non-gate cell, the 3rd non-gate cell, the first Schmidt trigger, second this schmitt trigger, rest-set flip-flop, the first not gate, the second not gate, the 3rd not gate, the 4th not gate, the first optocoupler, the second optocoupler, the 3rd optocoupler and the 4th optocoupler, wherein,

5. Intelligent Power Module according to claim 4, it is characterized in that, described the first non-gate cell comprises three not gates of series connection successively, and described the second non-gate cell comprises three not gates of series connection successively, and described the 3rd non-gate cell comprises two not gates of series connection successively.

6. Intelligent Power Module according to claim 5, it is characterized in that, described U descends brachium pontis drive circuit also to comprise lower brachium pontis control signal input, level shifting circuit, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 3rd electric capacity, the 4th electric capacity, the 5th not gate, the 6th not gate, the 7th not gate, the 8th not gate, the 9th not gate, the tenth not gate, the 11 not gate, the 12 not gate, the 5th optocoupler, the 6th optocoupler, the 7th optocoupler and the 8th optocoupler mutually; Wherein,

7. Intelligent Power Module according to claim 6, is characterized in that, described U goes up mutually brachium pontis metal-oxide-semiconductor, V and goes up mutually brachium pontis metal-oxide-semiconductor, W and go up mutually brachium pontis metal-oxide-semiconductor, U and descend mutually brachium pontis metal-oxide-semiconductor, V to descend mutually brachium pontis metal-oxide-semiconductor and W to descend mutually brachium pontis metal-oxide-semiconductor to be NMOS pipe.

8. Intelligent Power Module according to claim 7, is characterized in that, described V goes up circuit structure that brachium pontis drive circuit and described W go up brachium pontis drive circuit mutually mutually, and all to go up mutually the circuit structure of brachium pontis drive circuit identical with described U.

9. Intelligent Power Module according to claim 8, is characterized in that, described V descends brachium pontis drive circuit and described W to descend mutually the circuit structure of brachium pontis drive circuit all to descend mutually the circuit structure of brachium pontis drive circuit identical with described U mutually.