CN108233690B

CN108233690B - Intelligent power module, air conditioner controller and air conditioner

Info

Publication number: CN108233690B
Application number: CN201810061340.3A
Authority: CN
Inventors: 冯宇翔
Original assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Current assignee: Midea Group Co Ltd; GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2018-01-19
Filing date: 2018-01-19
Publication date: 2020-09-11
Anticipated expiration: 2038-01-19
Also published as: CN108233690A

Abstract

The invention provides an intelligent power module, an air conditioner controller and an air conditioner, wherein a detection circuit, an upper bridge over-current control circuit and a lower bridge over-current control circuit are added in the intelligent power module, and a sampling resistor is changed into a built-in structure, so that when the intelligent power module drives a load to generate over-current, a voltage signal on the sampling resistor can be subjected to delay feedback during over-current, so that the filtering of voltage noise is realized, the accuracy of over-current detection is improved, and when the over-current occurs, three-phase upper bridge arm IGBT tubes are respectively controlled to be all cut off by the upper bridge over-current control circuit and the lower bridge over-current control circuit, and the three-phase lower bridge arm IGBT tubes are respectively and intermittently conducted, so that induced charges generated by the load driven by the IPM module during over-current can be effectively and safely discharged, the impact of residual charges on the IGBT tubes is avoided, and.

Description

Intelligent power module, air conditioner controller and air conditioner

Technical Field

The invention relates to the technical field of intelligent power modules, in particular to an intelligent power module, an air conditioner controller and an air conditioner.

Background

An Intelligent Power Module, i.e., an IPM (Intelligent Power Module), is a Power driving product combining Power electronics and integrated circuit technology. The intelligent power module integrates a power switch device and a high-voltage driving circuit, and is internally provided with fault detection circuits such as overvoltage, overcurrent and overheat. The intelligent power module receives a control signal of the MCU to drive a subsequent circuit to work on one hand, and sends a state detection signal of the system back to the MCU on the other hand. The intelligent power module is especially suitable for frequency converter of driving motor and various inverter power sources, and is an ideal power electronic device for frequency conversion speed regulation, metallurgical machinery, electric traction, servo drive and frequency conversion household appliances.

As shown in fig. 1, a Circuit structure of a conventional IPM module 100 includes HVIC transistors (High voltage integrated Circuit chips) 111, three-phase upper arm IGBT transistors (Insulated gate bipolar transistors) 111, 112, 113, and three-phase lower

arm IGBT transistors

114, 115, 116, where the HVIC transistors 111 include therein a UH driving Circuit 101, a VH driving Circuit 102, and a WH driving Circuit 103 connected to the three-phase upper arm IGBT transistors, and a UL driving Circuit 104, a VL driving Circuit 105, and a WL driving Circuit 106 connected to the three-phase lower arm IGBT transistors, and the six driving circuits respectively drive six corresponding IGBT transistors to switch states under the control of six control signals input by the IPM module 100. The recommended circuit of the IPM module 100 during actual operation is shown in fig. 2, the IPM module 100 is connected to the MCU200 through six input control signals, the U, V, W three-phase output end of the IPM module 100 is connected to the three-phase winding of the motor 139, the

capacitors

135, 136, 137 are bootstrap capacitors respectively connecting the three-phase output terminal and the positive end of the corresponding phase high-voltage power supply, the six control signals output by the MCU200 control the switching states of the six IGBT tubes of the IPM module 100 to switch, and output the corresponding three-phase driving signals to the motor 139, thereby driving the motor 139 to operate. Further, UN, VN, WN are connected to one end of a parallel resistor 138, the resistor 138 is used to detect the output current value of the IPM module 100 driving motor 139 and input the output current value to Pin7 Pin of the MCU, in practical applications, especially in variable frequency air conditioning applications, according to environmental changes, the MCU detects the voltage change of the resistor 138 to control the working state of the intelligent power module 100, when the voltage value of the resistor 138 is greater than a certain specific value, that is, when the current flowing through the intelligent power module 100 is greater than a certain specific value, it is proved that the intelligent power module 100 has a risk of abnormal heating due to overload operation, and the PINs 1-Pin 6 ends of the MCU tube 200 simultaneously output low levels to control the intelligent power module 100 to stop operating. Through the above mechanism, as long as the specific voltage value is set to be small enough, the smart power module 100 can be ensured not to be damaged, but the disadvantages caused by the method are also obvious:

firstly, the intelligent power module has a severe working environment and very high voltage noise, and is very easy to generate false triggering, so that the intelligent power module is shut down without overcurrent of actual current;

secondly, when a real overcurrent occurs, because the load of the intelligent power module 100 is an inductive element, the overcurrent inevitably generates residual charges, the sudden stop of the intelligent power module 100 causes the residual charges not to have a discharge loop and to be accumulated, and after the intelligent power module 100 is powered on again, the residual charges at the load end impact the IGBT tube, so that the IGBT tube may be slightly damaged, and in a serious case, the intelligent power module 100 may be burnt, so that a system is paralyzed, and even a fire hazard and other safety accidents are caused.

Disclosure of Invention

The invention mainly aims to provide an intelligent power module, an air conditioner controller and an air conditioner, and aims to solve the problems that overcurrent detection of the intelligent power module is easy to trigger by mistake due to interference in the working process, and induced charges generated by a load impact the intelligent power module to influence the working reliability of the intelligent power module.

In order to achieve the purpose, the intelligent power module provided by the invention comprises a three-phase upper bridge arm IGBT tube, a three-phase lower bridge arm IGBT tube, a driving circuit corresponding to each IGBT tube in the three-phase upper bridge arm IGBT tube and the three-phase lower bridge arm IGBT tube, and a bridge arm control signal input end, and is characterized by further comprising an overcurrent detection circuit, an upper bridge overcurrent control circuit and a lower bridge overcurrent control circuit;

the first output end of the over-current detection circuit is connected with the control end of the upper bridge over-current control circuit, the second output end of the over-current detection circuit is connected with the control end of the lower bridge over-current control circuit, three output ends of the upper bridge over-current control circuit are respectively connected with the driving circuits corresponding to the three-phase upper bridge arm IGBT tubes, three output ends of the lower bridge over-current control circuit are respectively connected with the driving circuits corresponding to the three-phase lower bridge arm IGBT tubes, and three input ends of the upper bridge over-current control circuit and the lower bridge over-current control circuit are respectively connected with the corresponding bridge arm control signal input ends;

the overcurrent detection circuit is used for detecting the current value of the intelligent power module driving load, when the current value is greater than a preset current threshold value each time, the overcurrent detection circuit outputs a protection signal to the upper bridge overcurrent control circuit and the lower bridge overcurrent control circuit so as to disconnect the bridge arm control signal input end corresponding to the corresponding IGBT tube from the driving circuit and control the three-phase upper bridge arm IGBT tube to be cut off, and when the current value is greater than the preset current threshold value each time, each IGBT tube in the three-phase lower bridge arm IGBT tube is controlled to be intermittently conducted according to a preset frequency respectively so as to discharge the induced charge of the intelligent power module driving load.

In one possible design, the over-current detection circuit includes a comparison module, a delay module, and an output module;

the input end of the comparison module is the input end of the over-current detection circuit, the output end of the comparison module is connected with the input end of the delay module, the output end of the delay module is connected with the output module, and the two output ends of the output module are the output ends of the over-current detection circuit;

the input end of the comparison module is used for detecting an input voltage signal of the intelligent power module driving load current value, comparing the voltage signal with a preset voltage value, outputting an overcurrent signal to the delay module when the voltage signal exceeds the preset voltage value, delaying the overcurrent signal by the delay module and inputting the delayed overcurrent signal to the output module, and performing level conversion by the output module to output two paths of protection signals to the upper bridge overcurrent control circuit and the lower bridge overcurrent control circuit.

In one possible design, the comparison module includes a comparator, a voltage source;

one end of the voltage source is grounded, the other end of the voltage source is connected with the non-inverting input end of the comparison module, and the inverting input end of the comparison module is the input end of the comparison module.

In one possible design, the delay module includes a delay circuit, a first not gate, and a second not gate;

the input end of the first not gate is the input end of the delay module, and the output end of the first not gate is connected with the input end of the delay circuit;

the output end of the delay circuit is connected with the input end of the second not gate, and the output end of the second not gate is the output end of the delay module.

In one possible design, the output module includes a fifth not gate;

the first output end of the output module and the input end of the output module are connected to the input end of the fifth not gate in a shared mode, and the output end of the fifth not gate is the second output end of the output module.

In one possible design, the lower bridge over-current control circuit includes a sixth not gate, a seventh not gate, a gating circuit, a first analog switch, a second analog switch, a third analog switch, a fourth analog switch, a fifth analog switch, a sixth analog switch, a signal generator, a first or gate, a second or gate, and a third or gate;

the input end of the sixth not gate is the control end of the lower bridge over-current control circuit, the output end of the sixth not gate is connected with the input end of the seventh not gate, and the output end of the sixth not gate is simultaneously connected with the clock input end of the gating circuit;

one end of the first analog switch, one end of the second analog switch and one end of the third analog switch form three input ends of the lower bridge over-current control circuit, the other end of the first analog switch is connected with one input end of the first OR gate, the other end of the second analog switch is connected with one input end of the second OR gate, and the other end of the third analog switch is connected with one input end of the third OR gate;

the output end of the seventh not gate is simultaneously connected with the first analog switch, the second analog switch, the control end of the third analog switch and the enabling end of the gating circuit respectively, and three output ends of the gating circuit are connected with the control ends of the fourth analog switch, the fifth analog switch and the sixth analog switch respectively;

one end of the fourth analog switch is connected with the other input end of the first OR gate, one end of the fifth analog switch is connected with the other input end of the second OR gate, one end of the sixth analog switch is connected with the other input end of the third OR gate, and the other ends of the fourth analog switch, the fifth analog switch and the sixth analog switch are connected with the output end of the signal generator;

and the output ends of the first or gate, the second or gate and the third or gate form three output ends of the lower bridge over-current control circuit.

In one possible design, the gating circuit includes a fourth analog switch, a fifth analog switch, a sixth analog switch, an eighth not gate, a first D flip-flop, a second D flip-flop, and a third D flip-flop;

the clock input ends of the first D trigger, the second D trigger and the third D trigger are the clock input ends of the gating circuit, the output end of the first D trigger is connected with one end of the fourth analog switch, the output end of the second D trigger is connected with one end of the fifth analog switch, the output end of the third D trigger is connected with one end of the sixth analog switch, the output end of the first D trigger is simultaneously connected with the data end of the second D trigger, the output end of the second D trigger is simultaneously connected with the data end of the third D trigger, and the output end of the third D trigger is simultaneously connected with the data end of the first D trigger;

the other ends of the fourth analog switch, the fifth analog switch and the sixth analog switch form three output ends of the gating circuit;

the input end of the eighth not gate is the enabling end of the gating circuit, and the output end of the eighth not gate is respectively connected with the control ends of the fourth analog switch, the fifth analog switch and the sixth analog switch.

In one possible design, the upper bridge over-current control circuit comprises a ninth not gate, a first and gate, a second and gate and a third and gate;

the input end of the ninth not gate is the control end of the upper bridge over-current control circuit, the output end of the ninth not gate is respectively connected with one input end of the first and gate, one input end of the second and gate and one input end of the third and gate, the other input ends of the first and gate, the second and gate and the third and gate form three input ends of the upper bridge over-current control circuit, and the output ends of the first and gate, the second and gate and the third and gate form three output ends of the upper bridge over-current control circuit.

In order to achieve the above object, the present invention further provides an air conditioner controller, wherein the air conditioner comprises the intelligent power module.

In order to achieve the above object, the present invention further provides an air conditioner, which includes the air conditioner controller.

According to the intelligent power module provided by the invention, the detection circuit, the upper bridge over-current control circuit and the lower bridge over-current control circuit are added in the intelligent power module, and the sampling resistor is changed into a built-in structure, so that when the intelligent power module drives a load to generate over-current, a voltage signal on the sampling resistor during over-current can be subjected to delay feedback, and thus the filtering of voltage noise is realized, the accuracy of over-current detection is improved, and the three-phase upper bridge arm IGBT tubes are respectively controlled to be all cut off and the three-phase lower bridge arm tubes are respectively controlled to be intermittently conducted according to the preset frequency by the upper bridge over-current control circuit and the lower bridge over-current control circuit during over-current, so that induced charges generated by the load driven by the IPM module during over-current can be effectively and safely discharged, the impact of residual charges on the IGBT tubes is.

Drawings

FIG. 1 is a circuit block diagram of a prior art smart power module;

FIG. 2 is a circuit diagram of the actual operation of a prior art smart power module;

FIG. 3 is a circuit block diagram of the smart power module of the present invention;

FIG. 4 is a specific circuit structure diagram of the output adjustment circuit shown in FIG. 3;

FIG. 5 is a detailed enlarged view of the circuit of area A in FIG. 4;

FIG. 6 is a detailed circuit diagram of the delay circuit of FIG. 4;

fig. 7 is a specific circuit configuration diagram of the gate circuit in fig. 4.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

Referring to fig. 3, fig. 3 is a schematic structural diagram of an IPM module 4100 according to a first embodiment of the present invention, and for convenience of illustration, only the relevant parts related to the embodiment of the present invention are shown.

In this embodiment, the IPM module 4100 includes a three-phase upper bridge arm IGBT tube and a three-phase lower bridge arm IGBT tube, and a driving circuit and a bridge arm control signal input terminal corresponding to each of the three-phase upper bridge arm IGBT tube and the three-phase lower bridge arm IGBT tube, and the IPM module 4100 further includes an overcurrent detection circuit 4302, an upper bridge overcurrent control circuit 4304, and a lower bridge overcurrent control circuit 4303;

a first output end of the over-current detection circuit 4302 is connected with a control end of the lower bridge over-current control circuit 4303, a second output end of the over-current detection circuit 4302 is connected with a control end of the upper bridge over-current control circuit 4304, three output ends of the upper bridge over-current control circuit 4304 are respectively connected with a driving circuit corresponding to a three-phase upper bridge arm IGBT tube, three output ends of the lower bridge over-current control circuit 4303 are respectively connected with a driving circuit corresponding to a three-phase lower bridge arm IGBT tube, and three input ends of the upper bridge over-current control circuit 4304 and the lower bridge over-current control circuit 4303 are respectively connected with corresponding bridge arm control signal;

the over-current detection circuit 4302 is configured to detect a current value of a load driven by the intelligent power module 4100, where each time the current value is greater than a preset current threshold, the over-current detection circuit 4302 outputs a protection signal to the upper bridge over-current control circuit 4304 and the lower bridge over-current control circuit 4303 to disconnect the bridge arm control signal input end corresponding to the corresponding IGBT tube from the drive circuit and control the three-phase upper bridge arm IGBT tube to be turned off, and each time the current value is greater than the preset current threshold, each of the three-phase lower bridge arm IGBT tubes is controlled to be intermittently turned on according to a preset frequency, so as to discharge an induced charge of the load driven by the intelligent power module 4100.

As shown in fig. 2, the intelligent power module 4100 includes a power driving circuit 4400 and a sampling resistor 4301 for detecting the magnitude of the current value of the driving load of the intelligent power module 4100, where the sampling resistor 4301 is integrated in the intelligent power module 4100, and of course, the sampling resistor 4301 may also be connected to the intelligent power module 4100, where a power supply positive terminal VCC of the power driving circuit 4400 serves as a low-voltage area power supply positive terminal VDD of the intelligent power module 4100, and VDD is generally 15V;

a first input terminal HIN1 of the power driving circuit 4400 serves as a U-phase upper bridge arm input terminal UHIN of the intelligent power module 4100, a second input terminal HIN2 of the power driving circuit 4400 serves as a V-phase upper bridge arm input terminal VHIN of the intelligent power module 4100, a third input terminal HIN3 of the power driving circuit 4400 serves as a W-phase upper bridge arm input terminal WHIN of the intelligent power module 4100, a fourth input terminal LIN1 of the power driving circuit 4400 serves as a U-phase lower bridge arm input terminal ULIN of the intelligent power module 4100, a fifth input terminal 2 of the power driving circuit 4400 serves as a V-phase lower bridge arm input terminal VLIN of the intelligent power module 4100, and a sixth input terminal 3 of the power driving circuit 4400 serves as a W-phase lower bridge arm input terminal WLIN of the intelligent power module 4100.

A seventh output terminal ITRIP of the power driving circuit 4400 is connected to the U-phase low-voltage reference terminal UN of the power driving circuit 4400, the V-phase low-voltage reference terminal VN of the power driving circuit 4400, the W-phase low-voltage reference terminal WN of the power driving circuit 4400, and one end of the sampling resistor 4301, and serves as an abnormal feedback terminal ISO of the intelligent power module 4100.

A power supply negative terminal GND of the power driving circuit 4400 is connected with the other end of the sampling resistor 4301 and serves as a lowest voltage reference point N of the intelligent power module 4100, a U-phase high-voltage area power supply positive terminal VB1 of the power driving circuit 4400 is connected with one end of the capacitor 4133 and serves as a U-phase high-voltage area power supply positive terminal UVB of the intelligent power module 4100, and a U-phase high-voltage area power supply negative terminal VS1 of the power driving circuit 4400 is connected with the other end of the capacitor 4133 and serves as a U-phase high-voltage area power supply negative terminal UVS of the intelligent power module 4100; a positive end VB2 of a V-phase high-voltage region power supply source of the power driving circuit 4400 is connected with one end of the capacitor 4132 and serves as a positive end VVB of the V-phase high-voltage region power supply source of the intelligent power module 4100, and a negative end VS2 of the V-phase high-voltage region power supply source of the power driving circuit 4400 is connected with the other end of the capacitor 4132 and serves as a negative end VVS of the V-phase high-voltage region power supply source of the intelligent power module 4100; a W-phase high-voltage region power supply positive terminal VB3 of the power driving circuit 4400 is connected to one end of the capacitor 4131 and serves as a W-phase high-voltage region power supply positive terminal WVB of the intelligent power module 4100, a W-phase high-voltage region power supply negative terminal VS3 of the power driving circuit 4400 is connected to the other end of the capacitor 4131 and serves as a W-phase high-voltage region power supply negative terminal WVS of the intelligent power module 4100, and a highest voltage reference terminal P of the power driving circuit 4400 serves as a highest voltage reference point P of the intelligent power module 4100.

In the power driving circuit 4400, a voltage signal ITRIP is connected to an input end of the overcurrent detection circuit 4302; a first output end of the over-current detection circuit 4302 is connected to a control end of the lower bridge over-current control circuit 4303, and a second output end of the over-current detection circuit 4302 is connected to a control end of the upper bridge over-current control circuit 4304.

An LIN1 end of the power driving circuit 4400 is connected with a first input end of the lower bridge over-current control circuit 4303, an LIN2 end of the lower bridge over-current control circuit 4303, an LIN3 end of the lower bridge over-current control circuit 4303, an HIN1 end of the power driving circuit is connected with a first input end of the upper bridge over-current control circuit 4304, an HIN2 end of the power driving circuit 4400 is connected with a second input end of the upper bridge over-current control circuit 4304, and an HIN3 end of the power driving circuit 43034.

Specifically, a specific circuit of the over-current detection circuit 4302, the upper bridge over-current control circuit 4304, and the lower bridge over-current control circuit 4303 based on the above scheme is shown in fig. 4, and a further circuit diagram of the amplifying circuit of the above portion can be seen in fig. 5, where the specific circuit is as follows:

the over-current detection circuit 4302 comprises a comparison module 10, a delay module 20 and an output module 30;

the input end of the comparison module 10 is the input end of the over-current detection circuit 4302, the output end of the comparison module 10 is connected with the input end of the delay module 20, the output end of the delay module 20 is connected with the output module 30, and two output ends of the output module 30 are the output ends of the over-current detection circuit 4302;

the input end of the comparison module 10 is used for detecting a voltage signal itrp of an input intelligent power module driving load current value, comparing the voltage signal with a preset voltage value, outputting an overcurrent signal to the delay module 20 when the voltage value exceeds the preset voltage value, delaying the voltage signal by the delay module 20, inputting the delayed overcurrent signal to the output module 30, and performing level conversion by the output module 30 to output two paths of protection signals to the upper bridge overcurrent control circuit 4304 and the lower bridge overcurrent control circuit 4303.

Further, as a specific application circuit of the comparing module 10, the comparing module 10 includes a comparator 4312, a voltage source 4322; one end of the voltage source 4322 is grounded, the other end is connected to the non-inverting input terminal of the comparing module 10, and the directional input terminal of the comparing module 10 is the input terminal of the comparing module 10.

The delay module 20 includes a delay circuit 4342, a first not gate 4332 and a second not gate 4352;

the input end of the first not gate 4332 is the input end of the delay module 20, and the output end of the first not gate 4332 is connected to the input end of the delay circuit 4342;

the output terminal of the delay circuit 4342 is connected to the input terminal of the second not gate 4352, and the output terminal of the second not gate 4352 is the output terminal of the delay module 20.

Further, as a specific application circuit of the delay circuit 4342, as shown in fig. 5, the delay circuit 4342 includes a third not gate 43421, a fourth not gate 43422 and a first capacitor 43423, where the delay circuit mainly charges through the first capacitor 4345 to implement a delay function;

the input terminal of the third not gate 43421 is the input terminal of the delay circuit 4342, the output terminal of the third not gate 43421 and one end of the first capacitor 43422 are commonly connected to the input terminal of the fourth not gate 43422, and the output terminal of the fourth not gate 43422 is the output terminal of the delay circuit 4342.

The output module 30 includes a fifth not gate 4362;

the first output end OUT1 of the output block 30 and the input end of the output block 30 are commonly connected to the input end of the fifth not gate 4362, and the output end of the fifth not gate 4362 is the second output end OUT2 of the output block 30.

Further, as a specific application circuit of the lower bridge overcurrent control circuit 4303, the lower bridge overcurrent control circuit 4303 includes a sixth not gate 4313, a seventh not gate 4353, a gating circuit 4363, a first analog switch 4373, a second analog switch 4383, a third analog switch 4393, a fourth analog switch 43103, a fifth analog switch 43113, a sixth analog switch 43123, a signal generator 43133, a first or gate 4343, a second or gate 4333, and a third or gate 4323;

the input end of the sixth not gate 4313 is the control end of the lower bridge over-current control circuit 4303, the output end of the sixth not gate 4313 is connected to the input end of the seventh not gate 4353, and the output end of the sixth not gate 4313 is simultaneously connected to the signal input end CK of the gating circuit 4363;

one end of the first analog switch 4373, one end of the second analog switch 4383 and one end of the third analog switch 4393 form three input ends of the lower bridge overcurrent control circuit 4303, the other end of the first analog switch 4373 is connected to one input end of the first or gate 4343, the other end of the second analog switch 4383 is connected to one input end of the second or gate 4333, and the other end of the third analog switch 4393 is connected to one input end of the third or gate 4323;

the output end of the seventh not gate 4353 is simultaneously connected to the control ends of the first analog switch 4373, the second analog switch 4383, the third analog switch 4393 and the enable end EN of the gating circuit 4363, respectively, and three output ends of the gating circuit 4363 are connected to the control ends of the fourth analog switch 43103, the fifth analog switch 43113 and the sixth analog switch 43123, respectively;

one end of the fourth analog switch 43103 is connected to the other input end of the first or gate 4343, one end of the fifth analog switch 43113 is connected to the other input end of the second or gate 4333, one end of the sixth analog switch 43123 is connected to the other input end of the third or gate 4323, and the other ends of the fourth analog switch 43103, the fifth analog switch 43113 and the sixth analog switch 43123 are commonly connected to the output end of the signal generator 43133;

the outputs of the first or gate 4343, the second or gate 4333 and the third or gate 4323 constitute three outputs of the lower bridge over-current control circuit 4303.

Optionally, as shown in fig. 7, a specific circuit of the gating circuit 4363 is that the gating circuit 4363 includes a fourth analog switch 43634, a fifth analog switch 43635, a sixth analog switch 43636, an eighth not gate 43637, a first D flip-flop 43631, a second D flip-flop 43632, and a third D flip-flop 43633;

the clock input terminals of the first D flip-flop 43631, the second D flip-flop 43632 and the third D flip-flop 43633 are the clock input terminal CK of the gating circuit 4363, the output terminal of the first D flip-flop 43631 is connected to one terminal of the fourth analog switch 43634, the output terminal of the second D flip-flop 43632 is connected to one terminal of the fifth analog switch 43635, the output terminal of the third D flip-flop 43633 is connected to one terminal of the sixth analog switch 43636, the output terminal of the first D flip-flop 43631 is simultaneously connected to the data terminal of the second D flip-flop 43632, the output terminal of the second D flip-flop 43632 is simultaneously connected to the data terminal of the third D flip-flop 43633, and the output terminal of the third D flip-flop 43633 is simultaneously connected to the data terminal of the first D flip-flop 43631;

the other ends of the fourth analog switch 43634, the fifth analog switch 43635 and the sixth analog switch 43636 form three output ends of a gating circuit 4363;

an input end of the eighth not gate 43637 is an enable end EN of the gating circuit 4363, and an output end of the eighth not gate 43637 is connected to control ends of the fourth analog switch 43634, the fifth analog switch 43635 and the sixth analog switch 43636, respectively.

Further, as a specific application circuit of the upper bridge over-current control circuit 4304, the upper bridge over-current control circuit 4304 includes a seventh not gate 4314, a first and gate 4344, a second and gate 4334, and a third and gate 4324;

the input end of the seventh not gate 4314 is the control end of the upper bridge over-current control circuit 4304, the output end of the upper not gate is respectively connected with one input end of the first and gate 4344, the second and gate 4334 and the third and gate 4324 in common, the other input ends of the first and gate 4344, the second and gate 4334 and the third and gate 4324 constitute three input ends of the upper bridge over-current control circuit 4304, and the output ends of the first and gate 4344, the second and gate 4334 and the third and gate 4324 constitute three output ends of the upper bridge over-current control circuit 4304.

It should be noted that the circuit structure of the delay circuit 4342 is only a specific application circuit, and may be implemented by other application circuits, such as a counter delay circuit.

In the specific circuit shown in fig. 4, the power driving circuit 4400 further includes three-phase upper arm IGBT tubes 4111, 4112, 4113, a UH driving circuit 4101, a VH driving circuit 4102 and a WH driving circuit 4103 respectively connected to the three-phase upper arm IGBT tubes, and the power driving circuit 4400 further includes three-phase lower arm IGBT tubes 4114, 4115, 4116, and a UL driving circuit 4104, a VL driving circuit 4105 and a WL driving circuit 4106 respectively connected to the three-phase lower arm IGBT tubes.

Specifically, a first output terminal of the upper bridge overcurrent control circuit 4304 is connected to an input terminal of the UH driver circuit 4101, a second output terminal of the upper bridge overcurrent control circuit 4304 is connected to an input terminal of the VH driver circuit 4102, a third output terminal of the upper bridge overcurrent control circuit 4304 is connected to an input terminal of the WH driver circuit 4103, a first output terminal of the lower bridge overcurrent control circuit 4303 is connected to an input terminal of the UL driver circuit 4104, a second output terminal of the lower bridge overcurrent control circuit 4303 is connected to an input terminal of the VL driver circuit 4105, and a third output terminal of the lower bridge overcurrent control circuit 4303 is connected to an input terminal of the WL driver circuit 4106.

Here, the U, V, W three-phase six-input of the smart power module 4100 receives input signals of 0V or 5V.

The GND terminal of the power driver circuit 4400 serves as the low-voltage power supply negative terminal COM of the intelligent power module 4100, and is connected to the low-voltage power supply negative terminals of the UH driver circuit 4101, the VH driver circuit 4102, the WH driver circuit 4103, the UL driver circuit 4104, the VL driver circuit 4105, and the WL driver circuit 4106.

The VB1 end of the power driving circuit 4400 is connected to the positive end of the high-voltage power supply of the UH driving circuit 4101 inside the power driving circuit 4400, and is connected to one end of the capacitor 4131 outside the power driving circuit 4400, and is used as the positive end UVB of the U-phase high-voltage power supply of the intelligent power module 4100.

The HO1 terminal of the power driving circuit 4400 is connected to the output terminal of the UH driving circuit 4101 inside the power driving circuit 4400, and is connected to the gate of the U-phase upper arm IGBT tube 4121 outside the power driving circuit 4400.

The VS1 end of the power driving circuit 4400 is connected to the negative end of the high-voltage area power supply of the UH driving circuit 4101 inside the power driving circuit 4400, and is connected to the emitter of the IGBT 4121, the anode of the FRD tube 4111, the collector of the U-phase lower arm IGBT 4124, the cathode of the FRD tube 4114, and the other end of the capacitor 4131 outside the power driving circuit 4400, and serves as the negative end UVS of the U-phase high-voltage area power supply of the intelligent power module 4100.

The VB2 end of the power driving circuit 4400 is connected to the positive end of the high-voltage region power supply of the VH driving circuit 4102 inside the power driving circuit 4400, and one end of the capacitor 4132 is connected to the outside of the power driving circuit 4400 as the positive end VVB of the U-phase high-voltage region power supply of the intelligent power module 4100.

The HO2 terminal of the power driver circuit 4400 is connected to the output terminal of the VH driver circuit 4102 inside the power driver circuit 4400, and is connected to the gate of the V-phase upper arm IGBT tube 4122 outside the power driver circuit 4400.

The VS2 end of the power driving circuit 4400 is connected to the negative end of the high-voltage area power supply of the VH driving circuit 4102 inside the power driving circuit 4400, and is connected to the emitter of the IGBT 4122, the anode of the FRD tube 4112, the collector of the V-phase lower arm IGBT 4125, the cathode of the FRD tube 4115, and the other end of the capacitor 4132 outside the power driving circuit 4400, and is used as the negative end VVS of the V-phase high-voltage area power supply of the intelligent power module 4100.

The VB3 end of the power driving circuit 4400 is connected to the positive end of the high voltage power supply of the WH driving circuit 4103 inside the power driving circuit 4400, and one end of the capacitor 4133 is connected to the outside of the power driving circuit 4400 as the positive end WVB of the W-phase high voltage power supply of the intelligent power module 4100.

The HO3 terminal of the power driving circuit 4400 is connected to the output terminal of the WH driving circuit 4103 inside the power driving circuit 4400, and is connected to the gate of the W-phase upper arm IGBT 4123 outside the power driving circuit 4400.

The VS3 end of the power driving circuit 4400 is connected to the negative end of the high voltage area power supply of the WH driving circuit 4103 inside the power driving circuit 4400, and is connected to the emitter of the IGBT 4123, the anode of the FRD tube 4113, the collector of the W-phase lower arm IGBT 4126, the cathode of the FRD tube 4116, and the other end of the capacitor 4133 outside the power driving circuit 4400, and serves as the negative end WVS of the W-phase high voltage area power supply of the intelligent power module 4100.

An LO1 end of the power driving circuit 4400 is connected with the gate of the IGBT tube 4124, an LO2 end of the power driving circuit 4400 is connected with the gate of the IGBT tube 4125, and an LO3 end of the power driving circuit 4400 is connected with the gate of the IGBT tube 4126.

The emitter of the IGBT tube 4124 is connected to the anode of the FRD tube 4114 and serves as the U-phase low-voltage reference terminal UN of the intelligent power module 4100, the emitter of the IGBT tube 4125 is connected to the anode of the FRD tube 4115 and serves as the V-phase low-voltage reference terminal VN of the intelligent power module 4100, and the emitter of the IGBT tube 4126 is connected to the anode of the FRD tube 4116 and serves as the W-phase low-voltage reference terminal WN of the intelligent power module 4100.

The collector of the IGBT tube 4121, the cathode of the FRD tube 4111, the collector of the IGBT tube 4122, the cathode of the FRD tube 4112, the collector of the IGBT tube 4123, and the cathode of the FRD tube 4113 are connected to each other and serve as a high voltage input terminal P of the intelligent power module 4100, P is generally connected to 300V, UN, VN, and WN and is commonly connected to the ISO terminal of the intelligent power module 4100 at the same time, the power supply point serves as the voltage signal itrp terminal of the power driving circuit 4400, and the voltage signal itrp is connected to the input terminal of the current detecting circuit 4302 inside the power driving circuit 4400.

The power driver circuit 4400 functions as follows:

VDD is the positive terminal of the power supply of the power driving circuit 4400, and GND is the negative terminal of the power supply of the power driving circuit 4400; the VDD-GND voltage is generally 15V;

VB1 and VS1 are respectively the positive pole and the negative pole of a power supply of a U-phase high-voltage area, HO1 is the output end of the U-phase high-voltage area, VB2 and VS2 are respectively the positive pole and the negative pole of the power supply of the V-phase high-voltage area, HO2 is the output end of the V-phase high-voltage area, VB3 and VS3 are respectively the positive pole and the negative pole of the power supply of the U-phase high-voltage area, HO3 is the output end of the W-phase high-voltage area, and LO1, LO2 and LO3 are respectively the output ends of the U-phase, the V-phase and the W-phase.

The operation principle based on the circuits of fig. 4 and 5 is as follows:

when the load is driven by the intelligent power module 4100 to normally operate, the output currents of the U-phase low-voltage reference terminal UN, the V-phase low-voltage reference terminal VN and the W-phase low-voltage reference terminal WN are normal, at this time, the voltage of the output current on the sampling resistor 4301 is normal, that is, the voltage of the voltage signal itrep is normal, therefore, the voltage of the itrep is smaller than the voltage of the voltage source 4322, the output terminal of the voltage comparator 4312 is at a high level, the high level passes through the first not gate 4332, the delay circuit 4342 and the second not gate 4352, then the first output terminal OUT1 outputs a first high level signal, and the second output terminal OUT2 of the fifth not gate 4362 outputs a second low level signal, at this time:

a first output end of the current detection circuit 4302 is at a high level, and a second output end of the current detection circuit 4302 is at a low level; the sixth not gate 4313 changes its output low level to high level through the seventh not gate 4353 and outputs it to the enable terminal EN of the gating circuit 4363, so that the enable terminal EN of the gating circuit 4363 is set high and does not work, at this time, all of the three output terminals Q1, Q2 and Q3 of the gating circuit 4363 output low levels to the control terminals of the fourth analog switch 43103, the fifth analog switch 43113 and the sixth analog switch 43123, so that the fourth analog switch 43103, the fifth analog switch 43113 and the sixth analog switch 43123 are all turned off, at the same time, the sixth not gate 4313 outputs low levels through the seventh not gate 4353 and changes them to high levels and outputs them to the control terminals of the first analog switch 4373, the second analog switch 4383 and the third analog switch 4393, so that these three analog switches are turned on, and the three input signals of the lower bridge over-current control circuit 4303 are respectively input to the three or input terminals of the gates 4343, 4333 and 4323 of the lower bridge over-current control circuit 4303 through these three analog switches, since the gating circuit 4363 does not operate, three output terminals thereof output low levels to the other input terminals of the three or gates 4343, 4333 and 4323, and the ninth not gate 4314 outputs high levels to the three and gates of the upper bridge over-current control circuit 4304, as is clear from the logical relationship between the or gates and the and gates,

at this time, the level of the first output end of the lower bridge over-current control circuit 4303 is made to be consistent with the level of the first input end of the lower bridge over-current control circuit 4303, the level of the second output end of the lower bridge over-current control circuit 4303 is made to be consistent with the level of the second input end of the lower bridge over-current control circuit 4303, and the level of the third output end of the lower bridge over-current control circuit 4303 is made to be consistent with the level of the third input end of the lower bridge over-current control circuit 4303; the level of the first output end of the upper bridge over-current control circuit 4304 is made to be consistent with the level of the first input end of the upper bridge over-current control circuit 4304, the level of the second output end of the upper bridge over-current control circuit 4304 is made to be consistent with the level of the second input end of the upper bridge over-current control circuit 4304, and the level of the third output end of the upper bridge over-current control circuit 4304 is made to be consistent with the level of the third input end of the upper bridge over-current control circuit 4304.

Transmitting 0 or 5V logic input signals of input terminals HIN1, HIN2, HIN3 and LIN1, LIN2 and LIN3 to output terminals HO1, HO2, HO3 and LO1, LO2 and LO3 respectively, wherein HO1 is a logic output signal of VS1 or VS1+15V, HO2 is a logic output signal of VS2 or VS2+15V, HO3 is a logic output signal of VS3 or VS3+15V, and LO1, LO2 and LO3 are logic output signals of 0 or 15V;

note that input signals of the same phase cannot be high at the same time, that is, HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 cannot be high at the same time.

When the current value of the load driven by the intelligent power module 4100 is too large, the output currents of the U-phase low-voltage reference terminal UN, the V-phase low-voltage reference terminal VN and the W-phase low-voltage reference terminal WN are correspondingly increased, and at this time, the voltage of the output current on the sampling resistor 4301 is increased, that is, the voltage of the voltage signal itrep is increased, so that the output current is increased

The voltage of ITRIP is greater than the voltage of the voltage source 4322, the output terminal of the voltage comparator 4312 is at low level, and then:

after the delay circuit 4342 starts to operate, the low level signal output by the voltage comparator 4312 starts to discharge the first capacitor 43423 after passing through the first not gate 4332 and the third not gate 43421, so that the voltage on the first capacitor 43423 gradually decreases, when the voltage decreases to the trigger voltage at the input end of the fourth not gate 43422, the output end of the fourth not gate 43422 outputs a high level signal, and outputs a first output low level signal through the first output end OUT1 after passing through the second not gate 4352, and outputs a second output high level signal through the second output end OUT2 of the fifth not gate 4362, at this time:

a first output terminal of the current detection circuit 4302 is at a low level, and a second output terminal of the current detection circuit 4302 is at a high level; then the sixth not gate 4313 outputs a high level, which is changed to a low level by the seventh not gate 4353, and outputs the low level to the enable end EN of the gating circuit 4363, so that the enable end EN of the gating circuit 4363 starts to operate effectively, at the same time, the sixth not gate 4313 outputs a high level to the clock input end CK of the gating circuit 4363, at the same time, the sixth not gate 4313 outputs a high level, which is changed to a low level by the seventh not gate 4353, and outputs the low level to the control ends of the first analog switch 4373, the second analog switch 4383, and the third analog switch 4393, so that these three analog switches are turned off, the signals at the three input ends of the lower bridge over-current control circuit 4303 are turned off from the input ends of the three or

gates

4343, 4333, and 4323 of the lower bridge over-current control circuit 4303, and at this time, the specific operating:

since the enable end EN of the gating circuit 4363 is low, the eighth not gate 43637 therein outputs high at this time, so that the control ends of the fourth analog switch 43634, the fifth analog switch 43635 and the sixth analog switch 43636 are enabled, the fourth analog switch 43634, the fifth analog switch 43635 and the sixth analog switch 43636 are all turned on, and the working principle of the D start register is known, the circuit connection manner of the first D flip-flop 43631, the second D flip-flop 43632 and the third D flip-flop 43633 forms a shift register, when an effective rising edge signal is input to each clock input terminal CK, the output ends of the three D flip-flops sequentially output high, that is, the output signals thereof are related to the arrival of the rising edge of each clock input terminal CK, and the logic truth table of the gating circuit 4363 is as follows:

namely:

when the first rising edge of the signal input terminal CK comes, the first output terminal Q1 outputs a high level; during this period, the other two output ends are at low level; when the second rising edge of CK comes, the first output terminal Q2 outputs a high level; during this period, the other two output ends are at low level; when the third rising edge of CK comes, the first output terminal Q3 outputs a high level; during this period, the other two output ends are at low level; the operation is repeated in such a way that the fourth analog switch 43103 closes the fifth analog switch 43113 and opens the sixth analog switch 43123 after the first rising edge of CK arrives; so that the fifth analog switch 43113 is closed and the fourth analog switch 43103 and the sixth analog switch 43123 are opened after the second rising edge of CK arrives; so that the sixth analog switch 43123 is closed and the fourth and fifth analog switches 43103 and 43113 are opened after the first rising edge of CK arrives; so as to reciprocate. Until the enable terminal of the gating circuit 4363 is deactivated.

The output end of the signal generator 43133 outputs a pulse signal with a preset frequency, such as a square wave with 50% duty and 100ns period;

since the signal input terminal CK is related to the over-current signal detected and outputted by the over-current detection circuit 4302, when the signal input terminal CK changes to a rising edge each time the over-current occurs, the gating circuit 4363 of the corresponding output terminal outputs a high level.

The seventh not gate 4314 outputs a low level; then the not gate 4313 outputs a high level to three or gates of the lower bridge over-current control circuit 4303, and the not gate 4314 outputs a low level to three and gates of the upper bridge over-current control circuit 4304, as is clear from the logical relationship of the or gates and the and gates,

therefore, the first input terminal, the second output terminal, and the third input terminal of the lower bridge overcurrent control circuit 4303 generate a high level with a duration of 50ns every 50ns when the intelligent power module 4100 is in overcurrent each time; the IGBT tube 4124, the IGBT tube 4125 and the IGBT tube 4126 are alternately conducted in each overcurrent, and are turned off for 50ns after the conduction time lasts for 50ns, and the operation is repeated in this way; therefore, the first output terminal, the second output terminal, and the third output terminal of the lower bridge overcurrent control circuit 4303 respectively form an intermittent discharge loop for N, and at this time, the inductive charges of the load driven by the smart power module 4100 are sequentially discharged.

No matter what levels the first input end, the second input end and the third input end of the upper bridge over-current control circuit 4304 are, the first output end, the second output end and the third output end of the upper bridge over-current control circuit 4304 are all low levels; therefore, the low level of the first output terminal, the second output terminal and the third output terminal of the over-bridge current control circuit 4304 causes HO1, HO2 and HO3 to output low level, so that the IGBT 4121, the IGBT 4122 and the IGBT 4123 are turned off.

Specifically, taking a 15A smart power module as an example, the sampling resistor 4301 may be designed to 33m Ω, and the voltage of the voltage source 4322 may be designed to 0.5V, then:

when the current flowing through the sampling resistor 4301 is less than 15A, the voltage of ITRIP is less than the voltage of the voltage source 4322;

when the current flowing through the sampling resistor 4301 is greater than 15A, the voltage of ITRIP is greater than the voltage of the voltage source 4322.

It can be known from the above analysis that when the intelligent power module 4100 drives the load to generate an overcurrent, the overcurrent detection circuit 4302 will delay through the internal delay circuit 4342 to output a protection control signal, and control the three-phase upper bridge arm IGBT tube to be turned off and the three-phase lower bridge arm IGBT tube to be turned on when the protection is generated, so that the noise filtering is facilitated by the delay of the built-in sampling resistor 4301 in response to the overcurrent voltage signal ITRIP, and the unnecessary shutdown is reduced, and when the overcurrent is generated, the current detection circuit 4302 makes the input signals of the upper and lower bridges fail to be transmitted to the output end of the power driving circuit 4400, so that the three output ends of the lower bridge of the power driving circuit 4400 output high levels according to the respective overcurrent, so that the three IGBT tubes of the lower bridge are turned on after the respective overcurrent, and the three output ends of the upper bridge of the power driving circuit 4400 are low levels, so that the three IGBT tubes of the lower bridge are turned off, the three IGBT tubes of the lower bridge are respectively conducted to form a discharging loop, so that the residual charge of the inductive load is discharged, the impact of the residual charge on the intelligent power module 4100 when the power is on again is avoided, the possibility of micro-damage to the intelligent power module is greatly reduced, in addition, the three IGBT tubes are respectively conducted intermittently after each overcurrent, the charge at the load end is respectively discharged slowly and intermittently from the three IGBT tubes, each discharging IGBT tube can averagely bear the voltage impact without excessively concentrating the impact, the long-term reliability of the intelligent power module is improved, in addition, each IGBT tube is not continuously conducted when being conducted, but is turned on and off according to certain frequency, each IGBT tube can obtain the heat dissipation time, the effect of protecting the IGBT tubes of the lower bridge is achieved, the risk of burning out of the intelligent power module during long-term work is reduced, and the safety and the robustness of a frequency conversion system are improved, the promotion of the popularization and the application of the frequency conversion household appliances has an important role.

The IPM module 4100 provided by the embodiment of the invention is internally provided with the detection circuit 4302, the upper bridge over-current control circuit 4304 and the lower bridge over-current control circuit 4303, and the sampling resistor 4301 is internally arranged, so that when the intelligent power module 4100 drives a load to generate over-current, a voltage signal on the sampling resistor 4301 during over-current can be subjected to delay feedback, so that voltage noise is filtered, and the accuracy of over-current detection is improved, and when the over-current occurs, the upper bridge over-current control circuit 4304 and the lower bridge over-current control circuit 4303 respectively control the three-phase upper bridge arm IGBT tubes to be turned off and the three-phase lower bridge arm IGBT tubes to be respectively turned on after each over-current, so that induced charges generated by the load 4100 driven by the IPM module 4100 during over-current can be effectively and safely discharged, thereby avoiding impact of residual charges on the IGBT tubes, and improving the reliability of the IPM module 4100.

The invention also provides an air conditioner controller, which is used for realizing the control of the air conditioner in relative charge, in particular to a variable frequency air conditioner, the air conditioner controller can be divided into controllers of an indoor unit part and an outdoor unit part, the indoor unit controller realizes the driving of the running of loads such as an indoor unit fan motor, an air guide strip and the like, the outdoor unit controller realizes the driving of the running of loads such as a compressor, an outdoor fan motor, a four-way valve and the like, wherein the outdoor controller comprises the IPM module for driving the running of the compressor, if the outdoor fan motor is a direct current fan, the interior of the outdoor controller also comprises the IPM module for driving the direct current fan, and if the indoor fan motor is a direct current fan, the interior of the indoor controller also comprises the IPM module for driving the direct current fan. For specific implementation and effects of the IPM module, reference may be made to the above embodiments, which are not described herein again.

The invention also provides an air conditioner, which comprises the air conditioner controller.

In the description herein, references to the description of the terms "first embodiment," "second embodiment," "example," etc., mean that a particular method, apparatus, or feature described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, methods, apparatuses, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

The above description is only a preferred embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes, which are made by using the contents of the present specification and the accompanying drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. An intelligent power module comprises a three-phase upper bridge arm IGBT tube, a three-phase lower bridge arm IGBT tube, a driving circuit corresponding to each IGBT tube in the three-phase upper bridge arm IGBT tube and the three-phase lower bridge arm IGBT tube, and a bridge arm control signal input end, and is characterized by further comprising an overcurrent detection circuit, an upper bridge overcurrent control circuit and a lower bridge overcurrent control circuit;

the over-current detection circuit is used for detecting the current value of the intelligent power module driving load, when the current value is greater than a preset current threshold value each time, the over-current detection circuit outputs a protection signal to the upper bridge over-current control circuit and the lower bridge over-current control circuit so as to disconnect the bridge arm control signal input end corresponding to the corresponding IGBT tube from the driving circuit and control the three-phase upper bridge arm IGBT tube to be cut off, and when the current value is greater than the preset current threshold value each time, each IGBT tube in the three-phase lower bridge arm IGBT tube is controlled to be intermittently conducted according to a preset frequency respectively so as to discharge the induced charge of the intelligent power module driving load;

the lower bridge overcurrent control circuit comprises a sixth NOT gate, a seventh NOT gate, a gating circuit, a first analog switch, a second analog switch, a third analog switch, a fourth analog switch, a fifth analog switch, a sixth analog switch, a signal generator, a first OR gate, a second OR gate and a third OR gate;

2. The smart power module of claim 1 wherein the over-current detection circuit comprises a comparison module, a delay module, and an output module;

3. The smart power module of claim 2 wherein the comparison module comprises a comparator, a voltage source;

one end of the voltage source is grounded, the other end of the voltage source is connected with the non-inverting input end of the comparator, and the inverting input end of the comparator is the input end of the comparison module.

4. The smart power module of claim 2 wherein the delay module comprises a delay circuit, a first not gate and a second not gate;

5. The smart power module of claim 2, wherein the output module comprises a fifth not gate;

6. The smart power module of claim 1 wherein the gating circuit comprises a seventh analog switch, an eighth analog switch, a ninth analog switch, an eighth not gate, a first D flip-flop, a second D flip-flop, and a third D flip-flop;

the clock input ends of the first D trigger, the second D trigger and the third D trigger are the clock input ends of the gating circuit, the output end of the first D trigger is connected with one end of the seventh analog switch, the output end of the second D trigger is connected with one end of the eighth analog switch, the output end of the third D trigger is connected with one end of the ninth analog switch, the output end of the first D trigger is simultaneously connected with the data end of the second D trigger, the output end of the second D trigger is simultaneously connected with the data end of the third D trigger, and the output end of the third D trigger is simultaneously connected with the data end of the first D trigger;

the other ends of the seventh analog switch, the eighth analog switch and the ninth analog switch form three output ends of the gating circuit;

the input end of the eighth not gate is the enabling end of the gating circuit, and the output end of the eighth not gate is respectively connected with the control ends of the seventh analog switch, the eighth analog switch and the ninth analog switch.

7. The smart power module of claim 1, wherein the upper bridge over-current control circuit comprises a ninth not gate, a first and gate, a second and gate, and a third and gate;

8. An air conditioner controller comprising the smart power module of any one of claims 1 to 7.

9. An air conditioner comprising the air conditioner controller as claimed in claim 8.