CN203480359U

CN203480359U - Intelligent power module

Info

Publication number: CN203480359U
Application number: CN201320517182.0U
Authority: CN
Inventors: 冯宇翔
Original assignee: Guangdong Midea Refrigeration Equipment Co Ltd
Current assignee: GD Midea Air Conditioning Equipment Co Ltd
Priority date: 2013-08-22
Filing date: 2013-08-22
Publication date: 2014-03-12
Anticipated expiration: 2023-08-22

Abstract

The utility model belongs to the field of power drive control, and provides an intelligent power module. The intelligent power module comprises an HVIC chip which comprises a high-voltage DMOS transistor DM1, a high-voltage DMOS transistor DM2, a high-voltage DMOS transistor DM3, a U-phase adjusting module, a V-phase adjusting module, a W-phase adjusting module, a U-phase adjusting module, a V-phase voltage sampling and a W-phase voltage sampling module. When three upper bridge arm signal ends of the HVIC chip are at low levels (low level time is longer than high level time), the HVIC chip can charge a filter capacitor and an energy storage capacitor externally connected with the intelligent power module, charging time is prolonged greatly, and therefore when the intelligent power module is switched on, charging time for the filter capacitor and the energy storage capacitor is prolonged correspondingly. Besides, the heat value of an IGBT is decreased when the IGBT is powered on, service life of the IGBT and service life of the intelligent power module are prolonged, and use safety of the intelligent power module is improved.

Description

A kind of Intelligent Power Module

Technical field

The utility model belongs to power drive control field, relates in particular to a kind of Intelligent Power Module.

Background technology

Intelligent Power Module (IPM, Intelligent Power Module) is the power drive series products of a kind of combination Power Electronic Technique and integrated circuit technique.Intelligent Power Module integrates device for power switching and high-voltage driving circuit, and is built-in with superpotential, excess current and the failure detector circuit such as overheated.Intelligent Power Module by receiving the control signal of MCU and driving subsequent conditioning circuit to work, feeds back to MCU by the state detection signal of system again on the one hand on the other hand.Compare with the discrete scheme of tradition, Intelligent Power Module wins increasing market with advantages such as its high integration, high reliability, being particularly suitable for frequency converter and the various inverter of drive motor, is the desirable power electronic devices for frequency control, metallurgical machinery, electric propulsion, servo driving and frequency-conversion domestic electric appliances.

As shown in Figure 1, it is for exporting U electricity, V electricity and W electricity mutually mutually mutually for the circuit structure of existing Intelligent Power Module.Wherein:

HVIC(High Voltage Integrated Circuit, high voltage integrated circuit) the power end VCC of chip 101 is as the low-pressure area power supply anode VDD of Intelligent Power Module, the voltage at VDD place is generally 15V, HVIC chip 101 first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2 and the 3rd brachium pontis signal end HIN3 as the U of Intelligent Power Module, go up mutually respectively that brachium pontis input end UHIN, V go up brachium pontis input end VHIN mutually and W goes up brachium pontis input end WHIN mutually, first time brachium pontis signal end LIN1 of HVIC chip 101, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 descend brachium pontis input end ULIN, V to descend mutually brachium pontis input end VLIN and W to descend mutually brachium pontis input end WLIN as the U of Intelligent Power Module respectively mutually, at this, Intelligent Power Module first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2, the 3rd voltage range of the input signal of brachium pontis signal end HIN3, first time brachium pontis signal end LIN1, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 be 0～5V, the earth terminal GND of HVIC chip 101 is as the low-pressure area power supply negative terminal COM of Intelligent Power Module, the first power supply anode VB1 of HVIC chip 101 is as the U phase higher-pressure region power supply anode UVB of Intelligent Power Module, the first higher-pressure region control end HO1 of HVIC chip 101 is connected with the grid of IGBT pipe Q1, the first power supply negative terminal VS1 end of HVIC chip 101 and the source electrode of described IGBT pipe Q1, the anode of fast recovery diode D1, the IGBT pipe drain electrode of D4 and the negative electrode of fast recovery diode D4 are connected, and as the U phase higher-pressure region power supply negative terminal UVS of Intelligent Power Module, the U phase higher-pressure region power supply anode UVB that filter capacitor C1 is connected in Intelligent Power Module powers between negative terminal UVS with U phase higher-pressure region, the second power supply anode VB2 of HVIC chip 101 is as the V phase higher-pressure region power supply anode VVB of Intelligent Power Module, the second higher-pressure region control end HO2 of HVIC chip 101 is connected with the grid of IGBT pipe Q2, the source electrode of the second power supply negative terminal VS2 of HVIC chip 101 and IGBT pipe Q2, the anode of fast recovery diode D2, the IGBT pipe drain electrode of Q5 and the negative electrode of fast recovery diode D5 are connected, and as the V phase higher-pressure region power supply negative terminal VVS of Intelligent Power Module, the V phase higher-pressure region power supply anode VVB that filter capacitor C2 is connected in Intelligent Power Module powers between negative terminal VVS with V phase higher-pressure region, the 3rd power supply anode VB3 of HVIC chip 101 is as the W phase higher-pressure region power supply anode WVB of Intelligent Power Module, the third high nip control end HO3 of HVIC chip 101 is connected with the grid of IGBT pipe Q3, the source electrode of the 3rd power supply negative terminal VS3 of HVIC chip 101 and IGBT pipe Q3, the anode of fast recovery diode D3, the IGBT pipe drain electrode of Q6 and the negative electrode of fast recovery diode D6 are connected, and as the W phase higher-pressure region power supply negative terminal WVS of Intelligent Power Module, the W phase higher-pressure region power supply anode WVB that filter capacitor C3 is connected in Intelligent Power Module powers between negative terminal WVS with W phase higher-pressure region, the first low-pressure area control end LO1, the second low-pressure area control end LO2 of HVIC chip 101 and the 3rd low-pressure area control end LO3 are connected with the grid of the grid of described IGBT pipe Q4, the grid of IGBT pipe Q5 and IGBT pipe Q6 respectively, the source electrode of IGBT pipe Q4 is connected with the anode of fast recovery diode D4, and as the U phase low reference voltage end UN of Intelligent Power Module, the source electrode of IGBT pipe Q5 is connected with the anode of fast recovery diode D5, and as the V phase low reference voltage end VN of Intelligent Power Module, the source electrode of IGBT pipe Q6 is connected with the anode of fast recovery diode D6, and as the W phase low reference voltage end WN of Intelligent Power Module, the drain electrode of Q1 of IGBT pipe, the negative electrode of fast recovery diode D1, the IGBT pipe drain electrode of Q2, the negative electrode of fast recovery diode D2, the IGBT pipe collector of Q3 are, the negative electrode of fast recovery diode D3 connects altogether and as the high voltage input end P of Intelligent Power Module, P generally accesses 300V voltage.

The effect of HVIC chip 101 is that the logical signal of 0～5V that HIN1, HIN2, HIN3, LIN1, LIN2, LIN3 are received passes to respectively HO1, HO2, HO3, LO1, LO2, LO3, what wherein HO1, HO2 and HO3 exported is the logical signal of VS～VS+15V, and LO1, LO2, LO3 are the logical signals of 0～15V; The input signal of same phase can not be high level simultaneously, the input signal of brachium pontis signal end HIN1 and first time brachium pontis signal end LIN1 can not be high level simultaneously on first, on second, the input signal of brachium pontis signal end HIN2 and second time brachium pontis signal end LIN2 can not be high level simultaneously, and the input signal of brachium pontis signal end HIN3 and the 3rd time brachium pontis signal end LIN3 can not be high level simultaneously on the 3rd.

HVIC chip 101 inside include boostrap circuit, and the structure of this boostrap circuit is as follows:

The source electrode of high pressure DMOS pipe DM1, the source electrode of the source electrode of high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3 is connected to the power end VCC of HVIC chip 101 altogether, the substrate of high pressure DMOS pipe DM1, the equal ground connection of substrate of the substrate of high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3, the drain electrode of high pressure DMOS pipe DM1, the drain electrode of the drain electrode of high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3 connects respectively the first power supply anode VB1 of HVIC chip 101, the second power supply anode VB2 and the 3rd power supply anode VB3, the input end of U phase control circuit 1011, the input end of the input end of V phase control circuit 1012 and W phase control circuit 1013 connects respectively first time brachium pontis signal end LIN1 of HVIC chip 101, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3, the output terminal of U phase control circuit 1011, the output terminal of the output terminal of V phase control circuit 1012 and W phase control circuit 1013 is managed respectively the grid of DM1 with high pressure DMOS, the grid of the grid of high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3 is connected.

When practical application, as shown in Figure 2, capacitor C 4 is connected between UVB and UVS the mode of connection of Intelligent Power Module, and capacitor C 5 is connected between VVB and VVS, and capacitor C 6 is connected between WVB and WVS; UN, VN, WN are connected to the first end of resistance R 1 altogether, and the second end and the COM of resistance R 1 are connected to ground altogether.Below that to take U be the principle of work of example explanation Intelligent Power Module mutually:

When LIN1 is high level, HIN1 is necessary for low level, now, LO1 and HO1 export respectively high level and low level, thereby make the voltage at VS1 place be about 0V, when LIN1 is high level, U phase control circuit 1011 output high level make high pressure DMOS pipe DM1 conducting, VCC by high pressure DMOS pipe DM1 to capacitor C 1 and capacitor C 4 chargings, when time long enough or make capacitor C 1 and capacitor C 4 chargings before dump energy when abundant, VB1 approaches 15V to the voltage of VS1.

When LIN1 is low level, HIN1 is low level or high level.When HIN1 is low level, the equal output low level of LO1 and HO1, now do not work and no-output in U phase higher-pressure region; And when HIN1 is high level, LO1 and HO1 be output low level and high level respectively, thereby make the voltage at VS1 place be about 300V.When LIN1 is low level, U phase control circuit 1011 output low levels make high pressure DMOS pipe DM1 cut-off, the voltage of VB1 is raised to 315V left and right, electric weight by capacitor C 1 and capacitor C 4 maintains U phase higher-pressure region and works, if the duration that HIN1 is high level, enough electric weight short or capacitor C 1 and capacitor C 4 storages was abundant, in the course of work of U phase higher-pressure region, more than VB1 can remain on 14V to the voltage of VS1.In actual application, after the external capacitor C 4 of Intelligent Power Module is fully charged, VB1 can remain between 14V～15V to maintain the normal operation of Intelligent Power Module the voltage of VS1, but when just powering on, VB1 tends to as shown in Figure 3 the waveform of the voltage VB1-VS1 of VS1.Because the initial quantity of electricity of capacitor C 1 and capacitor C 4 is 0, so when just powering on, capacitor C 1 and capacitor C 4 will be recharged, when LIN1 is high level to the voltage LIN1-GND of GND, U phase control circuit 1011 is controlled high pressure DMOS pipe DM1 conducting, so that VCC charges to capacitor C 1 and capacitor C 4, because the electric capacity of capacitor C 4 is generally larger and can reach 0.5～1mF, so, according to existing charging principle, capacitor C 1 and capacitor C 4 only just can be recharged when LIN1 is high level, after powering on during first three input signal of LIN1 input, required voltage V when the saturation voltage drop that VB1 does not often reach IGBT pipe Q1 to the voltage of VS1 is stablized _iGBT, and when HO1 output high level, HO1 is consistent with VB1 to the voltage difference of VS1 to the voltage difference of VS1, therefore, when just powering on, HO1 does not reach V to the voltage of VS1 _iGBT, IGBT pipe Q1 cannot stablize conducting.According to grid-emitter voltage V of IGBT pipe _gEwith its saturation voltage drop V _cESATrelation property, work as V _gE<V _iGBTtime, the saturation voltage drop V of IGBT pipe _cESATcan be sharply rise, and then the power consumption while causing the conducting of IGBT pipe sharply increases.

Therefore, for above-mentioned existing Intelligent Power Module, when just powering on, the saturation voltage drop of IGBT pipe can be very large, causes IGBT pipe because power consumption is rapid, to increase sharply heating, for some special operation condition, even can cause because of heat accumulation the blast of IGBT pipe, and for conventional operating mode, the sharply heating of each powered on moment also can cause shorten the serviceable life of IGBT pipe, and then the serviceable life of shortening Intelligent Power Module.

In sum, there is the saturation voltage drop of IGBT pipe when powering on excessive and heating reduction of service life sharply in existing Intelligent Power Module, the problem that even can explode and damage because of IGBT pipe.

Utility model content

The utility model provides a kind of Intelligent Power Module, be intended to solve existing Intelligent Power Module existing when powering on the saturation voltage drop of IGBT pipe excessive and heating reduction of service life sharply, the problem that even can damage because of the blast of IGBT pipe.

The utility model is to realize like this, an Intelligent Power Module, comprises that HVIC chip, IGBT pipe Q1, fast recovery diode D1, IGBT pipe Q2, fast recovery diode D2, IGBT pipe Q3, fast recovery diode D3, IGBT pipe Q4, fast recovery diode D4, IGBT pipe Q5, fast recovery diode D5, IGBT manage Q6, fast recovery diode D6, filter capacitor C1, filter capacitor C2 and filter capacitor C3, the power end of described HVIC chip is the low-pressure area power supply anode of described Intelligent Power Module, described HVIC chip first on brachium pontis signal end, the U that on second, on brachium pontis signal end and the 3rd, brachium pontis signal end is respectively described Intelligent Power Module goes up brachium pontis input end mutually, V goes up mutually brachium pontis input end and W goes up brachium pontis input end mutually, first time brachium pontis signal end of described HVIC chip, the U that second time brachium pontis signal end and the 3rd time brachium pontis signal end are respectively described Intelligent Power Module descends brachium pontis input end mutually, V descends brachium pontis input end and W to descend mutually brachium pontis input end mutually, the earth terminal of described HVIC chip is as the low-pressure area power supply negative terminal of described Intelligent Power Module, the first power supply anode of described HVIC chip is as the U phase higher-pressure region power supply anode of described Intelligent Power Module, the first higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q1, the source electrode of the first power supply negative terminal of described HVIC chip and described IGBT pipe Q1, the anode of described fast recovery diode D1, the described IGBT pipe drain electrode of Q4 and the negative electrode of described fast recovery diode D4 connect the U phase higher-pressure region power supply negative terminal as described Intelligent Power Module altogether, described filter capacitor C1 is connected in the U phase higher-pressure region power supply anode of described Intelligent Power Module and powers between negative terminal with U phase higher-pressure region, the second power supply anode of described HVIC chip is as the V phase higher-pressure region power supply anode of described Intelligent Power Module, the second higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q2, the source electrode of the second power supply negative terminal of described HVIC chip and described IGBT pipe Q2, the anode of described fast recovery diode D2, the described IGBT pipe drain electrode of Q5 and the negative electrode of described fast recovery diode D5 connect the V phase higher-pressure region power supply negative terminal as Intelligent Power Module altogether, described filter capacitor C2 is connected in the V phase higher-pressure region power supply anode of described Intelligent Power Module and powers between negative terminal with V phase higher-pressure region, the 3rd power supply anode of described HVIC chip is as the W phase higher-pressure region power supply anode of described Intelligent Power Module, the third high nip control end of described HVIC chip is connected with the grid of described IGBT pipe Q3, the source electrode of the 3rd power supply negative terminal of described HVIC chip and described IGBT pipe Q3, the anode of described fast recovery diode D3, the described IGBT pipe drain electrode of Q6 and the negative electrode of described fast recovery diode D6 connect the W phase higher-pressure region power supply negative terminal as described Intelligent Power Module altogether, described filter capacitor C3 is connected in the W phase higher-pressure region power supply anode of Intelligent Power Module and powers between negative terminal with W phase higher-pressure region, the first low-pressure area control end of described HVIC chip, the second low-pressure area control end and the 3rd low-pressure area control end are connected with the grid of the grid of described IGBT pipe Q4, the grid of described IGBT pipe Q5 and described IGBT pipe Q6 respectively, the described IGBT pipe drain electrode of Q1 and the negative electrode of described fast recovery diode D1, the drain electrode of described IGBT pipe Q2, the drain electrode of described fast recovery diode D2, the described IGBT pipe drain electrode of Q3 and the negative electrode of described fast recovery diode D3 connect formed contact altogether altogether as the high voltage input end of described Intelligent Power Module, the described IGBT pipe source electrode of Q4 and the anode of described fast recovery diode D4 connect formed contact altogether altogether as the U phase low reference voltage end of described Intelligent Power Module, the described IGBT pipe source electrode of Q5 and the anode of described fast recovery diode D5 connect formed contact altogether altogether as the V phase low reference voltage end of described Intelligent Power Module, the described IGBT pipe source electrode of Q6 and the anode of described fast recovery diode D6 connect formed contact altogether altogether as the W phase low reference voltage end of described Intelligent Power Module,

Described HVIC chip comprises a boostrap circuit, and described boostrap circuit comprises:

High pressure DMOS pipe DM1, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, V phase voltage sampling module and W phase voltage sampling module;

The source electrode of the source electrode of the source electrode of described high pressure DMOS pipe DM1 and described high pressure DMOS pipe DM2 and described high pressure DMOS pipe DM3 is connected to the power end of described HVIC chip altogether, the drain electrode of described high pressure DMOS pipe DM1, the drain electrode of the drain electrode of described high pressure DMOS pipe DM2 and described high pressure DMOS pipe DM3 connects respectively the first power supply anode of described HVIC chip, the second power supply anode and the 3rd power supply anode, the substrate of described high pressure DMOS pipe DM1, the equal ground connection of substrate of the substrate of described high pressure DMOS pipe DM2 and described high pressure DMOS pipe DM3, the control end of the first input end of described U phase adjusting module and described U phase voltage sampling module is connected to first time brachium pontis signal end of described HVIC chip altogether, the input end of described U phase voltage sampling module is connected respectively the described high pressure DMOS pipe drain electrode of DM1 and the second input end of described U phase adjusting module with output terminal, the 3rd input end and the output terminal of described U phase adjusting module is connected respectively the first power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM1, the control end of the first input end of described V phase adjusting module and described V phase voltage sampling module is connected to second time brachium pontis signal end of described HVIC chip altogether, the input end of described V phase voltage sampling module is connected respectively the described high pressure DMOS pipe drain electrode of DM2 and the second input end of described V phase adjusting module with output terminal, the 3rd input end and the output terminal of described V phase adjusting module is connected respectively the second power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM2, the control end of the first input end of described W phase adjusting module and described W phase voltage sampling module is connected to the 3rd time brachium pontis signal end of described HVIC chip altogether, the input end of described W phase voltage sampling module is connected respectively the described high pressure DMOS pipe drain electrode of DM3 and the second input end of described W phase adjusting module with output terminal, the 3rd input end and the output terminal of described W phase adjusting module is connected respectively the 3rd power supply negative terminal of described HVIC chip and the grid of described high pressure DMOS pipe DM3.

In the utility model, by adopting, comprise high pressure DMOS pipe DM1 in Intelligent Power Module, high pressure DMOS manages DM2, high pressure DMOS manages DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, the HVIC chip of V phase voltage sampling module and W phase voltage sampling module, HVIC chip first on brachium pontis signal end, when brachium pontis signal end is low level (low level time is greater than high level time) on brachium pontis signal end and the 3rd on second, can make the first power supply anode of HVIC chip, the second power supply anode and the 3rd power supply anode charge to filter capacitor and the external storage capacitor of Intelligent Power Module, duration of charging is significantly increased, thereby Intelligent Power Module is correspondingly increased when starting to the duration of charging of filter capacitor and storage capacitor, and and then reduce the thermal value of IGBT pipe when electrifying startup is worked, extend the serviceable life of IGBT pipe and the serviceable life of Intelligent Power Module, improve the safety in utilization of Intelligent Power Module, solved existing Intelligent Power Module existing when powering on the saturation voltage drop of IGBT pipe excessive and heating reduction of service life sharply, even can manage the problem that blast damages because of IGBT.

Accompanying drawing explanation

Fig. 1 is the structural representation of existing Intelligent Power Module;

Fig. 2 is Intelligent Power Module schematic diagram in actual applications;

Fig. 3 is each waveform voltage signal figure related in the course of work of existing Intelligent Power Module after electrifying startup;

Fig. 4 is the structural representation of the Intelligent Power Module that provides of the utility model embodiment;

Fig. 5 is the included U phase adjusting module of the HVIC chip in the Intelligent Power Module that provides of the utility model embodiment and the exemplary circuit structural drawing of U phase voltage sampling module;

Fig. 6 is the included V phase adjusting module of the HVIC chip in the Intelligent Power Module that provides of the utility model embodiment and the exemplary circuit structural drawing of V phase voltage sampling module;

Fig. 7 is the included W phase adjusting module of the HVIC chip in the Intelligent Power Module that provides of the utility model embodiment and the exemplary circuit structural drawing of W phase voltage sampling module;

Fig. 8 is the included U phase adjusting module of the HVIC chip in the Intelligent Power Module that provides of the utility model embodiment related level signal oscillogram in the course of the work.

Embodiment

In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.

The utility model embodiment comprises high pressure DMOS pipe DM1 by adopting in Intelligent Power Module, high pressure DMOS manages DM2, high pressure DMOS manages DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, the HVIC chip of V phase voltage sampling module and W phase voltage sampling module, Intelligent Power Module is correspondingly increased the duration of charging of filter capacitor and storage capacitor when starting, and and then reduce the thermal value of IGBT pipe when electrifying startup is worked, extend the serviceable life of IGBT pipe and the serviceable life of Intelligent Power Module, improve the safety in utilization of Intelligent Power Module.

Fig. 4 shows the structure of the Intelligent Power Module that the utility model embodiment provides, and for convenience of explanation, only shows the part relevant to the utility model, and details are as follows:

Intelligent Power Module comprises that HVIC chip 100, IGBT pipe Q1, fast recovery diode D1, IGBT pipe Q2, fast recovery diode D2, IGBT pipe Q3, fast recovery diode D3, IGBT pipe Q4, fast recovery diode D4, IGBT pipe Q5, fast recovery diode D5, IGBT manage Q6, fast recovery diode D6, filter capacitor C1, filter capacitor C2 and filter capacitor C3.

The power end VCC of HVIC chip 100 is the low-pressure area power supply anode VDD of Intelligent Power Module 100, HVIC chip 100 first on brachium pontis signal end HIN1, the U that on second, on brachium pontis signal end HIN2 and the 3rd, brachium pontis signal end HIN3 is respectively Intelligent Power Module goes up brachium pontis input end UHIN mutually, V goes up mutually brachium pontis input end VHIN and W goes up brachium pontis input end WHIN mutually, first time brachium pontis signal end LIN1 of HVIC chip 100, the U that second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 are respectively Intelligent Power Module descends brachium pontis input end ULIN mutually, V descends brachium pontis input end VLIN and W to descend mutually brachium pontis input end WLIN mutually, the earth terminal GND of HVIC chip 100 is as the low-pressure area power supply negative terminal COM of Intelligent Power Module, the first power supply anode VB1 of HVIC chip 100 is as the U phase higher-pressure region power supply anode UVB of Intelligent Power Module, the first higher-pressure region control end HO1 of HVIC chip 100 is connected with the grid of IGBT pipe Q1, the source electrode of the first power supply negative terminal VS1 of HVIC chip 100 and IGBT pipe Q1, the anode of fast recovery diode D1, the IGBT pipe drain electrode of Q4 and the negative electrode of fast recovery diode D4 meet the U phase higher-pressure region power supply negative terminal UVS as Intelligent Power Module altogether, the U phase higher-pressure region power supply anode UVB that filter capacitor C1 is connected in Intelligent Power Module powers between negative terminal UVS with U phase higher-pressure region, the second power supply anode VB2 of HVIC chip 100 is as the V phase higher-pressure region power supply anode VVB of Intelligent Power Module, the second higher-pressure region control end HO2 of HVIC chip 100 is connected with the grid of IGBT pipe Q2, the source electrode of the second power supply negative terminal VS2 of HVIC chip 100 and IGBT pipe Q2, the anode of fast recovery diode D2, the IGBT pipe drain electrode of Q5 and the negative electrode of fast recovery diode D5 meet the V phase higher-pressure region power supply negative terminal VVS as Intelligent Power Module altogether, the V phase higher-pressure region power supply anode VVB that filter capacitor C2 is connected in Intelligent Power Module powers between negative terminal VVS with V phase higher-pressure region, the 3rd power supply anode VB3 of HVIC chip 100 is as the W phase higher-pressure region power supply anode WVB of Intelligent Power Module, the third high nip control end HO3 of HVIC chip 100 is connected with the grid of IGBT pipe Q3, the source electrode of the 3rd power supply negative terminal VS3 of HVIC chip 100 and IGBT pipe Q3, the anode of fast recovery diode D3, the IGBT pipe drain electrode of Q6 and the negative electrode of fast recovery diode D6 meet the W phase higher-pressure region power supply negative terminal WVS as Intelligent Power Module altogether, the W phase higher-pressure region power supply anode WVB that filter capacitor C3 is connected in Intelligent Power Module powers between negative terminal WVS with W phase higher-pressure region, the first low-pressure area control end LO1, the second low-pressure area control end LO2 of HVIC chip 100 and the 3rd low-pressure area control end LO3 are connected with the grid of the grid of IGBT pipe Q4, the grid of IGBT pipe Q5 and IGBT pipe Q6 respectively, the IGBT pipe drain electrode of Q1 and the negative electrode of fast recovery diode D1, the drain electrode of IGBT pipe Q2, the drain electrode of fast recovery diode D2, the IGBT pipe drain electrode of Q3 and the negative electrode of fast recovery diode D3 connect formed contact altogether altogether as the high voltage input end P of Intelligent Power Module, the IGBT pipe source electrode of Q4 and the anode of fast recovery diode D4 connect formed contact altogether altogether as the U phase low reference voltage end UN of Intelligent Power Module, the IGBT pipe source electrode of Q5 and the anode of fast recovery diode D5 connect formed contact altogether altogether as the V phase low reference voltage end VN of Intelligent Power Module, the IGBT pipe source electrode of Q6 and the anode of fast recovery diode D6 connect formed contact altogether altogether as the W phase low reference voltage end WN of Intelligent Power Module.

HVIC chip 100 comprises a boostrap circuit 10, and this boostrap circuit 10 comprises high pressure DMOS pipe DM1, high pressure DMOS pipe DM2, high pressure DMOS pipe DM3, U phase adjusting module 101, V phase adjusting module 102, W phase adjusting module 103, U phase voltage sampling module 104, V phase voltage sampling module 105 and W phase voltage sampling module 106.

The source electrode of the source electrode of the source electrode of high pressure DMOS pipe DM1 and high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3 is connected to the power end VCC of HVIC chip 100 altogether, the drain electrode of high pressure DMOS pipe DM1, the drain electrode of the drain electrode of high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3 connects respectively the first power supply anode VB1 of HVIC chip 100, the second power supply anode VB2 and the 3rd power supply anode VB3, the substrate of high pressure DMOS pipe DM1, the equal ground connection of substrate of the substrate of high pressure DMOS pipe DM2 and high pressure DMOS pipe DM3, the control end of the first input end of U phase adjusting module 101 and U phase voltage sampling module 104 is connected to first time brachium pontis signal end LIN1 of HVIC chip 100 altogether, the input end of U phase voltage sampling module 104 is connected respectively the high pressure DMOS pipe drain electrode of DM1 and the second input end of U phase adjusting module 101 with output terminal, the 3rd input end and the output terminal of U phase adjusting module 101 is connected respectively the first power supply negative terminal of HVIC chip 100 and the grid of high pressure DMOS pipe DM1, the control end of the first input end of V phase adjusting module 102 and V phase voltage sampling module 105 is connected to second time brachium pontis signal end LIN2 of HVIC chip 100 altogether, the input end of V phase voltage sampling module 105 is connected respectively the high pressure DMOS pipe drain electrode of DM2 and the second input end of V phase adjusting module 102 with output terminal, the 3rd input end and the output terminal of V phase adjusting module 102 is connected respectively the second power supply negative terminal of HVIC chip 100 and the grid of high pressure DMOS pipe DM2, the control end of the first input end of W phase adjusting module 103 and W phase voltage sampling module 106 is connected to the 3rd time brachium pontis signal end LIN3 of HVIC chip 100 altogether, the input end of W phase voltage sampling module 106 is connected respectively the high pressure DMOS pipe drain electrode of DM3 and the second input end of W phase adjusting module 103 with output terminal, the 3rd input end and the output terminal of W phase adjusting module 103 is connected respectively the 3rd power supply negative terminal VS1 of HVIC chip 100 and the grid of high pressure DMOS pipe DM3.

Due to HVIC chip 100 first on the input signal of brachium pontis signal end HIN1 and first time brachium pontis signal end LIN1 can not be high level simultaneously, HVIC chip 100 second on the input signal of brachium pontis signal end HIN2 and second time brachium pontis signal end LIN2 can not be high level simultaneously, HVIC chip 100 the 3rd on the input signal of brachium pontis signal end HIN3 and the 3rd time brachium pontis signal end LIN3 can not be high level simultaneously, so, first time brachium pontis signal end LIN1 at HVIC chip 100, when second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 are respectively high level, HVIC chip 100 first on brachium pontis signal end HIN1, on second, on brachium pontis signal end HIN2 and the 3rd, brachium pontis signal end HIN3 is respectively low level, when first time brachium pontis signal end LIN1 of HVIC chip 100, second time brachium pontis signal end LIN2 and the 3rd time brachium pontis signal end LIN3 are respectively low level, HVIC chip 100 first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2 and the 3rd brachium pontis signal end HIN3 be respectively high level or low level, hence one can see that, HVIC chip 100 first on brachium pontis signal end HIN1, second on brachium pontis signal end HIN2 and the 3rd brachium pontis signal end HIN3 in the low level time, be greater than respectively the time of high level.

When HVIC chip 100 first on brachium pontis signal end HIN1 while being low level, the level that U phase adjusting module 101 is inputted according to first of HVIC chip 100 time brachium pontis signal end LIN1, the Voltage-output high level of the first power supply negative terminal VS1 of the output voltage of U phase voltage sampling module 104 and HVIC chip 100 drives high pressure DMOS pipe DM1 conducting, and the storage capacitor C4(that the voltage that the power end VCC of HVIC chip 100 inputs is powered between negative terminal UVS to filter capacitor C1 and the U phase higher-pressure region power supply anode UVB that is connected in Intelligent Power Module and U phase higher-pressure region by high pressure DMOS pipe DM1 is as shown in Figure 2) charge.

When HVIC chip 100 second on brachium pontis signal end HIN2 while being low level, the level that V phase adjusting module 102 is inputted according to second of HVIC chip 100 time brachium pontis signal end LIN2, the Voltage-output high level of the second power supply negative terminal VS2 of the output voltage of V phase voltage sampling module 105 and HVIC chip 100 drives high pressure DMOS pipe DM2 conducting, and the storage capacitor C5(that the voltage that the power end VCC of HVIC chip 100 inputs is powered between negative terminal VVS to filter capacitor C2 and the V phase higher-pressure region power supply anode VVB that is connected in Intelligent Power Module and V phase higher-pressure region by high pressure DMOS pipe DM2 is as shown in Figure 2) charge.

When HVIC chip 100 the 3rd on brachium pontis signal end HIN3 while being low level, W phase adjusting module 103 is according to level that the 3rd of HVIC chip 100 the time brachium pontis signal end LIN3 inputs, the Voltage-output high level of the 3rd power supply negative terminal VS3 of the output voltage of W phase voltage sampling module 106 and HVIC chip 100 drives high pressure DMOS pipe DM3 conducting, and the storage capacitor C6(that the voltage that the power end of HVIC chip 100 is inputted is powered between negative terminal WVS to filter capacitor C3 and the W phase higher-pressure region power supply anode WVB that is connected in Intelligent Power Module and W phase higher-pressure region by high pressure DMOS pipe DM3 is as shown in Figure 2) charge.

Wherein, take U phase adjusting module 101(V phase adjusting module 102 and W phase adjusting module 103 in like manner) be example, when the first input end of U phase adjusting module 101 is low level, the output terminal of U phase adjusting module 101 can be exported high level, and from its second input end, receives the voltage of the first power supply negative terminal of HVIC chip 100 simultaneously; When the first input end of U phase adjusting module 101 is high level, U phase adjusting module 101 according to its first input end upper while being once high level, the received voltage of its second input end with and the first input end voltage output level correspondingly that becomes its 3rd input end after low level, this level is divided into following two kinds of situations:

(1) when the magnitude of voltage of the second input end is lower than predeterminated voltage value V _iTtime, concrete condition is as follows:

If the magnitude of voltage of the 3rd input end is lower than 15V-V _iT, U phase adjusting module 101 keeps high level output;

If the magnitude of voltage of the 3rd input end is higher than 15V-V _iT, U phase adjusting module 101 output low levels.

(2) when the magnitude of voltage of the second input end is higher than predeterminated voltage value V _iTtime, U phase adjusting module 101 output low levels.

As the utility model one embodiment, as shown in Figure 5, U phase adjusting module 101 comprises:

The first Schmidt trigger U1, first or door U2, the first Sheffer stroke gate U3, the first not gate U4, the second not gate U5, the 3rd not gate U6, the first rest-set flip-flop RS1, the 4th not gate U7, the first comparer U8, the first voltage source V 1, the 5th not gate U9, the first rejection gate U10, the 6th not gate U11, the 7th not gate U12, capacitor C 7, the second rest-set flip-flop RS2, the second comparer U13, the 8th not gate U14, second voltage source V2 and high pressure DMOS pipe DM4;

The input end of the first Schmidt trigger U1 is the first input end of U phase adjusting module 101, the output terminal of the first Schmidt trigger U1 connects first or the door first input end 1 of U2 and the second input end S of the second rest-set flip-flop RS2 simultaneously, first or the second input end 2 of door U2 connect the output terminal of the 4th not gate U7, first or the door output terminal 3 of U2 and the output terminal of the second not gate U5 be connected respectively first input end 1 and the second input end 2 of the first Sheffer stroke gate U3, the output terminal 3 of the first Sheffer stroke gate U3 connects the input end of the first not gate U4, the output terminal of the first not gate U4 is the output terminal of U phase adjusting module 101, the in-phase input end of the first comparer U8 is the second input end of U phase adjusting module 101, the anode of the first voltage source V 1 and negative terminal are connected respectively the inverting input of the first comparer U8-and ground, the output terminal of the first comparer U8 connects the input end of the 3rd not gate U6 simultaneously, the input end of the input end of the 5th not gate U9 and the 6th not gate U11, the output terminal of the 3rd not gate U6 connects the first input end R of the first rest-set flip-flop RS1, the output terminal of the 5th not gate U9 connects the first input end 1 of the first rejection gate U10, the first end of the output terminal of the 6th not gate U11 and capacitor C 7 is connected to the input end of the 7th not gate U12 altogether, the second end ground connection of capacitor C 7, the 7th not gate U12 connects the second input end 2 of the first rejection gate U10, the output terminal 3 of the first rejection gate U10 connects the second input end S of the first rest-set flip-flop RS1, the output terminal Q of the first rest-set flip-flop RS1 connects the input end of the 4th not gate U7, the drain electrode of high pressure DMOS pipe DM4 is the 3rd input end of U phase adjusting module 101, the substrate ground connection of high pressure DMOS pipe DM4, the source electrode of high pressure DMOS pipe DM4 connects the in-phase input end of the second comparer U13, the grid of high pressure DMOS pipe DM4 is connected with the output terminal Q of the second rest-set flip-flop RS2 and the input end of the 8th not gate U14 simultaneously, the anode of second voltage source V2 and negative terminal are connected respectively inverting input and the ground of the second comparer U13, the output terminal of the second comparer U13 connects the first input end R of the second rest-set flip-flop RS2, the output terminal of the 8th not gate U14 connects the input end of the second not gate U5.Wherein, the anode of the first voltage source V 1 is 15V to the anode of the voltage of negative terminal and second voltage source V2 to the voltage sum of negative terminal.

As the utility model one embodiment, as shown in Figure 6, V phase adjusting module 102 comprises:

The second Schmidt trigger U15, second or door U16, the second Sheffer stroke gate U17, the 9th not gate U18, the tenth not gate U19, the 11 not gate U20, the 3rd rest-set flip-flop RS3, the 12 not gate U21, the 3rd comparer U22, tertiary voltage source V3, the 13 not gate U23, the second rejection gate U24, the 14 not gate U25, the 15 not gate U26, capacitor C 8, the 4th rest-set flip-flop RS4, the 4th comparer U27, the 16 not gate U28, the 4th voltage source V 4 and high pressure DMOS pipe DM5;

The input end of the second Schmidt trigger U15 is the first input end of V phase adjusting module 102, the output terminal of the second Schmidt trigger U15 connects second or the door first input end 1 of U16 and the second input end S of the 4th rest-set flip-flop RS4 simultaneously, second or the second input end 2 of door U16 connect the output terminal of the 12 not gate U21, second or the door output terminal 3 of U16 and the output terminal of the tenth not gate U19 be connected respectively first input end 1 and the second input end 2 of the second Sheffer stroke gate U17, the output terminal 3 of the second Sheffer stroke gate U17 connects the input end of the 9th not gate U18, the output terminal of the 9th not gate U18 is the output terminal of V phase adjusting module 102, the in-phase input end of the 3rd comparer U22 is the second input end of V phase adjusting module 102, the anode of tertiary voltage source V3 and negative terminal are connected respectively the inverting input of the 3rd comparer U22-and ground, the output terminal of the 3rd comparer U22 connects the input end of the 11 not gate U20 simultaneously, the 13 input end of not gate U23 and the input end of the 14 not gate U25, the output terminal of the 11 not gate U20 connects the first input end R of the 3rd rest-set flip-flop RS3, the output terminal of the 13 not gate U23 connects the first input end 1 of the second rejection gate U24, the first end of the output terminal of the 14 not gate U25 and capacitor C 8 is connected to the input end of the 15 not gate U26 altogether, the second end ground connection of capacitor C 8, the 15 not gate U26 connects the second input end 2 of the second rejection gate U24, the output terminal 3 of the second rejection gate U24 connects the second input end S of the 3rd rest-set flip-flop RS3, the output terminal Q of the 3rd rest-set flip-flop RS3 connects the input end of the 12 not gate U21, the drain electrode of high pressure DMOS pipe DM5 is the 3rd input end of V phase adjusting module 102, the substrate ground connection of high pressure DMOS pipe DM5, the source electrode of high pressure DMOS pipe DM5 connects the in-phase input end of the 4th comparer U27, the grid of high pressure DMOS pipe DM5 is connected with the output terminal Q of the 4th rest-set flip-flop RS4 and the input end of the 16 not gate U28 simultaneously, the anode of the 4th voltage source V 4 and negative terminal are connected respectively inverting input and the ground of the 4th comparer U27, the output terminal of the 4th comparer U27 connects the first input end R of the 4th rest-set flip-flop RS4, the output terminal of the 16 not gate U28 connects the input end of the tenth not gate U19.Wherein, the anode of tertiary voltage source V3 is 15V to the anode of the voltage of negative terminal and the 4th voltage source V 4 to the voltage sum of negative terminal.

As the utility model one embodiment, as shown in Figure 7, W phase adjusting module 103 comprises:

The 3rd Schmidt trigger U29, the 3rd or door U30, the 3rd Sheffer stroke gate U31, the 17 not gate U32, the 18 not gate U33, the 19 not gate U34, the 5th rest-set flip-flop RS5, the 20 not gate U35, the 5th comparer U36, the 5th voltage source V 5, the 21 not gate U37, the 3rd rejection gate U38, the 22 not gate U39, the 23 not gate U40, capacitor C 9, the 6th rest-set flip-flop RS6, the 6th comparer U41, the 24 not gate U42, the 6th voltage source V 6 and high pressure DMOS pipe DM6,

The input end of the 3rd Schmidt trigger U29 is the first input end of W phase adjusting module 103, the output terminal of the 3rd Schmidt trigger U29 connects the 3rd or the door first input end 1 of U30 and the second input end S of the 6th rest-set flip-flop RS6 simultaneously, the 3rd or the second input end 2 of door U30 connect the output terminal of the 20 not gate U35, the 3rd or output terminal 3 and the output terminal of the 18 not gate U33 of door U30 be connected respectively first input end 1 and the second input end 2 of the 3rd Sheffer stroke gate U31, the output terminal 3 of the 3rd Sheffer stroke gate U31 connects the input end of the 17 not gate U32, the output terminal of the 17 not gate U32 is the output terminal of W phase adjusting module 103, the in-phase input end of the 5th comparer U36 is the second input end of W phase adjusting module 103, the anode of the 5th voltage source V 5 and negative terminal are connected respectively inverting input and the ground of the 5th comparer U36, the output terminal of the 5th comparer U36 connects the input end of the 19 not gate U34 simultaneously, the 21 input end of not gate U37 and the input end of the 22 not gate U39, the output terminal of the 19 not gate U34 connects the first input end R of the 5th rest-set flip-flop RS5, the output terminal of the 21 not gate U37 connects the first input end 1 of the 3rd rejection gate U38, the first end of the output terminal of the 22 not gate U39 and capacitor C 9 is connected to the input end of the 23 not gate U40 altogether, the second end ground connection of capacitor C 9, the 23 not gate U40 connects the second input end 2 of the 3rd rejection gate U38, the output terminal 3 of the 3rd rejection gate U38 connects the second input end S of the 5th rest-set flip-flop RS5, the output terminal Q of the 5th rest-set flip-flop RS5 connects the input end of the 20 not gate U35, the drain electrode of high pressure DMOS pipe DM6 is the 3rd input end of W phase adjusting module 103, the substrate ground connection of high pressure DMOS pipe DM6, the source electrode of high pressure DMOS pipe DM6 connects the in-phase input end of the 6th comparer U41, the grid of high pressure DMOS pipe DM6 is connected with the output terminal Q of the 6th rest-set flip-flop RS6 and the input end of the 24 not gate U42 simultaneously, the anode of the 6th voltage source V 6 and negative terminal are connected respectively inverting input and the ground of the 6th comparer U41, the output terminal of the 6th comparer U41 connects the first input end R of the 6th rest-set flip-flop RS6, the output terminal of the 24 not gate U42 connects the input end of the 18 not gate U33.Wherein, the anode of the 5th voltage source V 5 is 15V to the anode of the voltage of negative terminal and the 6th voltage source V 6 to the voltage sum of negative terminal.

As the utility model one embodiment, as shown in Figure 5, U phase voltage sampling module 104 comprises:

The 25 not gate U43, the 26 not gate U44 and high pressure DMOS pipe DM7;

The input end of the 25 not gate U43 is the control end of U phase voltage sampling module 104, the output terminal of the 25 not gate U43 connects the input end of the 26 not gate U44, the output terminal of the 26 not gate U44 connects the grid of high pressure DMOS pipe DM7, the drain electrode of high pressure DMOS pipe DM7 and input end and the output terminal that source electrode is respectively U phase voltage sampling module 104, the substrate ground connection of high pressure DMOS pipe DM7.

As the utility model one embodiment, as shown in Figure 6, V phase voltage sampling module 105 comprises:

The 27 not gate U45, the 28 not gate U46 and high pressure DMOS pipe DM8;

The input end of the 27 not gate U45 is the control end of V phase voltage sampling module 105, the output terminal of the 27 not gate U45 connects the input end of the 28 not gate U46, the output terminal of the 28 not gate U46 connects the grid of high pressure DMOS pipe DM8, the drain electrode of high pressure DMOS pipe DM8 and input end and the output terminal that source electrode is respectively V phase voltage sampling module 105, the substrate ground connection of high pressure DMOS pipe DM8.

As the utility model one embodiment, as shown in Figure 7, W phase voltage sampling module 106 comprises:

The 29 not gate U47, the 30 not gate U48 and high pressure DMOS pipe DM9;

The input end of the 29 not gate U47 is the control end of W phase voltage sampling module 106, the output terminal of the 29 not gate U47 connects the input end of the 30 not gate U48, the output terminal of the 30 not gate U48 connects the grid of high pressure DMOS pipe DM9, the drain electrode of high pressure DMOS pipe DM9 and input end and the output terminal that source electrode is respectively W phase voltage sampling module 106, the substrate ground connection of high pressure DMOS pipe DM9.

Because U phase adjusting module 101 is identical with the inner structure of V phase adjusting module 102 and W phase adjusting module 103, and U phase voltage sampling module 104 is identical with the inner structure of V phase voltage sampling module 105 and W phase voltage sampling module 106, so above-mentioned Intelligent Power Module is described further below in conjunction with the principle of work of U phase adjusting module 101 and U phase voltage sampling module 104:

The anode of supposing the first voltage source V 1 is V to the voltage of negative terminal _iT, the anode of second voltage source V2 is 15V-V to the voltage of negative terminal _iT.

When the power end VCC of HVIC chip 100 has just powered on, the output terminal Q of the output terminal Q of the first rest-set flip-flop RS1 and the second rest-set flip-flop RS2 is output low level all.

State one: when LIN1 accesses high level first, LO1 is also high level, so IGBT pipe Q4 conducting is 0 voltage thereby make VS1, VB1 is not now recharged, so be 0 voltage yet, the high level of LIN1 is also high level after the first Schmidt trigger U1, thereby make first or door U2 output high level, and the second input end S of the second rest-set flip-flop RS2 is high level, the output terminal Q of the second rest-set flip-flop RS2 is output as high level, and then make described high pressure DMOS pipe DM4 conducting, so the second comparer U13 (is 15V-V by the voltage of the voltage of VS1 and second voltage source V2 _iT) compare, because VS1 is 0 voltage, so the second comparer U13 output low level, the 8th not gate U14 output low level and the second not gate U5 output high level, that is the first input end 1 of the first Sheffer stroke gate U3 and the second input end 2 are all high level, so the first Sheffer stroke gate U3 output low level, the first not gate U4 is high level output by this low transition, high pressure DMOS pipe DM1 conducting, the power end VCC of HVIC chip 100 charges to filter capacitor C1 and storage capacitor C4 charging (to filter capacitor C1 and storage capacitor C4 charging) to VB1 by high pressure DMOS pipe DM1, the high level of LIN1 is high level after the 25 not gate U43 and the 26 not gate U44, high pressure DMOS pipe DM7 conducting, and the first comparer U8 (is V by the voltage of the voltage of VB1 and the first voltage source V 1 _iT) compare, and voltage is very low while being just recharged due to VB1 place, so the first voltage comparator U8 keeps low level output, and then make the 3rd not gate U6 export high level, the 5th not gate U9 output high level, the first input end R of the first rest-set flip-flop RS1 and the second input end S are respectively high level and low level, and the first rest-set flip-flop RS1 output terminal Q keeps low level output, the 4th not gate U7 output high level, at VB1, continued to charge to VB1 voltage over the ground higher than V _iT, the output of the first comparer U8 becomes high level from low level, the 3rd not gate U6 is output low level thereupon, the high level of the first comparer U8 output is from the waveform M of the common contact of the input end of the 5th not gate U9 and the input end of the 6th not gate U11, the waveform A of the first input end 1 of the first rejection gate U10, the waveform C of the waveform B of the second input end 2 of the first rejection gate U10 and the output terminal 3 of the first rejection gate U10 as shown in Figure 8, owing to there being capacitor C 7, the high level of the input end of the 5th not gate U9 and the common contact of the input end of the 6th not gate U11 arrives time of the second input end 2 of the first rejection gate U10 than the slightly time delay of the time of the first input end of the first rejection gate U10 1, delay time can be set to 300ns by adjusting the electric capacity of capacitor C 7, the output terminal 3 of the first rejection gate U10 can produce at the rising edge of waveform M the high level of a 300ns, this high level can make the output terminal Q output high level of the first rest-set flip-flop RS1, and the output terminal Q that makes the first rest-set flip-flop RS1 after the high level of waveform C disappears keeps high level constant.

State two: when LIN1 becomes low level from high level, if the voltage of VB1 is higher than V _iT, the 4th not gate U7 output low level, if the voltage of VB1 is still lower than V _iT, the 4th not gate U7 is output as high level; If the 4th not gate U7 output low level, first or door U2 output low level, the first Sheffer stroke gate U3 output high level, the first not gate U4 output low level, and then high pressure DMOS pipe DM1 is turn-offed, the power end VCC of HVIC chip 100 stops VB1 charging; If the 4th not gate U7 output high level, first or door U2 output high level, so, when LIN1 just becomes low level from high level, the second input end S of the second rest-set flip-flop RS2 becomes low level, and the single R of its first input keeps low level, at this moment, the output terminal Q of the second rest-set flip-flop RS2 keeps original high level output;

In said process, the voltage of VS1 may raise gradually, when the voltage of VS1 (is also 15V-V lower than the voltage of second voltage source V2 _iT) time, the output terminal Q of the second comparer U13 keeps high level, the 8th not gate U14 keeps low level output, and the second not gate U5 keeps high level output, so the first Sheffer stroke gate U3 output low level, the first not gate U4 output high level, so high pressure DMOS pipe DM1 keeps conducting state, the power end VCC of HVIC chip 100 continues to charge to VB1, and then guarantee that the pressure drop ratio between VB1 and VS1 is lower, and LIN1 is when low level state, still can VB1 be charged by the power end VCC of HVIC chip 100, thereby make Intelligent Power Module when just starting, the ascending velocity of the voltage of VB1 is largely increased.

When the voltage of VS1 (is 15-V higher than the voltage of second voltage source V2 _iT) time, the second comparer U13 output high level, the output terminal Q of the second rest-set flip-flop RS2 is reset and output low level, so high pressure DMOS pipe DM4 turn-offs, after high pressure DMOS pipe SM4 is turned off, the output of the second comparer U13 reverts to low level, but because the second input end S of the second rest-set flip-flop RS2 is still low level, so the output terminal Q of the second rest-set flip-flop RS2 keeps low level constant, the constant output high level of the 8th not gate U14, constant output low level of the second not gate U5, thereby make the first Sheffer stroke gate U3 output high level, the first not gate U4 output low level, high pressure DMOS pipe DM1 is turned off, the power end VCC of HVIC chip 100 stops VB1 charging.

State three: when LIN1 accesses high level again, the output terminal Q of the second rest-set flip-flop RS2 is become high level by set again, LO1 exports high level, IGBT pipe Q4 conducting, VS1 is no-voltage, the input/output state of each components and parts returns to the situation of above-mentioned state one, so moves in circles and carries out work.

Because U phase adjusting module 101 is identical with the inner structure of V phase adjusting module 102 and W phase adjusting module 103, U phase voltage sampling module 104 is identical with the inner structure of V phase voltage sampling module 105 and W phase voltage sampling module 106, so V phase adjusting module 102 is all identical with above-mentioned principle of work with the principle of work of W phase voltage sampling module 106 with principle of work and the W phase adjusting module 103 of V phase voltage sampling module 105, therefore repeats no more.

The utility model embodiment comprises high pressure DMOS pipe DM1 by adopting in Intelligent Power Module, high pressure DMOS manages DM2, high pressure DMOS manages DM3, U phase adjusting module, V phase adjusting module, W phase adjusting module, U phase voltage sampling module, the HVIC chip of V phase voltage sampling module and W phase voltage sampling module, HVIC chip first on brachium pontis signal end, when brachium pontis signal end is low level (low level time is greater than high level time) on brachium pontis signal end and the 3rd on second, can make the first power supply anode of HVIC chip, the second power supply anode and the 3rd power supply anode charge to filter capacitor and the external storage capacitor of Intelligent Power Module, duration of charging is significantly increased, thereby Intelligent Power Module is correspondingly increased when starting to the duration of charging of filter capacitor and storage capacitor, and and then reduce the thermal value of IGBT pipe when electrifying startup is worked, extend the serviceable life of IGBT pipe and the serviceable life of Intelligent Power Module, improve the safety in utilization of Intelligent Power Module.

The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.

Claims

1. an Intelligent Power Module, comprises that HVIC chip, IGBT pipe Q1, fast recovery diode D1, IGBT pipe Q2, fast recovery diode D2, IGBT pipe Q3, fast recovery diode D3, IGBT pipe Q4, fast recovery diode D4, IGBT pipe Q5, fast recovery diode D5, IGBT manage Q6, fast recovery diode D6, filter capacitor C1, filter capacitor C2 and filter capacitor C3, the power end of described HVIC chip is the low-pressure area power supply anode of described Intelligent Power Module, described HVIC chip first on brachium pontis signal end, the U that on second, on brachium pontis signal end and the 3rd, brachium pontis signal end is respectively described Intelligent Power Module goes up brachium pontis input end mutually, V goes up mutually brachium pontis input end and W goes up brachium pontis input end mutually, first time brachium pontis signal end of described HVIC chip, the U that second time brachium pontis signal end and the 3rd time brachium pontis signal end are respectively described Intelligent Power Module descends brachium pontis input end mutually, V descends brachium pontis input end and W to descend mutually brachium pontis input end mutually, the earth terminal of described HVIC chip is as the low-pressure area power supply negative terminal of described Intelligent Power Module, the first power supply anode of described HVIC chip is as the U phase higher-pressure region power supply anode of described Intelligent Power Module, the first higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q1, the source electrode of the first power supply negative terminal of described HVIC chip and described IGBT pipe Q1, the anode of described fast recovery diode D1, the described IGBT pipe drain electrode of Q4 and the negative electrode of described fast recovery diode D4 connect the U phase higher-pressure region power supply negative terminal as described Intelligent Power Module altogether, described filter capacitor C1 is connected in the U phase higher-pressure region power supply anode of described Intelligent Power Module and powers between negative terminal with U phase higher-pressure region, the second power supply anode of described HVIC chip is as the V phase higher-pressure region power supply anode of described Intelligent Power Module, the second higher-pressure region control end of described HVIC chip is connected with the grid of described IGBT pipe Q2, the source electrode of the second power supply negative terminal of described HVIC chip and described IGBT pipe Q2, the anode of described fast recovery diode D2, the described IGBT pipe drain electrode of Q5 and the negative electrode of described fast recovery diode D5 connect the V phase higher-pressure region power supply negative terminal as Intelligent Power Module altogether, described filter capacitor C2 is connected in the V phase higher-pressure region power supply anode of described Intelligent Power Module and powers between negative terminal with V phase higher-pressure region, the 3rd power supply anode of described HVIC chip is as the W phase higher-pressure region power supply anode of described Intelligent Power Module, the third high nip control end of described HVIC chip is connected with the grid of described IGBT pipe Q3, the source electrode of the 3rd power supply negative terminal of described HVIC chip and described IGBT pipe Q3, the anode of described fast recovery diode D3, the described IGBT pipe drain electrode of Q6 and the negative electrode of described fast recovery diode D6 connect the W phase higher-pressure region power supply negative terminal as described Intelligent Power Module altogether, described filter capacitor C3 is connected in the W phase higher-pressure region power supply anode of Intelligent Power Module and powers between negative terminal with W phase higher-pressure region, the first low-pressure area control end of described HVIC chip, the second low-pressure area control end and the 3rd low-pressure area control end are connected with the grid of the grid of described IGBT pipe Q4, the grid of described IGBT pipe Q5 and described IGBT pipe Q6 respectively, the described IGBT pipe drain electrode of Q1 and the negative electrode of described fast recovery diode D1, the drain electrode of described IGBT pipe Q2, the drain electrode of described fast recovery diode D2, the described IGBT pipe drain electrode of Q3 and the negative electrode of described fast recovery diode D3 connect formed contact altogether altogether as the high voltage input end of described Intelligent Power Module, the described IGBT pipe source electrode of Q4 and the anode of described fast recovery diode D4 connect formed contact altogether altogether as the U phase low reference voltage end of described Intelligent Power Module, the described IGBT pipe source electrode of Q5 and the anode of described fast recovery diode D5 connect formed contact altogether altogether as the V phase low reference voltage end of described Intelligent Power Module, the described IGBT pipe source electrode of Q6 and the anode of described fast recovery diode D6 connect formed contact altogether altogether as the W phase low reference voltage end of described Intelligent Power Module, it is characterized in that:

2. Intelligent Power Module as claimed in claim 1, is characterized in that, described U phase adjusting module comprises:

The first Schmidt trigger, first or door, the first Sheffer stroke gate, the first not gate, the second not gate, the 3rd not gate, the first rest-set flip-flop, the 4th not gate, the first comparer, the first voltage source, the 5th not gate, the first rejection gate, the 6th not gate, the 7th not gate, capacitor C 7, the second rest-set flip-flop, the second comparer, the 8th not gate, second voltage source and high pressure DMOS pipe DM4;

The input end of described the first Schmidt trigger is the first input end of described U phase adjusting module, the output terminal of described the first Schmidt trigger connect simultaneously described first or door first input end and the second input end of described the second rest-set flip-flop, described first or the second input end of door connect the output terminal of described the 4th not gate, described first or output terminal and the output terminal of described the second not gate of door be connected respectively first input end and second input end of described the first Sheffer stroke gate, the output terminal of described the first Sheffer stroke gate connects the input end of described the first not gate, the output terminal of described the first not gate is the output terminal of described U phase adjusting module, the in-phase input end of described the first comparer is the second input end of described U phase adjusting module, the anode of described the first voltage source and negative terminal are connected respectively inverting input and the ground of described the first comparer, the output terminal of described the first comparer connects the input end of described the 3rd not gate simultaneously, the input end of the input end of described the 5th not gate and described the 6th not gate, the output terminal of described the 3rd not gate connects the first input end of described the first rest-set flip-flop, the output terminal of described the 5th not gate connects the first input end of described the first rejection gate, the first end of the output terminal of described the 6th not gate and described capacitor C 7 is connected to the input end of described the 7th not gate altogether, the second end ground connection of described capacitor C 7, described the 7th not gate connects the second input end of described the first rejection gate, the output terminal of described the first rejection gate connects the second input end of described the first rest-set flip-flop, the output terminal of described the first rest-set flip-flop connects the input end of described the 4th not gate, the drain electrode of described high pressure DMOS pipe DM4 is the 3rd input end of described U phase adjusting module, the substrate ground connection of described high pressure DMOS pipe DM4, the source electrode of described high pressure DMOS pipe DM4 connects the in-phase input end of described the second comparer, the grid of described high pressure DMOS pipe DM4 is connected with the output terminal of described the second rest-set flip-flop and the input end of described the 8th not gate simultaneously, the anode in described second voltage source and negative terminal are connected respectively inverting input and the ground of described the second comparer, the output terminal of described the second comparer connects the first input end of described the second rest-set flip-flop, the output terminal of described the 8th not gate connects the input end of described the second not gate.

3. Intelligent Power Module as claimed in claim 1, is characterized in that, described V phase adjusting module comprises:

The second Schmidt trigger, second or door, the second Sheffer stroke gate, the 9th not gate, the tenth not gate, the 11 not gate, the 3rd rest-set flip-flop, the 12 not gate, the 3rd comparer, tertiary voltage source, the 13 not gate, the second rejection gate, the 14 not gate, the 15 not gate, capacitor C 8, the 4th rest-set flip-flop, the 4th comparer, the 16 not gate, the 4th voltage source and high pressure DMOS pipe DM5;

The input end of described the second Schmidt trigger is the first input end of described V phase adjusting module, the output terminal of described the second Schmidt trigger connect simultaneously described second or door first input end and the second input end of described the 4th rest-set flip-flop, described second or the second input end of door connect the output terminal of described the 12 not gate, described second or output terminal and the output terminal of described the tenth not gate of door be connected respectively first input end and second input end of described the second Sheffer stroke gate, the output terminal of described the second Sheffer stroke gate connects the input end of described the 9th not gate, the output terminal of described the 9th not gate is the output terminal of described V phase adjusting module, the in-phase input end of described the 3rd comparer is the second input end of described V phase adjusting module, the anode in described tertiary voltage source and negative terminal are connected respectively inverting input and the ground of described the 3rd comparer, the output terminal of described the 3rd comparer connects the input end of described the 11 not gate simultaneously, described the 13 input end of not gate and the input end of described the 14 not gate, the output terminal of described the 11 not gate connects the first input end of described the 3rd rest-set flip-flop, the output terminal of described the 13 not gate connects the first input end of described the second rejection gate, the first end of the output terminal of described the 14 not gate and described capacitor C 8 is connected to the input end of described the 15 not gate altogether, the second end ground connection of described capacitor C 8, described the 15 not gate connects the second input end of described the second rejection gate, the output terminal of described the second rejection gate connects the second input end of described the 3rd rest-set flip-flop, the output terminal of described the 3rd rest-set flip-flop connects the input end of described the 12 not gate, the drain electrode of described high pressure DMOS pipe DM5 is the 3rd input end of described V phase adjusting module, the substrate ground connection of described high pressure DMOS pipe DM5, the source electrode of described high pressure DMOS pipe DM5 connects the in-phase input end of described the 4th comparer, the grid of described high pressure DMOS pipe DM5 is connected with described the 4th output terminal of rest-set flip-flop and the input end of described the 16 not gate simultaneously, the anode of described the 4th voltage source and negative terminal are connected respectively inverting input and the ground of described the 4th comparer, the output terminal of described the 4th comparer connects the first input end of described the 4th rest-set flip-flop, the output terminal of described the 16 not gate connects the input end of described the tenth not gate.

4. Intelligent Power Module as claimed in claim 1, is characterized in that, described W phase adjusting module comprises:

The 3rd Schmidt trigger, the 3rd or door, the 3rd Sheffer stroke gate, the 17 not gate, the 18 not gate, the 19 not gate, the 5th rest-set flip-flop, the 20 not gate, the 5th comparer, the 5th voltage source, the 21 not gate, the 3rd rejection gate, the 22 not gate, the 23 not gate, capacitor C 9, the 6th rest-set flip-flop, the 6th comparer, the 24 not gate, the 6th voltage source and high pressure DMOS pipe DM6;

The input end of described the 3rd Schmidt trigger is the first input end of described W phase adjusting module, the output terminal of described the 3rd Schmidt trigger connect simultaneously the described the 3rd or door first input end and the second input end of described the 6th rest-set flip-flop, the described the 3rd or the second input end of door connect the output terminal of described the 20 not gate, the described the 3rd or output terminal and the output terminal of described the 18 not gate of door be connected respectively first input end and second input end of described the 3rd Sheffer stroke gate, the output terminal of described the 3rd Sheffer stroke gate connects the input end of described the 17 not gate, the output terminal of described the 17 not gate is the output terminal of described W phase adjusting module, the in-phase input end of described the 5th comparer is the second input end of described W phase adjusting module, the anode of described the 5th voltage source and negative terminal are connected respectively inverting input and the ground of described the 5th comparer, the output terminal of described the 5th comparer connects the input end of described the 19 not gate simultaneously, described the 21 input end of not gate and the input end of described the 22 not gate, the output terminal of described the 19 not gate connects the first input end of described the 5th rest-set flip-flop, the output terminal of described the 21 not gate connects the first input end of described the 3rd rejection gate, the first end of the output terminal of described the 22 not gate and described capacitor C 9 is connected to the input end of described the 23 not gate altogether, the second end ground connection of described capacitor C 9, described the 23 not gate connects the second input end of described the 3rd rejection gate, the output terminal of described the 3rd rejection gate connects the second input end of described the 5th rest-set flip-flop, the output terminal of described the 5th rest-set flip-flop connects the input end of described the 20 not gate, the drain electrode of described high pressure DMOS pipe DM6 is the 3rd input end of described W phase adjusting module, the substrate ground connection of described high pressure DMOS pipe DM6, the source electrode of described high pressure DMOS pipe DM6 connects the in-phase input end of described the 6th comparer, the grid of described high pressure DMOS pipe DM6 is connected with described the 6th output terminal of rest-set flip-flop and the input end of described the 24 not gate simultaneously, the anode of described the 6th voltage source and negative terminal are connected respectively inverting input and the ground of described the 6th comparer, the output terminal of described the 6th comparer connects the first input end of described the 6th rest-set flip-flop, the output terminal of described the 24 not gate connects the input end of described the 18 not gate.

5. Intelligent Power Module as claimed in claim 1, is characterized in that, described U phase voltage sampling module comprises:

The 25 not gate, the 26 not gate and high pressure DMOS pipe DM7;

The input end of described the 25 not gate is the control end of described U phase voltage sampling module, the output terminal of described the 25 not gate connects the input end of described the 26 not gate, the output terminal of described the 26 not gate connects the grid of described high pressure DMOS pipe DM7, the drain electrode of described high pressure DMOS pipe DM7 and input end and the output terminal that source electrode is respectively described U phase voltage sampling module, the substrate ground connection of described high pressure DMOS pipe DM7.

6. Intelligent Power Module as claimed in claim 1, is characterized in that, described V phase voltage sampling module comprises:

The 27 not gate, the 28 not gate and high pressure DMOS pipe DM8;

The input end of described the 27 not gate is the control end of described V phase voltage sampling module, the output terminal of described the 27 not gate connects the input end of described the 28 not gate, the output terminal of described the 28 not gate connects the grid of described high pressure DMOS pipe DM8, the drain electrode of described high pressure DMOS pipe DM8 and input end and the output terminal that source electrode is respectively described V phase voltage sampling module, the substrate ground connection of described high pressure DMOS pipe DM8.

7. Intelligent Power Module as claimed in claim 1, is characterized in that, described W phase voltage sampling module comprises:

The 29 not gate, the 30 not gate and high pressure DMOS pipe DM9;

The input end of described the 29 not gate is the control end of described W phase voltage sampling module, the output terminal of described the 29 not gate connects the input end of described the 30 not gate, the output terminal of described the 30 not gate connects the grid of described high pressure DMOS pipe DM9, the drain electrode of described high pressure DMOS pipe DM9 and input end and the output terminal that source electrode is respectively described W phase voltage sampling module, the substrate ground connection of described high pressure DMOS pipe DM9.