CN105356785B - SPM and air conditioner - Google Patents
SPM and air conditioner Download PDFInfo
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- CN105356785B CN105356785B CN201510860689.XA CN201510860689A CN105356785B CN 105356785 B CN105356785 B CN 105356785B CN 201510860689 A CN201510860689 A CN 201510860689A CN 105356785 B CN105356785 B CN 105356785B
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Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0006—Arrangements for supplying an adequate voltage to the control circuit of converters
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Conversion In General (AREA)
- Inverter Devices (AREA)
Abstract
The invention provides a kind of SPM and air conditioner, SPM includes：Bridge arm signal input part, current detecting end and PFC control signals under bridge arm signal input part, three-phase on three-phase；The first port corresponding to current detecting end and the second port corresponding to PFC control signals are provided with HVIC pipes；The first input end of adaptive circuit is connected to first port, and the second input of adaptive circuit is connected to second port, the Enable Pin of the output end of adaptive circuit as HVIC pipes；Wherein, for adaptive circuit when the input signal of the second input is in rising edge, the result detected twice according to the input signal to first input end exports the enable signal of corresponding level；Adaptive circuit carries out the enable signal of the corresponding level of result output of one-time detection according to the input signal to first input end when the input signal of the second input is not in rising edge.
Description
Technical field
It is empty in particular to a kind of SPM and one kind the present invention relates to SPM technical field
Adjust device.
Background technology
SPM (Intelligent Power Module, abbreviation IPM) is a kind of by power electronics deviding device
The analog line driver that part and integrated circuit technique integrate, SPM include device for power switching and high drive
Circuit, and with failure detector circuits such as overvoltage, overcurrent and overheats.The logic input terminal of SPM receives master control
The control signal of device processed, output end driving compressor or subsequent conditioning circuit work, while the system status signal detected is sent back to
Master controller.Relative to traditional discrete scheme, SPM has high integration, high reliability, self-test and protection circuit
Etc. advantage, be particularly suitable for the frequency converter of motor and various inverters, be frequency control, metallurgical machinery, electric propulsion,
The desired power level electronic device of servo-drive, frequency-conversion domestic electric appliances.
The structural representation of existing Intelligent power module circuit as shown in figure 1, MTRIP ports as current detecting end,
To be protected according to the size of current detected to SPM 100.PFCIN ports are as SPM
PFC (Power Factor Correction, PFC) control signal.
In the SPM course of work, certain frequency frequent switching between low and high level is pressed at PFCINP ends, is made
IGBT pipes 127 are continuously on off state and FRD pipes 131 are continuously in freewheeling state, the frequency be generally LIN1~LIN3,
2~4 times of HIN1~HIN3 switching frequencies, and do not contacted directly with LIN1~LIN3, HIN1~HIN3 switching frequency.
As shown in Fig. 2 UN, VN, WN meet one end of milliohm resistance 138, another the termination GND, MTRIP of milliohm resistance 138
It is current detecting pin, connects one end of milliohm resistance 138, electric current is calculated by the pressure drop for detecting milliohm resistance, as shown in figure 3,
When current is excessive, SPM 100 is stopped, avoid after producing overheat because of excessively stream, to SPM 100
Produce permanent damage.
- VP, COM, UN, VN, WN have electrical connection in actual use.Therefore, 121~IGBT of IGBT pipes pipes 127 are opened
Current noise when voltage noise during pass and FRD 111~FRD of pipe pipes 116, FRD 131 afterflows of pipe can all intercouple, right
The input pin of each low-voltage area impacts.
In each input pin, HIN1~HIN3, LIN1~LIN3, PFCINP threshold value typically in 2.3V or so, and
ITRIP threshold voltage typically only has 0.5V once, and therefore, ITRIP is the pin for being most susceptible to interference.When ITRIP by
Triggering, SPM 100 will be stopped, and because excessively stream now really occurs, ITRIP now tactile
Hair belongs to false triggering.As shown in figure 4, it is high level in PFCIN, when IGBT pipes 127 open moment, because FRD pipes 131 is reverse
The presence of restoring current, is superimposed out I131Current waveform, the electric current has larger concussion noise, by-VP, COM, UN, VN,
Electrical connections of the WN in peripheral circuit, concussion noise close out certain voltage in MTRIP ends meeting lotus root and raised.If trigger MTRIP
Condition be：Voltage>Vth, and duration>Tth；In Fig. 4, if Ta<Tth<Tb is then too high in the voltage in first three cycle
It is insufficient to allow MTRIP to produce false triggering, to the 4th cycle, MTRIP will produce false triggering.
The length of the reverse recovery time of FRD pipes is relevant with temperature, and temperature is higher, and reverse recovery time is longer, therefore with
The continuous firing of system, the constant temperature of SPM 100 rises, and the probability that MTRIP is triggered is increasing, one
A little severe application scenarios, eventually produce false triggering, make system stalls.Although this false triggering over time can
Recover to destroy without forming system, but undoubtedly user can be caused to perplex.Such as the application scenario of transducer air conditioning, ring
It is exactly user when more need air-conditioning system continuous firing that border temperature is higher, but high environment temperature can make the reverse of FRD pipes
Recovery time increases, and MTRIP is improved by the probability of false triggering, once MTRIP can be because being mistakenly considered to occur by false triggering, air-conditioning system
Excessively stream and be stopped 3~5 minutes, user can not be during this period of time obtained cold wind, this be cause air-conditioning system because refrigeration
Scarce capacity is by one of the main reason for customer complaint.
Therefore, how on the premise of ensuring that SPM has high reliability and high-adaptability, effectively drop
Low SPM turns into technical problem urgently to be resolved hurrily by the probability of false triggering.
The content of the invention
It is contemplated that at least solves one of technical problem present in prior art or correlation technique.
Therefore, it is an object of the present invention to propose a kind of new SPM, intelligent work(can ensured
On the premise of rate module has high reliability and high-adaptability, SPM is effectively reduced by the probability of false triggering.
It is another object of the present invention to propose a kind of air conditioner.
To achieve the above object, embodiment according to the first aspect of the invention, it is proposed that a kind of SPM, bag
Include：Bridge arm signal input part, three-phase low reference voltage end, current detecting end and PFC under bridge arm signal input part, three-phase on three-phase
Control signal；HVIC is managed, and is provided with the HVIC pipes and is respectively connecting on the three-phase bridge arm signal input part and described
The terminals of bridge arm signal input part under three-phase, and corresponding to the first port at the current detecting end and corresponding to described
The second port of PFC control signals, the first port are connected by connecting line with the current detecting end, second end
Mouth is connected by connecting line with the PFC control signals；Sampling resistor, the three-phase low reference voltage end and electric current inspection
The first end that end is connected to the sampling resistor is surveyed, the second end of the sampling resistor is connected to the SPM
Low-pressure area power supply negative terminal；Adaptive circuit, the power supply positive pole and negative pole of the adaptive circuit are respectively connecting to institute
State the low-pressure area power supply anode and negative terminal of SPM, the first input end of the adaptive circuit is connected to described
First port, the second input of the adaptive circuit are connected to the second port, the output end of the adaptive circuit
Enable Pin as the HVIC pipes；
Wherein, the adaptive circuit is when the input signal of second input is in rising edge, according to described
The result that the input signal of first input end is detected twice exports the enable signal of corresponding level；The adaptive circuit exists
When the input signal of second input is not in rising edge, carried out once according to the input signal to the first input end
The result of detection exports the enable signal of corresponding level.
SPM according to an embodiment of the invention, due to being in high level wink in second port (i.e. PFCINP)
Between, if the voltage pulsation of first port (ITRIP) is because circuit noise causes, then ITRIP voltages are a lasting drops
Low process, therefore by setting adaptive circuit, be in the input signal in the second input (i.e. PFC control signals)
During rising edge, the result detected twice according to the input signal to first input end (current detecting end) exports corresponding level
Enable signal so that in PFCINP high level moments, can be filtered out by secondary detection because circuit noise causes malfunction
May；And if coming from real excessively stream during ITRIP voltage pulsation, then ITRIP voltages are a processes continued to increase,
Secondary detection exports low level after confirming and is able to ensure that SPM is stopped to form protection in time.
By when the input signal of the second input is not in rising edge, being entered according to the input signal to first input end
The result of row one-time detection exports the enable signal of corresponding level so that after PFCINP high level, SPM can
To carry out conventional detection judgement, with the current signal detected at current detecting end it is excessive when, to SPM provide and
When protection.
SPM according to the abovementioned embodiments of the present invention, there can also be following technical characteristic：
According to one embodiment of present invention, the adaptive circuit is in upper in the input signal of second input
Rise along when, when the result that the input signal to the first input end is detected twice is that magnitude of voltage is higher than predetermined value,
The enable signal of the first level is exported, to forbid the HVIC pipes to work；Otherwise, the enable signal of second electrical level is exported, to permit
Perhaps described HVIC pipes work；
The adaptive circuit is when the input signal of second input is not in rising edge, when defeated to described first
When the result for entering the input signal progress one-time detection at end is that magnitude of voltage is higher than predetermined value, the enabled letter of first level is exported
Number；Otherwise, the enable signal of the second electrical level is exported.
Wherein, the enable signal of the first level can be low level signal, and the enable signal of second electrical level can be high electricity
Ordinary mail number.
According to one embodiment of present invention, the adaptive circuit includes：
First voltage comparator, the positive input terminal of the first voltage comparator are first defeated as the adaptive circuit
Enter end, the negative input end of the first voltage comparator is connected to the positive pole of voltage source, described in the negative pole of the voltage source is used as
The power supply negative pole of adaptive circuit, the output end of the first voltage comparator are connected to the first choice of analog switch
End；
The first NOT gate and the second NOT gate being connected in series, the input of first NOT gate is as the adaptive circuit
Second input, the output end of second NOT gate are connected to the first input end of the first NAND gate；
The 3rd NOT gate, the 4th NOT gate and the 5th NOT gate being connected in series, the input of the 3rd NOT gate are connected to described
The input of first NOT gate, the output end of the 5th NOT gate are connected to the second input of first NAND gate, and described
The output end of one NAND gate is connected to the input of the 6th NOT gate, and the output end of the 6th NOT gate is connected to the analog switch
Control terminal；
First electric capacity, be connected to the 4th NOT gate input and the adaptive circuit power supply negative pole it
Between；
Second electric capacity, be connected to the 5th NOT gate input and the adaptive circuit power supply negative pole it
Between；
The 7th NOT gate being connected in series and the 8th NOT gate, the input of the 7th NOT gate are connected to first NOT gate
Input, the output end of the 8th NOT gate are connected to the first input end of the second NAND gate；
The 9th NOT gate, the tenth NOT gate and the 11st NOT gate being connected in series, the input of the 9th NOT gate are connected to institute
The input of the first NOT gate is stated, the output end of the 11st NOT gate is connected to the second input of second NAND gate, institute
The output end for stating the second NAND gate is connected to the input of the 12nd NOT gate；
3rd electric capacity, be connected to the 11st NOT gate input and the adaptive circuit power supply negative pole it
Between；
Rest-set flip-flop, the R ends of the rest-set flip-flop are connected to the output end of the 12nd NOT gate；
The a/d converter and D/A converter being connected in series, the input of the a/d converter are connected to the first voltage ratio
Compared with device positive input terminal and the positive input terminal of second voltage comparator, the output end of the D/A converter is connected to the second voltage
The negative input end of comparator, the output end of the second voltage comparator are connected to the S ends of the rest-set flip-flop；
3rd NAND gate, the output end of the 6th NOT gate, the output end of the first voltage comparator and the RS are touched
The Q ends of hair device are respectively connecting to three inputs of the 3rd NAND gate, and the output end of the 3rd NAND gate is connected to the
The input of 13 NOT gates, the output end of the 13rd NOT gate are connected to the second selection end of the analog switch, the mould
The fixing end for intending switch is connected to the input of the 14th NOT gate, and the output end of the 14th NOT gate is as the adaptive electricity
The output end on road.
According to one embodiment of present invention, the signal output part of PFC drive circuits, institute are additionally provided with the HVIC pipes
Stating SPM also includes：First power switch pipe and the first diode, the anode of first diode are connected to institute
The emitter stage of the first power switch pipe is stated, the negative electrode of first diode is connected to the current collection of first power switch pipe
Pole, the colelctor electrode of first power switch pipe are connected to the anode of the second diode, the negative electrode connection of second diode
To the high voltage input of the SPM, the base stage of first power switch pipe is connected to the PFC drivings electricity
The signal output part on road, the PFC low reference voltages of the emitter stage of first power switch pipe as the SPM
End, the PFC ends of the colelctor electrode of first power switch pipe as the SPM.
Wherein, the first power switch pipe can be IGBT (Insulated Gate Bipolar Transistor, insulation
Grid bipolar transistor).
According to one embodiment of present invention, in addition to：Boostrap circuit, the boostrap circuit include：First two poles of bootstrapping
Pipe, the anode of first bootstrap diode are connected to the low-pressure area power supply anode of the SPM, and described the
The negative electrode of one bootstrap diode is connected to the U phases higher-pressure region power supply anode of the SPM；Second two poles of bootstrapping
Pipe, the anode of second bootstrap diode are connected to the low-pressure area power supply anode of the SPM, and described the
The negative electrode of two bootstrap diodes is connected to the V phases higher-pressure region power supply anode of the SPM；3rd two poles of bootstrapping
Pipe, the anode of the 3rd bootstrap diode are connected to the low-pressure area power supply anode of the SPM, and described the
The negative electrode of three bootstrap diodes is connected to the W phases higher-pressure region power supply anode of the SPM.
According to one embodiment of present invention, in addition to：Bridge arm circuit on three-phase, it is every in bridge arm circuit on the three-phase
The input of bridge arm circuit is connected to the signal output part that phase is corresponded in the three-phase high-voltage area of the HVIC pipes in one phase；Under three-phase
Bridge arm circuit, the input of bridge arm circuit is connected to the three-phase of the HVIC pipes under each phase under the three-phase in bridge arm circuit
The signal output part of phase is corresponded in low-pressure area.
Wherein, bridge arm circuit includes on three-phase：Bridge arm circuit in U phases, bridge arm circuit in V phases, bridge arm circuit in W phases；Three
Bridge arm circuit includes under phase：Bridge arm circuit under bridge arm circuit, W phases under bridge arm circuit, V phases under U phases.
According to one embodiment of present invention, bridge arm circuit includes in each phase：Second power switch pipe and the 3rd
Diode, the anode of the 3rd diode are connected to the emitter stage of second power switch pipe, the 3rd diode
Negative electrode is connected to the colelctor electrode of second power switch pipe, and the colelctor electrode of second power switch pipe is connected to the intelligence
The high voltage input of power model, the input of the base stage of second power switch pipe as bridge arm circuit in each phase
End, the emitter stage of second power switch pipe, which is connected to the SPM and corresponds to the higher-pressure region power supply of phase, to be born
End.Wherein, the second power switch pipe can be IGBT.
According to one embodiment of present invention, bridge arm circuit includes under each phase：3rd power switch pipe and the 4th
Diode, the anode of the 4th diode are connected to the emitter stage of the 3rd power switch pipe, the 4th diode
Negative electrode is connected to the colelctor electrode of the 3rd power switch pipe, and the colelctor electrode of the 3rd power switch pipe is connected on corresponding
The anode of the 3rd diode in bridge arm circuit, the base stage of the 3rd power switch pipe is as bridge arm under each phase
The input of circuit, the emitter stage of the 3rd power switch pipe are joined as the low-voltage of the corresponding phase of the SPM
Examine end.Wherein, the 3rd power switch pipe can be IGBT.
According to one embodiment of present invention, the voltage of the high voltage input of the SPM is 300V.
According to one embodiment of present invention, the anode of each phase higher-pressure region power supply of the SPM and
Filter capacitor is connected between negative terminal.
Embodiment according to a second aspect of the present invention, it is also proposed that a kind of air conditioner, including：Any one embodiment as described above
Described in SPM.
The additional aspect and advantage of the present invention will be set forth in part in the description, and will partly become from the following description
Obtain substantially, or recognized by the practice of the present invention.
Brief description of the drawings
The above-mentioned and/or additional aspect and advantage of the present invention will become in the description from combination accompanying drawings below to embodiment
Substantially and it is readily appreciated that, wherein：
Fig. 1 shows the structural representation of the SPM in correlation technique；
Fig. 2 shows the external circuit schematic diagram of SPM；
Fig. 3 shows the waveform diagram that current signal triggering SPM is stopped；
Fig. 4 shows the waveform diagram of noise caused by SPM in correlation technique；
Fig. 5 shows the structural representation of SPM according to an embodiment of the invention；
Fig. 6 shows the internal structure schematic diagram of adaptive circuit according to an embodiment of the invention.
Embodiment
It is below in conjunction with the accompanying drawings and specific real in order to be more clearly understood that the above objects, features and advantages of the present invention
Mode is applied the present invention is further described in detail.It should be noted that in the case where not conflicting, the implementation of the application
Feature in example and embodiment can be mutually combined.
Many details are elaborated in the following description to facilitate a thorough understanding of the present invention, still, the present invention may be used also
To be different from other modes described here using other to implement, therefore, protection scope of the present invention is not by described below
Specific embodiment limitation.
Fig. 5 shows the structural representation of SPM according to an embodiment of the invention.
As shown in figure 5, SPM according to an embodiment of the invention, including：HVIC pipes 1101 and adaptive electricity
Road 1105.
The VCC ends of HVIC pipes 1101 are general as low-pressure area power supply the anode VDD, VDD of SPM 1100
For 15V；
Inside HVIC pipes 1101：
ITRIP ends connect the first input end of adaptive circuit 1105；The of PININP ends connection adaptive circuit 1105
Two inputs；VCC ends connect the power supply anode of adaptive circuit 1105；GND ends connect the power supply of adaptive circuit 1105
Power supply negative terminal；The output end of adaptive circuit 1105 is designated as ICON, for controlling HIN1~HIN3, LIN1~LIN3, PFCINP
The validity of signal.
The inside of HVIC pipes 1101 also has boostrap circuit structure as follows：
VCC ends are connected with the anode of bootstrap diode 1102, bootstrap diode 1103, bootstrap diode 1104；Bootstrapping two
The negative electrode of pole pipe 1102 is connected with the VB1 of HVIC pipes 1101；The VB2 phases of the negative electrode of bootstrap diode 1103 and HVIC pipes 1101
Even；The negative electrode of bootstrap diode 1104 is connected with the VB3 of HVIC pipes 1101.
The HIN1 ends of HVIC pipes 1101 are bridge arm signal input part UHIN in the U phases of SPM 1100；HVIC is managed
1101 HIN2 ends are bridge arm signal input part VHIN in the V phases of SPM 1100；The HIN3 ends of HVIC pipes 1101 are
Bridge arm signal input part WHIN in the W phases of SPM 1100；The LIN1 ends of HVIC pipes 1101 are SPM
Bridge arm signal input part ULIN under 1100 U phases；The LIN2 ends of HVIC pipes 1101 are bridge arm under the V phases of SPM 1100
Signal input part VLIN；The LIN3 ends of HVIC pipes 1101 are bridge arm signal input part WLIN under the W phases of SPM 1100；
The ITRIP ends of HVIC pipes 1101 are the MTRIP ends of SPM 1100；The PFCINP ends of HVIC pipes 1101 are as intelligent work(
The PFC control signals PFCIN of rate module 100；The GND ends of HVIC pipes 1101 supply as the low-pressure area of SPM 1100
Electric power supply negative terminal COM.Wherein, SPM 1100 the tunnel of UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six input and
PFCIN ends receive 0V or 5V input signal.
One end of the VB1 ends connection electric capacity 1141 of HVIC pipes 1101, and as the U phases higher-pressure region of SPM 1100
Power supply anode UVB；The HO1 ends of HVIC pipes 1101 are connected with the grid of bridge arm IGBT pipes 1121 in U phases；HVIC pipes 1101
VS1 ends and colelctor electrode, the FRD pipes 1114 of bridge arm IGBT pipes 1124 under the emitter-base bandgap grading of IGBT pipes 1121, the anode of FRD pipes 1111, U phases
Negative electrode, the other end of electric capacity 1141 be connected, and as the U phases higher-pressure region power supply negative terminal UVS of SPM 1100.
One end of the VB2 ends connection electric capacity 1132 of HVIC pipes 1101, and as the V phases higher-pressure region of SPM 1100
Power supply anode VVB；The HO2 ends of HVIC pipes 1101 are connected with the grid of bridge arm IGBT pipes 1123 in V phases；HVIC pipes 1101
VS2 ends and colelctor electrode, the FRD pipes 1115 of bridge arm IGBT pipes 1125 under the emitter-base bandgap grading of IGBT pipes 1122, the anode of FRD pipes 1112, V phases
Negative electrode, the other end of electric capacity 1132 be connected, and as the V phases higher-pressure region power supply negative terminal VVS of SPM 1100.
One end of the VB3 ends connection electric capacity 1133 of HVIC pipes 1101, the W phases higher-pressure region as SPM 1100 supplies
Electric power positive end WVB；The HO3 ends of HVIC pipes 1101 are connected with the grid of bridge arm IGBT pipes 1123 in W phases；HVIC pipes 1101
VS3 ends and colelctor electrode, the FRD pipes 1116 of bridge arm IGBT pipes 1126 under the emitter-base bandgap grading of IGBT pipes 1123, the anode of FRD pipes 1113, W phases
Negative electrode, the other end of electric capacity 1133 be connected, and as the W phases higher-pressure region power supply negative terminal WVS of SPM 1100.
The LO1 ends of HVIC pipes 1101 are connected with the grid of IGBT pipes 1124；The LO2 ends of HVIC pipes 1101 and IGBT pipes 1125
Grid be connected；The LO3 ends of HVIC pipes 1101 are connected with the grid of IGBT pipes 1126；The emitter-base bandgap grading of IGBT pipes 1124 is managed with FRD
1114 anode is connected, and as the U phase low reference voltages end UN of SPM 1100；The emitter-base bandgap grading of IGBT pipes 1125 with
The anode of FRD pipes 1115 is connected, and as the V phase low reference voltages end VN of SPM 1100；IGBT pipes 1126 are penetrated
Pole is connected with the anode of FRD pipes 1116, and as the W phase low reference voltages end WN of SPM 1100.
VDD is the power supply anode of HVIC pipes 1101, and GND is the power supply negative terminal of HVIC pipes 1101；VDD-GND voltages
Generally 15V；VB1 and VS1 is respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO1 is the output end of U phases higher-pressure region；
VB2 and VS2 is respectively the positive pole and negative pole of the power supply of V phases higher-pressure region, and HO2 is the output end of V phases higher-pressure region；VB3 and VS3 difference
For the positive pole and negative pole of the power supply of U phases higher-pressure region, HO3 is the output end of W phases higher-pressure region；LO1, LO2, LO3 are respectively U phases, V
The output end of phase, W phase low-pressure areas.
The PFCO ends of HVIC pipes 1101 are connected with the grid of IGBT pipes 1127；The emitter-base bandgap grading of IGBT pipes 1127 and FRD pipes 1117
Anode be connected, and as the PFC low reference voltages end-VP of SPM 1100；The colelctor electrode and FRD of IGBT pipes 1127
Negative electrode, the anode of FRD pipes 1131 of pipe 1117 are connected, and as the PFC ends of SPM 1100；
The colelctor electrode of IGBT pipes 1121, the negative electrode of FRD pipes 1111, the colelctor electrode of IGBT pipes 1122, the moon of FRD pipes 1112
Pole, the colelctor electrode of IGBT pipes 1123, the negative electrode of FRD pipes 1113, the negative electrode of FRD pipes 1131 are connected, and are used as SPM
1100 high voltage input P, P typically meets 300V.
The effect of HVIC pipes 1101 is：
When ICON is high level, the 0 of input HIN1, HIN2, HIN3 or 5V logic input signal are passed to respectively
Output end HO1, HO2, HO3, LIN1, LIN2, LIN3 signal are passed into output end LO1, LO2, LO3 respectively, by PFCINP's
Signal passes to output end PFCO, and wherein HO1 is that VS1 or VS1+15V logic output signal, HO2 are patrolling for VS2 or VS2+15V
Volume output signal, HO3 are VS3 or VS3+15V logic output signal, and LO1, LO2, LO3, PFCO are 0 or 15V logic output
Signal；
When ICON is low level, HO1, HO2, HO3, LO1, LO2, LO3, PFCO are all set to low level.
The effect of adaptive circuit 1105 is：
In the PFCINP of HVIC pipes 1101 rising edge, adaptive circuit 1105 carries out secondary detection to ITRIP signal,
The voltage that detects is higher than a certain particular value for the first time, and when the ITRIP detected for the second time voltage is higher than first time,
ICON exports low level；When the voltage detected for the first time is less than a certain particular value, although or the voltage that detects for the first time it is high
When a certain particular value but the ITRIP voltages that detect for the second time are less than first time, ICON keeps enabled output, the i.e. high electricity of output
It is flat；
After the PFCINP of HVIC pipes 1101 rising edge, the first input end detection one in real time of adaptive circuit 1105
Secondary ITRIP voltage, ICON export high level or low level according to ITRIP voltage swing.
In one embodiment of the invention, the particular circuit configurations schematic diagram of adaptive circuit 1105 is as shown in fig. 6, tool
Body is：
PFCINP connections NOT gate 2001, NOT gate 2003, NOT gate 2011, the input of NOT gate 2013；The output of NOT gate 2001
The input of end connection NOT gate 2002；One end of the output end connection electric capacity 2008 of NOT gate 2003, the input of NOT gate 2004；It is non-
One end of the output end connection electric capacity 2009 of door 2004, the input of NOT gate 2005；Another termination GND of electric capacity 2008；Electric capacity
2009 another termination GND；
One of input of the output termination NAND gate 2006 of NOT gate 2002；The output termination NAND gate of NOT gate 2005
2006 another input；The input of the output end NAND gate 2007 of NAND gate 2006 is connected；The output end of NOT gate 2007
Connect the control terminal of the one of input and analog switch 2027 of NAND gate 2025；
The input of the output end connection NOT gate 2012 of NOT gate 2011；The output end of NOT gate 2013 connects the defeated of NOT gate 2014
Enter end；One end of the output end connection electric capacity 2019 of NOT gate 2014, the input of NOT gate 2015；Another termination of electric capacity 2019
GND；One of input of the output termination NAND gate 2016 of NOT gate 2012；The output termination NAND gate 2016 of NOT gate 2015
Another input；The input of the output end NAND gate 2017 of NAND gate 2016 is connected；The output termination RS of NOT gate 2017
The R ends of trigger 2024；
ITRIP ends and the positive input terminal of voltage comparator 2010, the positive input terminal of voltage comparator 2023, a/d converter
2021 input is connected；The anode of voltage source 2018 is connected with the negative input end of voltage comparator 2010；Voltage source 2018
Negative terminal meets GND；The output end of voltage comparator 2010 and one of input of NAND gate 2025, the 0 of analog switch 2027
Selection end is connected；The output end of a/d converter 2021 is connected with the input of D/A converter 2022；The output of D/A converter 2022
End is connected with the negative input end of voltage comparator 2023；The output end of voltage comparator 2023 and the S ends phase of rest-set flip-flop 2024
Even；The Q ends of rest-set flip-flop 2024 are connected with one of input of NAND gate 2025；
The input of the output end connection NOT gate 2026 of NAND gate 2025；The output end connection analog switch of NOT gate 2026
2027 1 selection end；The input of the fixed termination NOT gate 2020 of analog switch 2027；The output termination ICON of NOT gate 2020.
Illustrate the operation principle and key parameter value of above-described embodiment below：
Because the time-lag action of electric capacity 2019, in the rising edge of PFCINP signal, A points produce a burst pulse；Because
The time-lag action of electric capacity 2008 and electric capacity 2009, in the rising edge of PFCINP signal, B points produce one than A points burst pulse more
Big pulse；
During B point pulses, 1 selection end of analog switch 2027 is connected with the fixing end of analog switch 2027；Otherwise, mould
The 0 selection end for intending switch 2027 is connected with the fixing end of analog switch 2027；
When 0 selection end of analog switch 2027 is connected with the fixing end of analog switch 2027：ITRIP signals and voltage source
2018 voltage V1 compares, and when ITRIP voltages are higher than V1, ICON exports low level, and otherwise ICON exports high level；
When 1 selection end of analog switch 2027 is connected with the fixing end of analog switch 2027：The R ends of rest-set flip-flop 2024
After being resetted by the high level at A ends, NAND gate 2025 exports high level, and after NOT gate 2026 and NOT gate 2020, ICON is initially defeated
Go out high level；
ITIRP voltages are compared with the voltage V1 of voltage comparator 2018：
When ITRIP voltages are less than V1 voltages, NAND gate 2025 exports high level, by NOT gate 2026 and NOT gate 2020
Afterwards, it is constant persistently to export high level by ICON；
When ITRIP voltages are more than V1 voltages, this flashy voltage of ITRIP passes through a/d converter 2021 and D/A converter
After 2022, as the comparison voltage V2 of the negative terminal of voltage comparator 2023, the duration of conversion is designated as T, and ITRIP passes through T time
Voltage V3 afterwards is compared with voltage V2：
When V3 is less than V2, show that ITRIP voltage overshoot is reducing, it may be possible to which noise, voltage comparator 2023 export
Low level, then the low level at the Q ends of rest-set flip-flop 2024 is constant, and NAND gate 2025 exports high level, by NOT gate 2026 and non-
After door 2020, it is constant that ICON persistently exports high level；
When V3 is more than V2, show that in lasting increase, having a good chance for excessively stream, voltage ratio occur for ITRIP voltage overshoot
High level is exported compared with device 2023, the Q ends of rest-set flip-flop 2024 are set to high level, then the three of NAND gate 2025 input is all
For high level, the output end of NAND gate 2025 is low level, after NOT gate 2026 and NOT gate 2020, ICON output low levels.
NOT gate 2013 and NOT gate 2014 can select the minimum dimension that technique allows, the value NAND gate 2013 of NOT gate 2011
Together, the value NAND gate 2014 of NOT gate 2012 is same, and the value of electric capacity 2019 can be 3~5pF, the then burst pulse of A points width
In 100ns or so, it is sufficient to reset rest-set flip-flop 2024；
NOT gate 2003 and NOT gate 2004 can select the minimum dimension that technique allows, the value NAND gate 2003 of NOT gate 2001
Together, the value NAND gate 2004 of NOT gate 2002 is same, and the value of electric capacity 2009 is same with electric capacity 2019, and the value of electric capacity 2008 can be
15~25pF, then for the width of the pulse of B points in 350ns~550ns, whether it is noise to ITRIP voltage that this time is exactly
The time of secondary-confirmation is carried out, if this time is too short, the erroneous judgement probability to ITIRP voltages is larger, if this time
It is long, then can be excessively slow to the promptness of ITIRP voltage responses；
The voltage of voltage source 2018 may be configured as 0.5V, may be alternatively provided as 0.7V, according to the milliohm electricity connect outside ITRIP
Depending on the value of resistance, the value of milliohm resistance that also can be external adapts to the magnitude of voltage of voltage source 2018, usually, voltage source 2018
Voltage it is unsuitable too low, otherwise the probability of false triggering is very high, also unsuitable too high, and otherwise the resistance of outside institute connecting resistance can be very big,
Cause the power requirement to outside milliohm resistance very high, increase system cost；
It is T that total delay of a/d converter 2021 and D/A converter 2022, which was designed in 200~300ns, this time, then
V3 voltages are the voltage at 200~300ns time point after V2 voltages, judge that ITRIP voltages are still big after 200~300ns
In V1 and continue to increase, then the exception of ITRIP voltages increases not because the Reverse recovery of the FRD pipes 1131 of PFCINP controls
Probability is very big caused by time, whereas if judge ITRIP voltages after 200~300ns still above V1 but it is lasting reduce or
ITRIP voltages are less than V1 after 200~300ns, then the exception of ITRIP voltages increases the FRD pipes because PFCINP controls
Probability caused by 1131 reverse recovery time is very big.
From the technical scheme of above-described embodiment, SPM proposed by the present invention and existing SPM
It is completely compatible, directly it can be replaced with existing SPM.In PFCINP high level moments, if ITRIP electricity
Pressure fluctuation is caused because of circuit noise, then ITRIP voltages are a processes persistently reduced, can be filtered by secondary detection
Except the possibility for causing malfunction because of circuit noise；If real excessively stream is come from during ITRIP voltage pulsation, then ITRIP electricity
Pressure is a process continued to increase, and secondary detection exports low level in time after confirming makes SPM of the present invention stop work
Make to form protection.And after PFCINP high level, SPM system of the invention enters ITRIP and routinely judges detection
State, noise suppressed function revocation, the voltage change of pin can be made in time reaction so as to SPM provide and
When protect.
Technical scheme is described in detail above in association with accompanying drawing, the present invention proposes a kind of new intelligent power mould
Block, on the premise of can having high reliability and high-adaptability ensuring SPM, effectively reduce SPM
By the probability of false triggering.
The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the invention, for the skill of this area
For art personnel, the present invention can have various modifications and variations.Within the spirit and principles of the invention, that is made any repaiies
Change, equivalent substitution, improvement etc., should be included in the scope of the protection.
Claims (10)
- A kind of 1. SPM, it is characterised in that including：Bridge arm signal input part under bridge arm signal input part, three-phase on three-phase, three-phase low reference voltage end, current detecting end and PFC control signals；HVIC is managed, and is provided with the HVIC pipes and is respectively connecting on the three-phase bridge under bridge arm signal input part and the three-phase The terminals of arm signal input part, and it is corresponding to the first port at the current detecting end and defeated corresponding to PFC controls Enter the second port at end, the first port is connected by connecting line with the current detecting end, and the second port passes through company Wiring is connected with the PFC control signals；Sampling resistor, the three-phase low reference voltage end and the current detecting end are connected to the first of the sampling resistor End, the second end of the sampling resistor is connected to the low-pressure area power supply negative terminal of the SPM；Adaptive circuit, the power supply positive pole and negative pole of the adaptive circuit are respectively connecting to the SPM Low-pressure area power supply anode and negative terminal, the first input end of the adaptive circuit are connected to the first port, it is described from Second input of adaptive circuit is connected to the second port, and the output end of the adaptive circuit is as the HVIC pipes Enable Pin；Wherein, the adaptive circuit is when the input signal of second input is in rising edge, according to described first The result that the input signal of input is detected twice exports the enable signal of corresponding level；The adaptive circuit is described When the input signal of second input is not in rising edge, one-time detection is carried out according to the input signal to the first input end Result export the enable signal of corresponding level.
- 2. SPM according to claim 1, it is characterised in that：The adaptive circuit is when the input signal of second input is in rising edge, when to the first input end Input signal is detected twice, and the magnitude of voltage detected for the first time is higher than predetermined value, and the magnitude of voltage detected for the second time During higher than first time, the enable signal of the first level is exported, to forbid the HVIC pipes to work；Otherwise, second electrical level is exported Enable signal, to allow the HVIC pipes to work；The adaptive circuit is when the input signal of second input is not in rising edge, when to the first input end Input signal when carrying out the result of one-time detection and be higher than predetermined value for magnitude of voltage, the enable signal of output first level； Otherwise, the enable signal of the second electrical level is exported.
- 3. SPM according to claim 1, it is characterised in that the adaptive circuit includes：First voltage comparator, the positive input terminal of the first voltage comparator input as the first of the adaptive circuit End, the negative input end of the first voltage comparator are connected to the positive pole of voltage source, and the negative pole conduct of the voltage source is described certainly The power supply negative pole of adaptive circuit, the output end of the first voltage comparator are connected to the first choice end of analog switch；The first NOT gate and the second NOT gate being connected in series, the input of first NOT gate as the adaptive circuit second Input, the output end of second NOT gate are connected to the first input end of the first NAND gate；The 3rd NOT gate, the 4th NOT gate and the 5th NOT gate being connected in series, the input of the 3rd NOT gate are connected to described first The input of NOT gate, the output end of the 5th NOT gate are connected to the second input of first NAND gate, described first with The output end of NOT gate is connected to the input of the 6th NOT gate, and the output end of the 6th NOT gate is connected to the control of the analog switch End processed；First electric capacity, it is connected between the input of the 4th NOT gate and the power supply negative pole of the adaptive circuit；Second electric capacity, it is connected between the input of the 5th NOT gate and the power supply negative pole of the adaptive circuit；The 7th NOT gate being connected in series and the 8th NOT gate, the input of the 7th NOT gate are connected to the input of first NOT gate End, the output end of the 8th NOT gate are connected to the first input end of the second NAND gate；The 9th NOT gate, the tenth NOT gate and the 11st NOT gate being connected in series, the input of the 9th NOT gate are connected to described The input of one NOT gate, the output end of the 11st NOT gate are connected to the second input of second NAND gate, and described The output end of two NAND gates is connected to the input of the 12nd NOT gate；3rd electric capacity, it is connected between the input of the 11st NOT gate and the power supply negative pole of the adaptive circuit；Rest-set flip-flop, the R ends of the rest-set flip-flop are connected to the output end of the 12nd NOT gate；The a/d converter and D/A converter being connected in series, the input of the a/d converter are connected to the first voltage comparator The positive input terminal of positive input terminal and second voltage comparator, the output end of the D/A converter are connected to the second voltage and compared The negative input end of device, the output end of the second voltage comparator are connected to the S ends of the rest-set flip-flop；3rd NAND gate, the output end of the 6th NOT gate, the output end of the first voltage comparator and the rest-set flip-flop Q ends be respectively connecting to three inputs of the 3rd NAND gate, the output end of the 3rd NAND gate is connected to the 13rd The input of NOT gate, the output end of the 13rd NOT gate are connected to the second selection end of the analog switch, and the simulation is opened The fixing end of pass is connected to the input of the 14th NOT gate, and the output end of the 14th NOT gate is as the adaptive circuit Output end.
- 4. SPM according to claim 1, it is characterised in that PFC drivings are additionally provided with the HVIC pipes The signal output part of circuit, the SPM also include：First power switch pipe and the first diode, the anode of first diode are connected to first power switch pipe Emitter stage, the negative electrode of first diode are connected to the colelctor electrode of first power switch pipe, first power switch The colelctor electrode of pipe is connected to the anode of the second diode, and the negative electrode of second diode is connected to the SPM High voltage input, the base stage of first power switch pipe are connected to the signal output part of the PFC drive circuits, and described PFC low reference voltage end of the emitter stage of one power switch pipe as the SPM, first power switch pipe PFC end of the colelctor electrode as the SPM.
- 5. SPM according to any one of claim 1 to 4, it is characterised in that also include：Boostrap circuit, The boostrap circuit includes：First bootstrap diode, the anode of first bootstrap diode are connected to the low-pressure area power supply of the SPM Power positive end, the negative electrode of first bootstrap diode are being connected to the U phases higher-pressure region power supply of the SPM just End；Second bootstrap diode, the anode of second bootstrap diode are connected to the low-pressure area power supply of the SPM Power positive end, the negative electrode of second bootstrap diode are being connected to the V phases higher-pressure region power supply of the SPM just End；3rd bootstrap diode, the anode of the 3rd bootstrap diode are connected to the low-pressure area power supply of the SPM Power positive end, the negative electrode of the 3rd bootstrap diode are being connected to the W phases higher-pressure region power supply of the SPM just End.
- 6. SPM according to any one of claim 1 to 4, it is characterised in that also include：Bridge arm circuit on three-phase, the input of bridge arm circuit is connected to described in each phase on the three-phase in bridge arm circuit The signal output part of phase is corresponded in the three-phase high-voltage area of HVIC pipes；Bridge arm circuit under three-phase, the input of bridge arm circuit is connected to described under each phase under the three-phase in bridge arm circuit The signal output part of phase is corresponded in the three-phase low-voltage area of HVIC pipes.
- 7. SPM according to claim 6, it is characterised in that bridge arm circuit includes in each phase：Second power switch pipe and the 3rd diode, the anode of the 3rd diode are connected to second power switch pipe Emitter stage, the negative electrode of the 3rd diode are connected to the colelctor electrode of second power switch pipe, second power switch The colelctor electrode of pipe is connected to the high voltage input of the SPM, and the base stage of second power switch pipe is as institute The input of bridge arm circuit in each phase is stated, the emitter stage of second power switch pipe is connected to the SPM pair Answer the higher-pressure region power supply negative terminal of phase.
- 8. SPM according to claim 7, it is characterised in that bridge arm circuit includes under each phase：3rd power switch pipe and the 4th diode, the anode of the 4th diode are connected to the 3rd power switch pipe Emitter stage, the negative electrode of the 4th diode are connected to the colelctor electrode of the 3rd power switch pipe, the 3rd power switch The colelctor electrode of pipe is connected to the anode of the 3rd diode in corresponding upper bridge arm circuit, the 3rd power switch pipe Input of the base stage as bridge arm circuit under each phase, the emitter stage of the 3rd power switch pipe is as the intelligent work( The low reference voltage end of the corresponding phase of rate module.
- 9. the SPM according to claim 7 or 8, it is characterised in that the high voltage of the SPM The voltage of input is 300V, is connected between the anode and negative terminal of each phase higher-pressure region power supply of the SPM There is filter capacitor.
- A kind of 10. air conditioner, it is characterised in that including：SPM as claimed in any one of claims 1-9 wherein.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510860689.XA CN105356785B (en) | 2015-11-30 | 2015-11-30 | SPM and air conditioner |
| PCT/CN2016/097729 WO2017092448A1 (en) | 2015-11-30 | 2016-08-31 | Intelligent power module and air conditioner |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510860689.XA CN105356785B (en) | 2015-11-30 | 2015-11-30 | SPM and air conditioner |
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| WO2017092448A1 (en) * | 2015-11-30 | 2017-06-08 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
| CN105577016B (en) * | 2016-03-04 | 2017-12-19 | 广东美的制冷设备有限公司 | SPM and air conditioner |
| CN105763090B (en) * | 2016-03-04 | 2018-03-27 | 广东美的制冷设备有限公司 | SPM and air conditioner |
| CN105703657B (en) * | 2016-03-04 | 2018-03-27 | 广东美的制冷设备有限公司 | SPM and air conditioner |
| CN105577018B (en) * | 2016-03-04 | 2017-12-19 | 广东美的制冷设备有限公司 | SPM and air conditioner |
| CN105577020B (en) * | 2016-03-08 | 2018-03-27 | 广东美的制冷设备有限公司 | SPM and air conditioner |
| CN105577019B (en) * | 2016-03-08 | 2018-02-02 | 广东美的制冷设备有限公司 | SPM and air conditioner |
| WO2017206385A1 (en) * | 2016-05-30 | 2017-12-07 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
| CN105871182B (en) * | 2016-05-30 | 2017-10-13 | 广东美的制冷设备有限公司 | SPM and air conditioner |
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| JP2001327171A (en) * | 2000-05-11 | 2001-11-22 | Fuji Electric Co Ltd | Power semiconductor module and high breakdown voltage ic |
| JP2013055739A (en) * | 2011-09-01 | 2013-03-21 | Mitsubishi Electric Corp | Semiconductor device |
| CN103872884A (en) * | 2014-03-24 | 2014-06-18 | 美的集团股份有限公司 | Intelligent power module |
| CN104811078A (en) * | 2015-04-28 | 2015-07-29 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
| CN104821705A (en) * | 2015-04-28 | 2015-08-05 | 广东美的制冷设备有限公司 | Intelligent power module circuit and air-conditioner |
| CN205195591U (en) * | 2015-11-30 | 2016-04-27 | 重庆美的制冷设备有限公司 | Intelligence power module and air conditioner |
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| JP2001327171A (en) * | 2000-05-11 | 2001-11-22 | Fuji Electric Co Ltd | Power semiconductor module and high breakdown voltage ic |
| JP2013055739A (en) * | 2011-09-01 | 2013-03-21 | Mitsubishi Electric Corp | Semiconductor device |
| CN103872884A (en) * | 2014-03-24 | 2014-06-18 | 美的集团股份有限公司 | Intelligent power module |
| CN104811078A (en) * | 2015-04-28 | 2015-07-29 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
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