CN103970699A

CN103970699A - Method for debugging FPGA pre-emphasis equilibrium value

Info

Publication number: CN103970699A
Application number: CN201410225340.4A
Authority: CN
Inventors: 王素华
Original assignee: Inspur Electronic Information Industry Co Ltd
Current assignee: Inspur Electronic Information Industry Co Ltd
Priority date: 2014-05-23
Filing date: 2014-05-23
Publication date: 2014-08-06

Abstract

The invention discloses a method for debugging an FPGA pre-emphasis equilibrium value. In the FPGA development and design stage, an FPGA verification panel is designed, novel high-speed interconnection buses are adopted between an in-panel processor and an FPGA, a processor panel is connected with an FPGA panel in an orthogonal mode, a panel edge is provided with an S parameter test port of an interconnection transmission channel, a real interconnection parameter is obtained, an S parameter of the channel is tested through a network analysis instrument, pre-emphasis prediction is carried out on the S parameter of the channel through an error rate analysis instrument, the best pre-emphasis value of the parameter is obtained in a traveling mode, pre-emphasis at one end is fixed, and then a CTLE value of a receiving end is determined. The method is good for design of the FPGA verification panel and debugging of the pre-emphasis equilibrium value, and is a test method based on an actual link. Pre-emphasis equilibrium arrangement of the channel is achieved on the basis of real tests.

Description

The method of a kind of FPGA Debugging pre-emphasis equilibrium

Technical field

The present invention relates to electronic applications, chip design and emulation testing field, be specifically related to the method for a kind of FPGA Debugging pre-emphasis equilibrium.

Technical background

Along with the raising of signal rate, signal quality signal effectively in transmission shared position more and more important.For unavoidable reflection in signals transmission and the dielectric loss that increases along with increase frequency, the distorted signals problem that transmission line loss brings, becomes the thorny problem that high speed serialization link and chip design must be faced.

Along with the transmission speed of signal is more and more faster, system is to 25G future development.And high speed serialization link transmits the frequency dependence that maximum obstacle is interconnecting channels loss, along with increase frequency, loss also increases, and signal is correctly transferred to receiving end becomes a kind of challenge.So need to strengthen signal transmission capabilities by equilibrating mechanism.

Now general conventional high-speed serial bus has PCIE, QPI, and SATA, SAS, QDR, FDR etc., signal rate is up to more than 14Ghz.Chip interconnects by PCB transmission line, the conductor losses that has reflection on transmission path and increase along with frequency, the rising edge that dielectric loss is brought is degenerated and amplitude reduces, if such signal arrives receiving end, receiver can not correctly recover, and must cause distorted signals.So need transmitting and receiving terminal necessarily to process signal, strengthen signal transmission capabilities.Current high-speed serial bus all can do pre-emphasis at transmitting terminal, and receiving end does equilibrating mechanism, improves signal transmission capabilities.

Need to be in the IO of chip partial design transmitting terminal pre-emphasis in the time of design chips, receiving end equilibrating mechanism leaves surplus as much as possible to unavoidable loss in design on board level as far as possible.Carry out emulation testing so need to research and develop the FPGA stage by the initial stage, understand the ability of equalization in chip real work, to give the PCB of the chip application producer rule of design when later stage flow, allow it understand the driving force of chip, give design on board level and leave great design margin.

Summary of the invention

The technical problem to be solved in the present invention is: the method that the equilibrium of a kind of FPGA Debugging pre-emphasis is provided.

The technical solution adopted in the present invention is:

The method of a kind of FPGA Debugging pre-emphasis equilibrium, in the research and development design FPGA stage, design FPGA witness plate, plate inner treater is between FPGA, adopt novel high speed interconnection, processor plate adopts orthogonal manner to connect with FPGA plate, edges of boards need arrange the S parameter testing interface of interconnected transmission channel, obtain real interconnected parameter, record the S parameter of passage by network analyzer, by Bit Error Rate Analyzer, this passage S parameter is carried out to the prediction of pre-emphasis, travel through out the best pre-emphasis value for this parameter, the pre-emphasis of fixing one end, determine again the CTLE value of receiving end.

The balanced setting of the pre-emphasis of passage all draws based on authentic testing in the situation that like this.

Described interconnection is a kind of novel high-speed serial bus, and bus transfer rate is 8Gbps.

Processor is with interconnected by straddle between FPGA, and PCB transmission length is 15inch, and path is through the via hole under a high speed orthogonal connector and two BGA, and total loss is about 8.5dB.

In the time of design FPGA plate, copy interconnected between real cabling situation at edges of boards design test link.

Note: FPGA(Field-Programmable Gate Array), i.e. field programmable gate array, it is the product further developing on the basis of the programming devices such as PAL, GAL, CPLD.It occurs as a kind of semi-custom circuit in special IC (ASIC) field, has both solved the deficiency of custom circuit, has overcome again the limited shortcoming of original programming device gate circuit number.

Beneficial effect of the present invention is:

The present invention is a kind of adjustment method of the pre-emphasis balance parameters based on actual measurement.Along with the raising of signal rate, signal quality signal effectively in transmission shared position more and more important.For unavoidable reflection in signals transmission and the dielectric loss that increases along with increase frequency, the distorted signals problem that transmission line loss brings, becomes the thorny problem that high speed serialization link and chip design must be faced.Need to be in the IO of chip partial design transmitting terminal pre-emphasis in the time of design chips, receiving end equilibrating mechanism leaves surplus as much as possible to unavoidable loss in design on board level as far as possible.Carry out emulation testing so need to research and develop the FPGA stage by the initial stage, understand the ability of equalization in chip real work, to give the PCB of the chip application producer rule of design when later stage flow, allow it understand the driving force of chip, give design on board level and leave great design margin.

Method of the present invention is design FPGA witness plate, and the good method of debugging pre-emphasis equilibrium value, is based on physical link method of testing.The balanced setting of the pre-emphasis of passage all draws based on authentic testing in the situation that like this.

Brief description of the drawings

Fig. 1 is bus topolopy figure of the present invention;

Fig. 2 is mutual relationship between pre-emphasis equilibrium of the present invention;

Fig. 3 is that Error Detector travels through based on physical link S parameter, compensation channels loss.

Embodiment

With reference to the accompanying drawings, by embodiment, the present invention is further described:

In the research and development design FPGA stage, need design FPGA witness plate.Bus topology is interconnected between processor and FPGA, interconnection is a kind of novel high-speed serial bus, bus transfer rate is that 8Gbps. processor is with interconnected by straddle between FPGA, PCB transmission length is 15inch, path is through the via hole under a high speed orthogonal connector and two BGA, total loss is about 8.5dB, and link topology as shown in Figure 1.

Taking FPGA as transmitting terminal, processor is that receiving end is example.FPGA holds TXLE, processor end CTLE, and between DFE and passage, topological relation is as shown in Figure 2.

It is that end is three rank pre-emphasis that FPGA sends, and regulates PRE-COURE and POST-COURE value to have thousands of combinations, cannot manually attempt regulating, and does parameter traversal variant with physical link after all by software emulation.So invention is a kind of for the comparatively simple and easy method accurately of the balanced debugging of FPGA link pre-emphasis.

In the time of design FPGA plate, copy interconnected between real cabling situation at edges of boards design test link, use the S parameter of network analyzer test interacted system.The S parameter that this test is obtained imports in Bit Error Rate Analyzer, Bit Error Rate Analyzer can, based on this passage S parameter, carry out the traversal of FPGA pre-emphasis, draws so a more objective pre-emphasis value, as shown in Figure 3, interconnected frequency dependence is effectively compensated.

Determine the pre-emphasis of transmitting terminal, then adjusted the value of the CTLE of receiving end.Connect oscillograph by receiving end, adjust the value of CTLE, little because be worth range of choice for this reason, can judge which value is more suitable by experience, in the time there is comparatively desirable eye pattern in oscillograph, just can determine this group TXLE, CTLE is the best of breed based under this link with adaptive DFE, obtains passage optimum reception eye pattern.

The close passage in UNICOM path can arrange unified TXLE, and CTLE value, for the larger path of gap, continues to find in this way pre-emphasis, equilibrium value.

This kind of method is design FPGA witness plate, and the good method of debugging pre-emphasis equilibrium value, is based on physical link method of testing.

Claims

1. the method for FPGA Debugging pre-emphasis equilibrium, it is characterized in that: in the research and development design FPGA stage, design FPGA witness plate, plate inner treater is between FPGA, adopt novel high speed interconnection, processor plate adopts orthogonal manner to connect with FPGA plate, edges of boards arrange the S parameter testing interface of interconnected transmission channel, obtain real interconnected parameter, record the S parameter of passage by network analyzer, by Bit Error Rate Analyzer, this passage S parameter is carried out to the prediction of pre-emphasis, travel through out the best pre-emphasis value for this parameter, the pre-emphasis of fixing one end, determine again the CTLE value of receiving end.

2. the method for a kind of FPGA Debugging pre-emphasis according to claim 1 equilibrium, is characterized in that: described interconnection is a kind of novel high-speed serial bus, and bus transfer rate is 8Gbps.

3. the method for a kind of FPGA Debugging pre-emphasis according to claim 1 equilibrium, it is characterized in that: processor is with interconnected by straddle between FPGA, PCB transmission length is 15inch, and path is through the via hole under a high speed orthogonal connector and two BGA, and total loss is about 8.5dB.

4. the method for a kind of FPGA Debugging pre-emphasis according to claim 1 equilibrium, is characterized in that: in the time of design FPGA plate, copy interconnected between real cabling situation at edges of boards design test link.