CN112187695B - FPGA channel pre-emphasis and equalization method and system based on OFDM high-speed logging telemetry system - Google Patents

FPGA channel pre-emphasis and equalization method and system based on OFDM high-speed logging telemetry system Download PDF

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CN112187695B
CN112187695B CN202011054423.3A CN202011054423A CN112187695B CN 112187695 B CN112187695 B CN 112187695B CN 202011054423 A CN202011054423 A CN 202011054423A CN 112187695 B CN112187695 B CN 112187695B
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赵弘炜
宋克柱
吴传
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University of Science and Technology of China USTC
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2628—Inverse Fourier transform modulators, e.g. inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
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    • H04L27/265—Fourier transform demodulators, e.g. fast Fourier transform [FFT] or discrete Fourier transform [DFT] demodulators
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2647—Arrangements specific to the receiver only
    • H04L27/2655—Synchronisation arrangements
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Abstract

The invention relates to an FPGA channel pre-emphasis and equalization method and system based on an OFDM high-speed logging telemetry system.A ground communication board sends a training sequence A to an underground communication board, the underground communication board FPGA utilizes M repeated short training sequences in A to carry out data synchronization, and utilizes N repeated long training sequences in A to train an LMS time domain equalizer; carrying out OFDM modulation of 4QAM on data of an Nth sequence of the N repeated long training sequences after passing through a time domain equalizer by using a specific channel and sending the data to a ground communication board; the ground communication board FPGA carries out fast Fourier transform on the Nth equalized long training sequence data to obtain pre-emphasis coefficients of all sub-channels, a new long training sequence E is obtained through calculation according to the obtained pre-emphasis coefficients of all sub-channels, and a training sequence B is sent to the underground end communication board FPGA; and the FPGA of the underground communication board performs data synchronization by using M repeated short training sequences in B, performs equalization on N repeated long training sequences E in B by using a time domain equalizer obtained by previous training, performs fast Fourier transform, calculates frequency domain equalization coefficients of each subchannel, and completes pre-emphasis and equalization on the channel.

Description

FPGA channel pre-emphasis and equalization method and system based on OFDM high-speed logging telemetry system
Technical Field
The invention relates to an FPGA channel pre-emphasis and equalization method and system based on an OFDM high-speed logging telemetry system, and belongs to the field of deep ground exploration.
Background
The underground data transmission system in deep ground exploration is composed of a transmission system between underground acquisition arrays and a logging telemetry system between underground acquisition equipment and a ground control center, wherein the performance of the logging telemetry system determines the performance of the whole underground data transmission system. The logging telemetry system mainly has the functions of transmitting underground data acquired by the logging acquisition system to a ground control center through transmission media such as slurry, cables, optical fibers, cables and the like, and transmitting instructions of the ground control center to the logging acquisition system. The speed of the transmission speed of the logging telemetry system is an important index for measuring the performance of logging equipment.
Most of cables adopted in the existing logging system are seven-core cables, the length of the cables is generally 3000-7000m, the working frequency range is narrow, the attenuation on high-frequency signals is large and is generally between 0 and 300kHz, the system cannot transmit information by using carrier waves with higher frequencies, and the improvement of the transmission speed becomes a bottleneck. At present, three logging companies in the world all have respective developed advanced core technologies, wherein the MAXI-500 system of the Schlumberger company adopts the QAM modulation and demodulation technology, so that the uplink data transmission rate of the system can reach 5 OOkbit/s; an ECLIPS-5700 logging system of the Alterlas company adopts Manchester coding technology, so that the transmission rate of uplink data of the system can reach 23 Okbit/s; the LOG-IQ logging technology of Hardbergton in America uses ADSL and DMT modulation technology, and the uplink data transmission rate can reach 800kbit/s, which represents the most advanced logging technology level in the world. However, the imaging logging technology in China starts late, most companies still carry out resource exploitation work by purchasing foreign equipment at present, and certain gap exists between the imaging logging technology and the foreign advanced logging technology.
The underground signals can be quickly, efficiently and timely transmitted to the ground through the logging cable, and the method is the key point and the direction of the research in academic circles and society at home and abroad. The speed of cable transmission becomes the bottleneck of efficiency improvement, and aiming at the physical characteristics of the cable, the attenuation characteristics of the cable can be compensated through an advanced equalization technology and a pre-emphasis technology, distorted signals are recovered, and intersymbol interference of a system is reduced. Therefore, it is important to design an efficient and stable channel pre-emphasis and equalization method.
With the continuous deepening of the logging depth in the deep resource exploration and the continuous increase of the data volume, the problem that the available frequency band is narrow, especially the attenuation of high-frequency signals is large, in the logging telemetry system becomes more and more severe.
Disclosure of Invention
The invention solves the problems: the method and the system overcome the defects of the prior art, provide the FPGA channel pre-emphasis and equalization method and the system based on the OFDM high-speed logging telemetry system, solve the problems of narrow available frequency band and especially large high-frequency signal attenuation in the logging telemetry system, and jointly adopt the pre-emphasis, time domain equalization, frequency domain equalization and other methods to compensate the channel. Compared with the method that the original signals can be better recovered only by balancing at the receiving end, the method is simple and efficient, the underground communication board can adopt the FPGA with lower power consumption, and the pressure of power supply and heat dissipation is relieved.
In order to solve the problems, the invention provides an FPGA channel pre-emphasis and equalization method based on an OFDM high-speed logging telemetry system, which realizes the pre-emphasis and equalization of a channel by utilizing a field programmable logic array FPGA and comprises the following steps:
(1) and the ground communication board sends a training sequence A to the underground communication board, wherein the training sequence A comprises M repeated short training sequences C with the length of P and N repeated long training sequences D with the length of Q. Wherein M is more than or equal to 10, N is more than or equal to 3, P is Q/4, and Q is the number of fast Fourier transform points required by OFDM modulation in the OFDM telemetry system, and the method specifically comprises the following steps:
step 1.1: the ground communication board FPGA stores a conjugate random sequence x with the length of Q and composed of 0,1 and-1 in a ROM1,x2,x3…xQPerforming a fast inverse Fourier transform, wherein only x1And xQ/2Is 0, and the rest is 1 or-1, to obtain the long training sequence D.
And 1.2, repeatedly sending M short training sequences C stored in the ROM by the FPGA of the ground communication board, repeatedly sending N long training sequences D obtained in the step 1.1 to the digital-to-analog conversion circuit and the driving circuit of the ground communication board, and sending the long training sequences D to the underground communication board through the logging cable.
(2) And the FPGA of the underground communication board utilizes M repeated short training sequences to carry out data synchronization, utilizes N repeated long training sequences and adopts a variable-step LMS algorithm to adjust the tap coefficient of the time domain equalizer. The method specifically comprises the following steps:
step 2.1: and the analog-to-digital conversion circuit of the underground communication board converts the analog signals on the logging cable into digital signals and sends the digital signals to the FPGA.
Step 2.2: the FPGA sends the received signals to a P +1 stage shift register, and the data in each stage of shift register is a0,a2,a3…aP。
Step 2.3: computing energy sum in P +1 stage shift register data window in k clock period
Figure BDA0002710514680000021
Step 2.4: while calculating the correlation energy as a0aPSending the data into another P +1 stage shift register, wherein the data in each stage of shift register is c0,c2,c3…cP。
Step 2.5: calculating the sum of the correlation energies as E2(k)＝E2(k-1)+c0(k)-cP(k) A 1 is mixing E1(k) Delaying P +1 cycle later with E2(k) And (5) synchronously outputting.
Step 2.6: when E is1(k)＞T1And E2(k)/E1(k)＞T2And when lasting M times P clock cycles, representing that M short training sequences arrive, and sending the last N long training sequences following the short training sequences into an LMS time domain equalizer module, T1And T2Less than ideal E1(k) And E2(k)/E1(k) And equal to or greater than half of them.
Step 2.7: the LMS time domain equalizer is of 17 stages, an ideal long training sequence d '(k) is read from a downhole communication board ROM while the received long training sequence d' (k) is input, and the received long training sequences are respectively r 'in 17 stages of shift registers in the equalizer'1,r'2,r'3…r'17；
Step 2.8: the output of the LMS time-domain equalizer is
Figure BDA0002710514680000031
Updating the weight vector W at the k-th clock cycleg(k) The formula is Wg(k)＝Wg(k-1)+μ(y(k)-d(k))rg' (k). At 1 st lengthInput of training sequence mu 2-10After N-2 long training sequences are input, mu is 2-14And mu multiplication is realized by data shift.
Step 2.9: the LMS time-domain equalizer fixes the weight vector W after inputting N-1 repeated long training sequencesg(k) And outputting data after the weight vector is fixed and the Nth long training sequence is equalized, and completing the training of the LMS time domain equalizer.
(3) And the data of the Nth sequence of the N repeated long training sequences after passing through the time domain equalizer is subjected to 4QAM OFDM modulation by using a specific channel and sent to the ground communication board by the FPGA. The method specifically comprises the following steps:
step 3.1: and the underground communication board FPGA carries out 4QAM constellation coding on the Nth equalized long training sequence output by the LMS time domain equalizer.
Step 3.2: and the underground communication board FPGA carries out OFDM modulation on the coded data by using a specific sub-channel with the frequency less than 50kHz, sends the coded data to the digital-to-analog conversion circuit and the driving circuit of the underground communication board, and sends the coded data to the ground communication board through the logging cable.
(4) And the ground communication board FPGA performs fast Fourier transform on the received Nth equalized long training sequence data and obtains pre-emphasis coefficients of all sub-channels. The method specifically comprises the following steps:
step 4.1: and the analog-to-digital conversion circuit of the ground communication board converts the analog signals on the logging cable into digital signals and sends the digital signals to the FPGA.
Step 4.2: and the ground communication board FPGA carries out OFDM demodulation and 4QAM constellation inverse coding on the signal to obtain the data of the Nth equalized long training sequence sent by the underground communication board.
Step 4.3: the ground communication board FPGA carries out fast Fourier transform on the Nth equalized long training sequence data to obtain e1,e2,e3…eQ。
Step 4.4: calculating to obtain pre-emphasis coefficients of each sub-channel as
Figure BDA0002710514680000032
(5) And (4) calculating by the FPGA according to the pre-emphasis coefficients of the sub-channels obtained in the step (4) to obtain a new long training sequence E. And sending a training sequence B to the downhole end communication board, wherein the training sequence B comprises M repeated short training sequences C and N repeated long training sequences E. The method specifically comprises the following steps:
step 5.1: calculating the conjugate random sequence x in step 1.1 after pre-emphasis according to the pre-emphasis coefficient obtained in step 4.41,x2,x3…xQTo obtain
Figure BDA0002710514680000041
Step 5.2: to pair
Figure BDA0002710514680000042
And performing fast inverse Fourier transform to obtain a new long training sequence E.
Step 5.3: and the ground communication board FPGA repeatedly sends M short training sequences C stored in the ROM, then repeatedly sends N long training sequences E obtained in the step 5.2 to the digital-to-analog conversion circuit and the driving circuit of the ground communication board, and sends the long training sequences E to the underground communication board through the logging cable.
(6) And (3) carrying out data synchronization by using M repeated short training sequences by the FPGA, balancing N repeated long training sequences by using the time domain equalizer obtained in the step (2), carrying out fast Fourier transform, calculating frequency domain balancing coefficients of each sub-channel, and completing pre-emphasis and balancing of the channel. The method specifically comprises the following steps:
step 6.1: and (3) carrying out data synchronization on the underground communication board in the same manner as the steps 2.1-2.6, and sending the N long training sequences to an LMS time domain equalizer module in the FPGA.
Step 6.2: the LMS time domain equalizer module uses the weight vector W obtained in step 2.9g(k) And performing time domain equalization on the N long training sequences.
Step 6.3: the FPGA of the underground communication board performs fast Fourier transform on the N long training sequences, and averages the N transformed results to obtain h1,h2,h3…hQ。
Step 6.4: the frequency domain equalization coefficient of each sub-channel obtained by FPGA calculation of the underground communication board is
Figure BDA0002710514680000043
And pre-emphasis and equalization of the channel are completed.
The invention relates to an FPGA channel preemphasis and equalization system based on an OFDM high-speed logging telemetry system, which comprises the following components: an aboveground communication board and a downhole communication board;
the ground communication board and the underground communication board are connected through a logging cable;
the ground communication board includes: the device comprises an FPGA, an ADC, a DAC, a driving circuit and a receiving circuit;
the downhole communication board includes: the device comprises an FPGA, an ADC, a DAC, a driving circuit and a receiving circuit;
the FPGA is used for signal synchronization, time domain equalization, frequency domain equalization, pre-emphasis and calculation of response parameters; the DAC inputs digital signals from the FPGA, converts the digital signals into analog signals, outputs the analog signals to the driving circuit for amplification, and transmits the analog signals to the underground/aboveground communication board through the logging cable by the aboveground/underground communication board; the receiving circuit amplifies the signals transmitted to the underground/underground communication board by the underground/underground communication board, filters the signals and sends the signals into the ADC, and the analog signals are converted into digital signals and then output to the FPGA for processing;
the ground communication board FPGA and the underground communication board FPGA comprise: the device comprises a long training sequence ROM module, a short training sequence ROM module, a Fourier transform module, an inverse Fourier transform module, an LMS time domain equalizer module, a pre-emphasis module, a frequency domain equalization module, a synchronization module and respective control logic modules;
the long training sequence ROM module is used for storing a conjugate random sequence required by generating a long training sequence; the short training sequence ROM module is used for storing a short training sequence; the Fourier transform module is used for converting the time domain signal on the cable into a frequency domain signal so as to calculate the parameters of the pre-emphasis module and the frequency domain equalization module; the inverse Fourier transform module is used for generating a long training sequence and converting the frequency domain signal into a time domain signal; the LMS time domain equalizer module is used for carrying out time domain equalization at a receiving end; the pre-emphasis module is used for carrying out frequency domain equalization at a sending end; the frequency domain equalization module is used for carrying out frequency domain equalization at a receiving end; the synchronization module is used for identifying the received signals and synchronizing data; the control logic module of the ground communication board FPGA is used for calculating pre-emphasis coefficients and controlling the ground communication board ADC and DAC; and the control logic module of the underground communication board FPGA is used for calculating the weight vector and the frequency domain equalization coefficient of the LMS time domain equalizer module and controlling the ADC and the DAC of the underground communication board.
Compared with the prior art, the invention has the advantages that:
(1) the invention adopts the mode of combining pre-emphasis, time domain equalization and frequency domain equalization to compensate the attenuation of the high-frequency part of the signal caused by the channel reason, and can more truly restore the original signal when the attenuation of the high-frequency part of the signal is larger compared with the method only using single equalization or pre-emphasis.
(2) Compared with an aboveground communication board FPGA, the underground communication board FPGA only bears smaller calculation tasks, for example, in the step (3), the underground communication board FGPA does not further calculate the long training sequence after time domain equalization, but sends the long training sequence to the aboveground communication board FGPA to calculate the pre-emphasis coefficient, the requirement of the underground communication board FPGA on logic resources is reduced, the underground communication board FPGA can adopt a low-power-consumption model, and the pressure of power supply and heat dissipation of an underground part is relieved.
(3) The invention only uses the FPGA to carry out channel training, optimizes the calculation method according to the hardware characteristics, has the characteristics of simplicity and high efficiency, and has good application prospect in a logging telemetry system.
Drawings
FIG. 1 is a block diagram of a channel training process of the present invention;
FIG. 2 is a block diagram of the structure of an OFDM logging telemetry system;
FIG. 3 is a block diagram of the internal logic circuit of the FPGA;
FIG. 4 is a graph comparing the performance of the method of the present invention with that of the conventional method.
Detailed Description
The following sections will further describe embodiments of the present invention with reference to the accompanying drawings and specific workflow.
FIG. 2 is a block diagram of an OFDM logging telemetry system according to an embodiment of the invention. The underground communication cable consists of an aboveground communication board and an underground communication board which are connected through a logging cable.
The ground communication board comprises an FPGA, an ADC, a DAC, a driving circuit and a receiving circuit; the underground communication board comprises an FPGA, an ADC, a DAC, a driving circuit and a receiving circuit.
The FPGA is used for signal synchronization, time domain equalization, frequency domain equalization, pre-emphasis and calculation of response parameters; and the DAC inputs digital signals from the FPGA, converts the digital signals into analog signals, outputs the analog signals to the driving circuit for amplification, and transmits the analog signals to the underground/aboveground communication board through the logging cable by the aboveground/underground communication board. The receiving circuit amplifies the signals transmitted to the underground/underground communication board by the underground/underground communication board, filters the signals and sends the signals into the ADC, and the analog signals are converted into digital signals and then output to the FPGA for processing.
The FPGA of the ground communication board and the FPGA of the underground communication board comprise a long training sequence ROM module, a short training sequence ROM module, a Fourier transform module, an inverse Fourier transform module, an LMS time domain equalizer module, a pre-emphasis module, a frequency domain equalization module, a synchronization module and respective control logic modules, wherein the connection relation among the modules is shown in figure 4.
The long training sequence ROM module is used for storing a conjugate random sequence required by generating a long training sequence; the short training sequence ROM module is used for storing a short training sequence; the Fourier transform module is used for converting the time domain signal on the cable into a frequency domain signal so as to calculate the parameters of the pre-emphasis module and the frequency domain equalization module; the inverse Fourier transform module is used for generating a long training sequence and converting the frequency domain signal into a time domain signal; the LMS time domain equalizer module is used for carrying out time domain equalization at a receiving end; the pre-emphasis module is used for carrying out frequency domain equalization at a sending end; the frequency domain equalization module is used for carrying out frequency domain equalization at a receiving end; the synchronization module is used for identifying the received signals and synchronizing data; the control logic module of the ground communication board FPGA is used for calculating pre-emphasis coefficients and controlling the ground communication board ADC and DAC; and the control logic module of the underground communication board FPGA is used for calculating the weight vector and the frequency domain equalization coefficient of the LMS time domain equalizer module and controlling the ADC and the DAC of the underground communication board.
The FPGA adopted by the embodiment of the invention is Cyclone10, the logging cable adopts a 7km armored cable, the number of fast Fourier transform points during OFDM modulation is 512, and the frequency band used for communication is 1-256 kHz.
As shown in fig. 1, after the surface and downhole communication boards are powered on, the channel training phase is entered, which includes the following steps:
(1) the method comprises the following steps that the ground communication board sends a training sequence A to the downhole communication board, wherein the training sequence A comprises 10 repeated short training sequences C with the length of 128 and 3 repeated long training sequences D with the length of 512, and the method specifically comprises the following steps:
step 1.1: the ground communication board FPGA stores a conjugate random sequence x consisting of 0,1 and-1 with the length of 512 in the ROM1,x2,x3…x512Performing a fast inverse Fourier transform, wherein only x1And x256Is 0, and the rest is 1 or-1, to obtain the long training sequence D.
And 1.2, repeatedly sending 10 short training sequences C stored in the ROM by the FPGA, then repeatedly sending 3 long training sequences D obtained in the step 1.1 to the digital-to-analog conversion circuit and the driving circuit of the ground communication board, and sending the long training sequences D to the underground communication board through the logging cable.
(2) The underground communication board FPGA utilizes 10 repeated short training sequences to carry out data synchronization, utilizes 2 repeated long training sequences and adopts a variable step LMS algorithm to adjust the tap coefficient of the time domain equalizer. The method specifically comprises the following steps:
step 2.1: and the analog-to-digital conversion circuit of the underground communication board converts the analog signals on the logging cable into digital signals and sends the digital signals to the FPGA.
Step 2.2: the FPGA sends the received signals to 129-stage shift registers, and the data in each stage of shift register is a0,a2,a3…a128。
Step 2.3: energy sum in 129-stage shift register data window is calculated in k clock period
Figure BDA0002710514680000071
Step 2.4: while calculating the correlation energy as a0a128Sending the data into another 129 stages of shift registers, wherein the data in each stage of shift register is c0,c2,c3…c128。
Step 2.5: calculating the sum of the correlation energies as E2(k)＝E2(k-1)+c0(k)-c128(k) A 1 is mixing E1(k) Delayed for 129 cycles and E2(k) And (5) synchronously outputting.
Step 2.6: when E is1(k)＞T1And E2(k)/E1(k)＞T2And lasting 10 × 128 clock cycles, it represents that 10 short training sequences arrive, and sends the last 2 long training sequences following the short training sequence to the LMS time domain equalizer module.
Step 2.7: the LMS time domain equalizer is of 17 stages, an ideal long training sequence d '(k) is read from a downhole communication board ROM while the received long training sequence d' (k) is input, and the received long training sequences are respectively r 'in 17 stages of shift registers in the equalizer'1,r'2,r'3…r'17。
Step 2.8: the output of the LMS time-domain equalizer is
Figure BDA0002710514680000072
Updating the weight vector W at the k-th clock cycleg(k) The formula is Wg(k)＝Wg(k-1)+μ(y(k)-d(k))rg' (k). When inputting the 1 st long training sequence, mu is 2-10When inputting the 2 nd long training sequence, mu is 2-14And mu multiplication is realized by data shift.
Step 2.9: the LMS time-domain equalizer fixes the weight vector W after inputting N-1 repeated long training sequencesg(k) And outputting data after the weight vector is fixed and the Nth long training sequence is equalized, and completing the training of the LMS time domain equalizer.
(3) And the underground communication board FPGA carries out 4QAM OFDM modulation on the data of the 3 rd sequence of the 3 repeated long training sequences after passing through the time domain equalizer by using a specific channel and sends the data to the ground communication board. The method specifically comprises the following steps:
step 3.1: and the underground communication board FPGA carries out 4QAM constellation coding on the 3 rd equalized long training sequence output by the LMS time domain equalizer.
Step 3.2: and the underground communication board FPGA carries out OFDM modulation on the coded data by using a specific sub-channel of 10-20kHz, sends the coded data to the digital-to-analog conversion circuit and the driving circuit of the underground communication board, and sends the coded data to the ground communication board through the logging cable.
(4) And the ground communication board FPGA performs fast Fourier transform on the received data of the 3 rd equalized long training sequence, and obtains pre-emphasis coefficients of all sub-channels. The method specifically comprises the following steps:
step 4.1: and the analog-to-digital conversion circuit of the ground communication board converts the analog signals on the logging cable into digital signals and sends the digital signals to the FPGA.
Step 4.2: and the ground communication board FPGA carries out OFDM demodulation and 4QAM constellation inverse coding on the signal to obtain the data of the 3 rd balanced long training sequence sent by the underground communication board.
Step 4.3: the FPGA carries out fast Fourier transform on the data of the 3 rd equalized long training sequence to obtain e1,e2,e3…e512。
Step 4.4: calculating to obtain pre-emphasis coefficients of each sub-channel as
Figure BDA0002710514680000081
(5) And (4) calculating by the FPGA according to the pre-emphasis coefficients of the sub-channels obtained in the step (4) to obtain a new long training sequence E. And sending a training sequence B to the downhole end communication board, wherein the training sequence B comprises 10 repeated short training sequences C and 3 repeated long training sequences E. The method specifically comprises the following steps:
step 5.1: calculating the conjugate random sequence x in step 1.1 after pre-emphasis according to the pre-emphasis coefficient obtained in step 4.41,x2,x3…x512To obtain
Figure BDA0002710514680000082
Step 5.2: to pair
Figure BDA0002710514680000083
And performing fast inverse Fourier transform to obtain a new long training sequence E.
Step 5.3: and the ground communication board FPGA repeatedly sends 10 short training sequences C stored in the ROM, then repeatedly sends 3 long training sequences E obtained in the step 5.2 to the digital-to-analog conversion circuit and the driving circuit of the ground communication board, and sends the long training sequences E to the underground communication board through the logging cable.
(6) And (3) carrying out data synchronization by using M repeated short training sequences by the FPGA, balancing the 3 repeated long training sequences by using the time domain equalizer obtained in the step (2), carrying out fast Fourier transform, calculating frequency domain balancing coefficients of each sub-channel, and completing pre-emphasis and balancing of the channel. The method specifically comprises the following steps:
step 6.1: and (3) carrying out data synchronization on the underground communication board in the same manner as the steps 2.1-2.6, and sending the N long training sequences to an LMS time domain equalizer module in the FPGA.
Step 6.2: the LMS time domain equalizer module uses the weight vector W obtained in step 2.9g(k) Time domain equalization is performed on the 3 long training sequences.
Step 6.3: the FPGA of the underground communication board performs fast Fourier transform on the 3 long training sequences, and averages the results after the 3 transforms to obtain h1,h2,h3…h512。
Step 6.4: the frequency domain equalization coefficient of each sub-channel obtained by FPGA calculation of the underground communication board is
Figure BDA0002710514680000091
And pre-emphasis and equalization of the channel are completed.
After the channel training is finished, the ground and underground communication boards exchange pre-emphasis and equalization coefficients through OFDM modulation by using 10-20kHz sub-channels, and enter a data transmission stage.
In the transmission stage, both the data sending end and the receiving end can be ground or underground communication boards. When the data transmitting end carries out OFDM modulation, each sub-channel data is multiplied by a corresponding pre-emphasis coefficient, and then OFDM modulation is carried out. After receiving the signal, the data receiving end performs time domain equalization by the LMS time domain equalizer obtained by training, and after OFDM demodulation, multiplies each subchannel data by the corresponding frequency domain equalization coefficient, thereby well restoring the original signal.
Under the condition of the example, the performance of the method is compared with that of the traditional method only performing time domain equalization, for example, as shown in fig. 4, when a signal transmitted by a transmitting end reaches through a 7km armored cable, the signal at 250kHz is attenuated to nearly 30dB compared with the original signal, although the traditional method only performing time domain equalization compensates for a high-frequency signal to a certain extent, the attenuation is still 15dB, but the method not only reduces the attenuation to less than 2.5dB, but also has flatter response on the whole frequency band, and is more suitable for signal transmission.
The present invention is not limited to the above embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. An FPGA channel preemphasis and equalization method based on an OFDM high-speed logging telemetry system is characterized in that: the method for realizing the pre-emphasis and equalization of the channel by utilizing the field programmable logic array FPGA comprises the following steps:
(1) the method comprises the steps that an overground communication board sends a training sequence A to an underground communication board, wherein the training sequence A comprises M repeated short training sequences C with the length of P and N repeated long training sequences D with the length of Q, M is more than or equal to 10, N is more than or equal to 3, P is Q/4, and Q is the number of fast Fourier transform points required during OFDM modulation in an OFDM telemetry system;
(2) the underground communication board utilizes M repeated short training sequences to carry out data synchronization, utilizes N repeated long training sequences and adopts a variable-step LMS algorithm to adjust a weight vector of a time domain equalizer, namely, the LMS time domain equalizer is trained;
(3) the underground communication board transmits the data of the Nth sequence of the N repeated long training sequences after passing through the time domain equalizer to the ground communication board by using a specific channel to carry out 4QAM OFDM modulation;
(4) the ground communication board performs fast Fourier transform on the received Nth equalized long training sequence data and obtains pre-emphasis coefficients of all sub-channels in OFDM modulation;
(5) calculating by the ground communication board according to the pre-emphasis coefficients of the sub-channels obtained in the step (4) to obtain a new long training sequence E, and sending a training sequence B to the underground communication board, wherein the training sequence B comprises M repeated short training sequences C and N repeated long training sequences E;
(6) and (3) carrying out data synchronization by using M repeated short training sequences by the underground communication board, equalizing the N repeated long training sequences by using the LMS time domain equalizer obtained by training in the step (2), carrying out fast Fourier transform, calculating frequency domain equalization coefficients of each sub-channel, and completing pre-emphasis and equalization on the channel.
2. The FPGA channel pre-emphasis and equalization method based on the OFDM high-speed logging telemetry system according to claim 1, characterized in that: the step (1) specifically comprises the following steps:
step 1.1: the ground communication board FPGA stores a conjugate random sequence x with the length of Q and composed of 0,1 and-1 in a ROM1,x2,x3…xQPerforming a fast inverse Fourier transform, wherein only x1And xQ/2Is 0, the rest is 1 or-1, and a long training sequence D is obtained;
and 1.2, repeatedly sending M short training sequences C stored in the ROM by the FPGA of the ground communication board, repeatedly sending N long training sequences D obtained in the step 1.1 to the digital-to-analog conversion circuit and the driving circuit of the ground communication board, and sending the long training sequences D to the underground communication board through the logging cable.
3. The FPGA channel pre-emphasis and equalization method based on the OFDM high-speed logging telemetry system according to claim 1, characterized in that: the step (2) specifically comprises the following steps:
step 2.1: an analog-to-digital conversion circuit on the underground communication board converts an analog signal on the logging cable into a digital signal and sends the digital signal to an FPGA on the underground communication board;
step 2.2: the FPGA on the underground communication board sends the received signals into a P +1 stage shift register, and the data in each stage of shift register is a0,a2,a3…aP；
Step 2.3: computing energy sum in P +1 stage shift register data window in k clock period
Figure FDA0003271625790000021
Step 2.4: while calculating the correlation energy as a0aPSending the data into another P +1 stage shift register, wherein the data in each stage of shift register is c0,c2,c3…cP；
Step 2.5: calculating the sum of the correlation energies as E2(k)＝E2(k-1)+c0(k)-cP(k) A 1 is mixing E1(k) Delaying P +1 cycle later with E2(k) Synchronously outputting;
step 2.6: when E is1(k)>T1And E2(k)/E1(k)>T2And when lasting M times P clock cycles, representing that M short training sequences arrive, and sending the last N long training sequences following the short training sequences into an LMS time domain equalizer module, T1And T2Less than ideal E1(k) And E2(k)/E1(k) And is greater than E1(k) And E2(k)/E1(k) Half of (1);
step 2.7: the LMS time domain equalizer is of 17 stages, an ideal long training sequence d '(k) is read from a downhole communication board ROM while the received long training sequence d' (k) is input, and the received long training sequences are respectively r 'in 17 stages of shift registers in the equalizer'1,r'2,r'3…r'17；
Step 2.8: the output of the LMS time-domain equalizer is
Figure FDA0003271625790000022
At the k clock cycleUpdate weight vector Wg(k) The formula is Wg(k)＝Wg(k-1)+μ(y(k)-d(k))rg' (k) when the 1 st long training sequence is input,. mu.2-10After N-2 long training sequences are input, mu is 2-14And mu multiplication is realized by data shift;
step 2.9: the LMS time-domain equalizer fixes the weight vector W after inputting N-1 repeated long training sequencesg(k) And outputting data after the weight vector is fixed and the Nth long training sequence is equalized, and completing the training of the LMS time domain equalizer.
4. The FPGA channel pre-emphasis and equalization method based on the OFDM high-speed logging telemetry system according to claim 1, characterized in that: the step (3) specifically comprises the following steps:
step 3.1: the underground communication board FPGA carries out 4QAM constellation coding on the Nth equalized long training sequence output by the LMS time domain equalizer;
step 3.2: and the underground communication board FPGA carries out OFDM modulation on the coded data by using a specific sub-channel with the frequency less than 50kHz, sends the coded data to the digital-to-analog conversion circuit and the driving circuit of the underground communication board, and sends the coded data to the ground communication board through the logging cable.
5. The FPGA channel pre-emphasis and equalization method based on the OFDM high-speed logging telemetry system according to claim 1, characterized in that: the step (4) specifically comprises the following steps:
step 4.1: the analog-to-digital conversion circuit of the ground communication board converts an analog signal on the logging cable into a digital signal and sends the digital signal to the FPGA on the ground communication board;
step 4.2: the ground communication board FPGA carries out OFDM demodulation and 4QAM constellation inverse coding on the signal to obtain data of the Nth balanced long training sequence sent by the underground communication board;
step 4.3: the ground communication board FPGA carries out fast Fourier transform on the Nth equalized long training sequence data to obtain e1,e2,e3…eQ；
Step 4.4: calculating to obtain pre-emphasis of each sub-channelCoefficient of
Figure FDA0003271625790000031
6. The FPGA channel pre-emphasis and equalization method based on the OFDM high-speed logging telemetry system according to claim 5, characterized in that: the step (5) specifically comprises the following steps:
step 5.1: calculating a pre-emphasized conjugate random sequence x according to the pre-emphasis coefficient obtained in the step (4)1,x2,x3…xQTo obtain
Figure FDA0003271625790000032
Step 5.2: to pair
Figure FDA0003271625790000033
Performing fast inverse Fourier transform to obtain a new long training sequence E;
step 5.3: the ground communication board FPGA repeatedly sends M short training sequences C stored in the ROM, and then repeatedly sends N obtained long training sequences E to the digital-to-analog conversion circuit and the driving circuit of the ground communication board, and the long training sequences E are sent to the underground communication board through the logging cable.
7. The FPGA channel pre-emphasis and equalization method based on the OFDM high-speed logging telemetry system according to claim 3, characterized in that: the step (6) specifically comprises the following steps:
step 6.1: an analog-to-digital conversion circuit on the underground communication board converts an analog signal on the logging cable into a digital signal and sends the digital signal to an FPGA on the underground communication board;
step 6.2: the FPGA on the underground communication board sends the received signals into a P +1 stage shift register, and the data in each stage of shift register is a0,a2,a3…aP；
Step 6.3: computing energy sum in P +1 stage shift register data window in k clock period
Figure FDA0003271625790000034
Step 6.4: while calculating the correlation energy as a0aPSending the data into another P +1 stage shift register, wherein the data in each stage of shift register is c0,c2,c3…cP；
Step 6.5: calculating the sum of the correlation energies as E2(k)＝E2(k-1)+c0(k)-cP(k) A 1 is mixing E1(k) Delaying P +1 cycle later with E2(k) Synchronously outputting;
step 6.6: when E is1(k)>T1And E2(k)/E1(k)>T2And when lasting M times P clock cycles, representing that M short training sequences arrive, and sending the last N long training sequences following the short training sequences into an LMS time domain equalizer module, T1And T2Less than ideal E1(k) And E2(k)/E1(k) And is greater than E1(k) And E2(k)/E1(k) Half of (1);
step 6.7: the LMS time-domain equalizer uses a weight vector Wg(k) Performing time domain equalization on the N long training sequences;
step 6.8: the FPGA of the underground communication board performs fast Fourier transform on the N long training sequences, and averages the N transformed results to obtain h1,h2,h3…hQ；
Step 6.9: the frequency domain equalization coefficient of each sub-channel obtained by FPGA calculation of the underground communication board is
Figure FDA0003271625790000041
And pre-emphasis and equalization of the channel are completed.
8. A system for realizing the FPGA channel pre-emphasis and equalization method based on the OFDM high-speed logging telemetry system, which is characterized by comprising the following steps: an aboveground communication board and a downhole communication board;
the ground communication board and the underground communication board are connected through a logging cable;
the ground communication board includes: the device comprises an FPGA, an ADC, a DAC, a driving circuit and a receiving circuit;
the downhole communication board includes: the device comprises an FPGA, an ADC, a DAC, a driving circuit and a receiving circuit;
the FPGA is used for signal synchronization, time domain equalization, frequency domain equalization, pre-emphasis and calculation of response parameters; the DAC inputs digital signals from the FPGA, converts the digital signals into analog signals, outputs the analog signals to the driving circuit for amplification, and transmits the analog signals to the underground/aboveground communication board through the logging cable by the aboveground/underground communication board; the receiving circuit amplifies the signals transmitted to the underground/underground communication board by the underground/underground communication board, filters the signals and sends the signals into the ADC, and the analog signals are converted into digital signals and then output to the FPGA for processing;
the ground communication board FPGA and the underground communication board FPGA comprise: the device comprises a long training sequence ROM module, a short training sequence ROM module, a Fourier transform module, an inverse Fourier transform module, an LMS time domain equalizer module, a pre-emphasis module, a frequency domain equalization module, a synchronization module and respective control logic modules;
the long training sequence ROM module is used for storing a conjugate random sequence required by generating a long training sequence; the short training sequence ROM module is used for storing a short training sequence; the Fourier transform module is used for converting the time domain signal on the cable into a frequency domain signal so as to calculate the parameters of the pre-emphasis module and the frequency domain equalization module; the inverse Fourier transform module is used for generating a long training sequence and converting the frequency domain signal into a time domain signal; the LMS time domain equalizer module is used for carrying out time domain equalization at a receiving end; the pre-emphasis module is used for carrying out frequency domain equalization at a sending end; the frequency domain equalization module is used for carrying out frequency domain equalization at a receiving end; the synchronization module is used for identifying the received signals and synchronizing data; the control logic module of the ground communication board FPGA is used for calculating pre-emphasis coefficients and controlling the ground communication board ADC and DAC; and the control logic module of the underground communication board FPGA is used for calculating the weight vector and the frequency domain equalization coefficient of the LMS time domain equalizer module and controlling the ADC and the DAC of the underground communication board.
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